JPH03153122A - Level conversion circuit - Google Patents

Abstract

PURPOSE:To improve the operating speed and to suppress an input standby current by connecting two CMOS inverters using a high level power supply line and a low level power supply line in common in multi-stage, and inserting an N-channel MOS transistor(TR) between a pre-stage inverter and the high level power supply line. CONSTITUTION:A first stage CMOS inverter 13 comprising a P-channel MOS TR T11 and an N-channel MOS TR T12 and a next stage CMOS inverter 14 comprising a P-channel MOS TR T13 and an N-channel MOS TR T14 in multi- stage, an N-channel MOS TR T15 is connected between the TR T11 and the high level power supply line VCC the gate of the TR T15 is connected to the source VC and the drains of the TRs T12, T14 are connected to an L level power supply line VSS and the source of the TR T13 is connected to the VCC. A high level output logic of the 1st stage CMOS inverter 13 is supplied as a level decreased from the VCC by the threshold level of the TR T15, the transition time of the 1st stage CMOS inverter 13 to a high level is quickened and the input standby current is suppressed.

Description

[Detailed Description of the Invention] [Summary] Regarding a level conversion circuit that converts a TTL level signal to a CMOS level signal, the present invention aims to improve operating speed and suppress input standby current. Two CMOS inverters that share a common side power line are connected in multiple stages, and the CMOS in the previous stage
N-channel MO3 between the inverter and the high potential side power supply line
It is characterized in that it is connected via an I-transistor, and the gate of the N-channel MO3) transistor is connected to a high-potential side power supply line.

(Industrial Application Field) The present invention relates to a level conversion circuit, and particularly to a level conversion circuit that converts a TTL level signal into a CMOS level signal.

In recent years, the speed limit of LSIs that use TTL input/output has been pointed out. In particular, the limits of speed increases are becoming apparent in LSIs that handle high-speed signal frequencies, such as microprocessors.

This is because, as the frequency used has become higher, the shadow of noise caused by TTL switching noise, reflections, strokes, etc. can no longer be ignored. Therefore, instead of using TTL input/output as is, it is used after converting it to a CMOS rail signal.

[Prior Art] FIG. 4 shows an example of a level conversion circuit used in a TTL input/output LSI. , and the low potential side (hereinafter,
CMOS inverter 1 and P-channel MO3!・Langister T
Configure l by connecting one node. The input threshold characteristic of CM OS inverter 1 corresponds to TTI7 level, and T T
Depending on the logic state of the input signal S of Ll/bell, one of the pair of transistors T7.5 and T7.5 and T13 is turned on. For example, if T2 on the P channel side turns on,
The output signal S2 is T.

The node potential ■1 between and T, and this potential is T
, is the P channel, and the gate 1- of T1 is VSS
Since it is connected to , V+=Vcc.

[Problem to be solved by the invention]

However, in such a conventional level conversion circuit C1, the no-FW level of the CMOS inverter 1 is converted to VC.
Since the potential is the same as that of C, 1) the transition time of Sz to H level is 6. (e.g. Mo5V) up to -[-
This corresponds to the amount of time required, and there are points that need to be improved in terms of operating speed.

11) Furthermore, since the internal circuit is driven by S2 that has risen to almost VCC, the drive current becomes large, that is, the standby current at the input stage is large, which is another point that should be improved.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a level conversion circuit that improves operating speed and suppresses manual stand-up current.

[Failure to solve the problem]

In order to achieve the dual purpose, the present invention connects two CMOS inverters that share a high-potential side power line and a low-potential side power line in multiple stages, and connects the previous stage CMOS inverter and the high-potential side power line. and the N-channel Mo3t- transistor.
It is characterized in that it is constructed by connecting the transistor gate 1- to the high-potential side power supply line B.

[Function] In the present invention, the I (level output logic) of the first-stage CMOS inverter is given by a potential lower than the H-level power supply by the threshold of the N-channel Mo3t-transistor.

Therefore, the transition time of the first-stage CMOS inverter to Hl/Bell becomes faster, speeding up, and input stand-high current being suppressed.

(Example〕 Hereinafter, the present invention will be explained based on the drawings.

1 to 3 are diagrams showing one embodiment of a level conversion circuit according to the present invention.

In FIG. 1, 10 is an LSI, and 5ILO is a level conversion circuit 1 that converts the TTL level human input signal S, CM Os 1/Hel output signal S 2 'zy, .
1, and an internal circuit 12 having a CMOS configuration that operates in response to S2.

FIG. 2 is a diagram showing the configuration of the level conversion circuit 11, in which the level conversion circuit 11, P channel MO3) transistor T11
and N f-Yanel MO3) transistor T5. ．． The first stage consists of a CBIOS inverter 13, a P-channel MO3) transistor TI3 and an N-channel MOS transistor.
The next stage CMOS inverter 14 consisting of transistors T l /i is connected in multiple stages, and T + t of the first stage CMOS inverter 13 and the H level power line (high potential side power line) ■0. An N-channel Mo3t-transistor TIS is connected between these 1, 2, and 1. ■The gate of
. , and connect the drains of T12, ] and 14 of the first-stage CMOS inverter 13 and the next-stage CMOS inverter 14 to the L+/bevel source line (low potential side power supply line),.

and the next stage CMOS inverter 14.
Connect the Tin source to ■ and C.

In such a configuration, TII and T4. The node potential (2) between V and V is a potential lowered by a threshold value vth (generally 0.5V to 1.OV) of T'+s.

Therefore, when Tl+ of the first stage CMOS inverter 13 is turned on depending on the logic state of Sl, the first stage CMOS
The output level of the S inverter 13 transitions to V11, but this transition time is T2. It will be less by the amount of. That is, in FIG. 3, the output level of the first stage CMOS inverter 13 is L-+Hi! ! As shown in the figure, the level is ■, c
Since (2) is reduced by (2) from (2), the speed can be increased by the time Ld corresponding to the difference between (2) and (2) compared to the conventional case where the voltage rises to VCC. Furthermore, the drive current at the subsequent stage can also be reduced by the amount of V, and the input stand-up current can be suppressed.

[Effects of the Invention] According to the present invention, with the above configuration, the operating speed can be improved and input stand-up current can be suppressed.

[Brief explanation of the drawing]

1 to 3 are diagrams showing one embodiment of the level conversion circuit according to the present invention, FIG. 1 is a block diagram of an LSI to which the level conversion circuit is applied, and FIG. 2 is a specific example of the level conversion circuit. 3 is a diagram showing the output level characteristics of the first-stage CMOS inverter, and FIG. 4 is a diagram showing the configuration of a conventional level conversion circuit. VCC...H level power line (high potential side power line)
, VSS...L level power line (low potential side power line), T1. ...N-channel MOS transistor. 1O-LS 13: First-stage CMOS inverter vcc: H level power supply line V, .: L level power supply line A concrete configuration diagram of the level conversion circuit of the embodiment Fig. 1 Fig. 3 Fig. 3

Claims (1)

[Claims] Two CMOS inverters that share a high-potential side power line and a low-potential side power line are connected in multiple stages, and the CMOS in the previous stage
N-channel MOS between the inverter and the high potential side power supply line
1. A level conversion circuit characterized in that the N-channel MOS transistor is connected via a transistor, and the gate of the N-channel MOS transistor is connected to a high potential side power supply line.