JP3536442B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an input terminal provided with a MOS transistor for fixing a potential.

[0002]

2. Description of the Related Art FIG. 4 shows an example of a circuit according to the prior art.
Input terminal potential fixing MOS transistors 111 and 21
The buffering of the control signal of 0 has been performed by the two elements of the inverter 320 and the inverter 321 for outputting its inverted signal. However, as the chip size increases, the number of inputs / outputs increases, and it becomes necessary to drive a large number of pull-up and pull-down MOS transistors. For example, the parasitic capacitance of 200 pull-up / pull-down resistors and the signal wiring for transmitting the signal is several hundred p
In order to drive F to such a large load, a large layout area is required because a driving capability equivalent to that of an output cell that outputs a signal to the outside of the chip is required.

The withstand voltage between the source and drain of the NMOS transistor of a semiconductor device using a 0.7 μm submicron process for realizing a logic circuit with an operating voltage of about 3 to 5 V is about 12 V, which is a fine process. However, it tends to become lower as a result. The power supply voltage when performing quiescent current measurement or screening, which is a test test item for testers, is usually around 8V in an IC with a working voltage of 3V to 5V, considering the improvement in the accuracy of initial failure detection of transistors and the transistor breakdown voltage. A high voltage is applied.

Then, the VSS power supply inside the chip is vibrated by the circuit operation due to the influence of the inductance mainly parasitic on the lead frame and the gold wire forming the package and the transistor and the metal wiring forming the chip. The fluctuation of the power source is greatly affected by the output cells, and the fluctuation range becomes large in a state where the output cells having high driving capability are simultaneously changed. According to the simulation result under the condition that two output cells with high driving capability of 15 nH of package lead frame, IOL = 24 mA and VOL = 0.4 V are changed at the same time, and 100 pF which is the terminal capacitance of the tester is added to those outputs. , VSS inside the chip
The power supply line can swing about 3V in the negative direction at the maximum. In addition, when a control signal is input from the input control terminal 300 to control the on / off of the pull-up / pull-down resistor and the output of the inverter 320 is changed, the output of the inverter is a large load of several hundred pF and the package. Due to the influence of the inductance of the lead frame, the simulation result shows a swing of about 2V in the positive direction. Therefore, when the IC is tested at 8V, which is higher than the normal use voltage, the power supply voltage is 8V, the swing width of the VSS power supply line inside the chip is 3V, and the swing width of the output of the inverter 320 is 2V.
13V, which is the sum of V, constitutes the inverter 320.
It is between the source and drain of the OS transistor. Therefore, there is a risk that a voltage exceeding the withstand voltage is applied between the source and drain of the NMOS transistor and the NMOS transistor is destroyed. Since more outputs are switched in the actual chip, a larger VSS fluctuation than in this example occurs in the chip, and it is predicted that the VDD power supply in the chip will also swing to the positive side, which is higher. There was a potential difference and it was easy to cause this phenomenon.

Therefore, the buffering inverter is provided in all the input / output cells to take a measure to reduce the load.

FIG. 3 shows an example of a prior art of a potential fixing MOS transistor for an input terminal and a control circuit therefor, which is provided with the measures described above. Input potential fixing MOS transistor 11
By controlling 1.210, the input leak of the input cell can be measured, and the quiescent current of the IC can be easily measured, which greatly contributes to the quality improvement of the IC. ON / OFF of the MOS transistors 210 and 111 is controlled by a signal from the control signal input terminal 300. The signal applied to the input terminal 300 is input to the gate of the input potential fixing MOS transistor via the buffering inverters 212, 213, 112 and 113 provided in all the input / output cells. The operation of the potential fixing MOS transistor is off when the control signal input terminal is “High” and is on when the control signal input terminal is “Low”. When the MOS transistors 210 and 111 are turned on, the external input terminal 200 is fixed to "Low" and the external input terminal 100 is fixed to "High". When the control input terminal 300 receives no external input, the NMOS transistor 312 fixes the input terminal 300 to “Low” and the MOS transistors 210 and 111 are turned on.
・ The potential of 200 is fixed.

[0007]

However, in the prior art of FIG. 3, the IC having a structure in which a plurality of voltages are used as power supplies and each of the input / output cells is independently used as one of the power supplies is an IC. When applied to, it had the following problems. Using the circuit example shown in FIG. 3, the input / output cell CEL
A description will be given assuming that a voltage of 5V is supplied to L1 and CELL3, and a voltage of 3V is supplied to CELL2.

Inputting "Low" to the control signal input terminal 300, the potential fixing MOS transistor 111 at the input terminal is input.
-Set 210 to the ON state. At this time, the control signal buffering inverters 212 and 21 are connected in series.
The inputs of 3, 112, and 113, that is, the outputs of the preceding-stage inverters are respectively “High (5V)” and “Low (0
V) ',' High (3V), 'Low (0V),' H
high (5V) '. In the CMOS inverter circuit, when an intermediate potential between the ground voltage and the power supply voltage is input to the gate, a short circuit current flows in the inverter circuit. In the conventional example of FIG. 3, the inverter 213 is supplied with a 3V power source and connected to the next stage of the inverter 112.
Is supplied with a 5V power source. Therefore, the output voltage of the inverter 213 becomes 3V, and a short-circuit current flows through the inverter 112 which receives the signal as input and uses 5V as a power source, which accelerates quality deterioration due to heat generation, increases current consumption, and causes circuit due to power supply noise. There is a high risk of causing adverse effects on operation. Further, since the output waveform is unstable, the operation of the potential fixing MOS transistor 111 of the input terminal controlled by this signal becomes unstable, and it becomes difficult to reliably fix the potential of the input terminal.

Therefore, a method of removing the inverters 212 and 213 using a low voltage as a power source and buffering the control signal can be considered. However, when a 5V system control signal is input to the NMOS transistor 210 in the input / output cell that uses 3V as a power supply, the ON resistance value thereof is affected by the 5V system power supply. However, for the 5V power supply, there is a need to reduce the power supply voltage from 5V to 3V in order to reduce the operating voltage of the elements constituting the peripheral circuit and to cope with the PCMCIA interface of a personal computer.

The drain-source current value IDS in the saturation region of the NchMOS transistor is IDS = 1 / 2.multidot.
β · (VGS-VTH) squared, and the resistance value R at that time is R
= VIN / IDS Here, β is the gain coefficient of the MOS transistor, VGS is the gate-source voltage of the transistor, VTH is the threshold value of the transistor, and VIN is the input voltage applied to the input terminal. The ratio of the resistance values when 5V is input to the gate of the NMOS transistor that forms the pull-down resistor that fixes the input potential of the 3V input terminal and when 3V is input is R (5V) / R (3V ) =
{VGS (3V) -VTH} squared / {VGS (5V) -VTH}
Squared. For example, the threshold value of the transistor is 0.7
In the case of V, the pull-down resistance value input with 5V is about 0.3 times the pull-down resistance value input with 3V. Ideally, the pull-up / pull-down resistance value should change the input potential promptly for an effective input signal while considering the influence of external noise.
It is not desirable that the resistance value greatly fluctuates as in this example. Further, in order to prepare MOS transistors having optimum resistance values according to combinations of operating voltages of the respective models, it is necessary to prepare transistors of various sizes, which causes an increase in layout area.

Therefore, the present invention solves such a problem, and an object of the present invention is to input a voltage signal lower than the highest voltage to a signal buffering circuit for controlling an input potential fixing circuit. Prevents short-circuit current that occurs, realizes stable operation of the circuit and prevents deterioration of quality, and the pull-up / pull-down resistance of the input terminal that uses the low-side voltage as the power supply is optimal without being affected by the highest voltage. To realize the resistance value.

[0012]

[Means for Solving the Problems]

(Means 1) A logic region mainly formed in a central portion of the semiconductor chip for realizing a predetermined logic circuit, and a logic region formed around the logic region between the outside of the semiconductor chip and the logic circuit An input cell that handles input / output signals, or a peripheral area including an output cell or a bidirectional cell (hereinafter referred to as an input / output cell), and an input potential fixing circuit for fixing the input potential of the input cell or the bidirectional cell And a semiconductor device having input / output cells of a first power supply system having the highest potential and a second power supply system having a potential lower than that of the first power supply system, having at least two different potentials as power sources. In the second aspect, the input potential fixing circuit control signal buffering circuit is provided only in the input / output cell of the first power supply system.

(Means 2) The first power supply system is used as a power supply in a power supply cell which is formed in the same peripheral area as the input / output cell and which supplies power supplies having different potentials from the outside to the inside of the semiconductor device. It is characterized by including a buffering circuit.

(Means 3) A logic region mainly formed in a central portion of the semiconductor chip for realizing a predetermined logic circuit, and a logic region formed around the logic region, outside the semiconductor chip and the logic circuit. An input cell for handling input / output signals between, or a peripheral area including an output cell or a bidirectional cell (hereinafter referred to as an input / output cell) and an input for fixing the input potential of the input cell or the bidirectional cell An input / output cell of a first power supply system which has a potential fixing circuit and uses at least two different potentials as power supplies and which has the highest potential and a second power supply system which has a lower potential than the first power supply system. In a semiconductor device having, the buffering circuit output,
At least one or more inversions in which the same power supply as that of each input / output cell is supplied between it and the control input of the input potential fixing circuit built in the input / output cell using the second power supply system as the power supply. It is characterized by having a logic element.

(Means 4) The buffering circuit according to the means 1 to 3 is a normal logic circuit constituted by at least two or more inverting logic elements.

(Means 5) The outputs of the buffering circuits described in the means 1 to 4 are connected to the buffering circuits which are arranged closest to each other in the same direction, and on the peripheral area which constitutes an input / output cell. It is characterized in that it is a multi-stage series connection circuit of inverters that go around.

[0017]

In the means 1 and 2, the buffering of the signal for controlling the input potential fixing circuit is performed only by the inverter having the highest voltage as the power source, so that the short circuit current due to the buffering signal of the voltage lower than that is applied. It is possible to prevent the occurrence and to realize the stable operation of the circuit.

In the means 3, the high voltage control signal is stepped down by the inverter using the low voltage as the power source,
It is possible to fix the on-resistance value of the input potential fixing MOS transistor only with a low voltage power supply.

[0019]

1 shows an embodiment of an input potential fixing circuit according to the present invention, and FIG. 2 shows an overall chip layout showing the arrangement of input / output cells and power supply cells at that time. In FIG. 1, the input potential fixing circuit includes a pull-up / pull-down control terminal 300, inverters 310, 331, 332, 112, 113 for buffering the signal and a potential fixing MOS for inputting the buffered control signal.
It includes a transistor 111, inverters IN21 and IN22 for lowering the voltage level of the control signal, and a potential fixing MOS transistor 210 controlled by the signal. By inputting “Low” to the control terminal 300, the input potential fixing MOS transistors 111 and 210 are turned on, and the potentials of the input terminals 100 and 200 are fixed. By inputting “High” to the control terminal 300, the input potential fixing MOS transistors 111 and 210 are turned off. This allows the input terminal 100
And 200 input leaks can be inspected
It becomes possible to suppress the current flowing into the pull-up resistor and pull-down resistor, which is a problem when measuring the quiescent current of, and the quiescent current selection test can be easily performed.

In the embodiment of FIG. 1, the input cells CELL1.
The first cell power supply 5V is supplied to the CELL3, and the input cell CE
The second system power supply 3V is supplied to LL2. Power cell P
The OWER1 is configured in the same peripheral region as the input / output cell and has a role of supplying some positive power supplies such as a negative power supply, a first power supply and a second power supply, which are externally supplied, to the inside of the semiconductor device. It is a cell that has, and there is no problem with a power supply of either polarity. When “Low” is input to the control terminal 300, the output 313 of the inverter 332 becomes “High” via the inverters 310 and 331 which are built in the power supply cell POWER1 and use the first system power supply as a power supply. In the IO cell CELL2, which is powered by the adjacent second system power source, buffering is not performed and the through is performed by the metal wiring.
It is input to the inverter 112 built in CELL3, which is the IO cell next to it, and is output from the output 131 as'Lo.
w'is output. The power supply voltage of the inverter 332 is 5V
Therefore, 5V'High 'is output from the output 313. The PMOS transistor forming the inverter 112 that receives the signal is completely turned off, and a short current does not flow. Therefore its output 131
Does not become an intermediate potential, and becomes a stable'Low 'level signal, and a stable ON state of the MOS transistor 111 controlled by the output signal 131 is realized. Therefore, the on-resistance value of the MOS transistor 111 becomes a value having a certain variation determined by the transistor size and the power supply voltage, and the potential of the input terminal 100 can be fixed with stable electrical characteristics, and the short current causes It is possible to avoid the risk of circuit malfunction due to noise or power supply voltage drop.

Next, the circuit operation of the second system power supply side will be described. The inverter IN21 outputs "Low" when receiving the 5V "High" level signal 313, and the output signal 222 of the next-stage inverter IN22 outputs 3V "High" which is the same as the supplied power supply voltage. Input terminal potential fixing MOS transistor 21 controlled by control signal 222
0 is turned on, and the input terminal 200 is fixed at the'Low 'level. In this way, the inverter IN21 ・ IN
22 performs a level shift function of step-down converting the signal 313 of 5V amplitude into the signal 222 of 3V amplitude. A control signal for the MOS transistor 210 is always a signal having the same amplitude as the second system power supply voltage, regardless of the power supply voltage of the first system power supply, which is the higher voltage. Therefore, the factors that determine the on resistance value of the MOS transistor 210 are only the transistor size and the power supply voltage of the second system, and are not affected by other power supplies. Therefore, it is not necessary to change the size of the MOS transistor 210 or change the peripheral circuits even if the power supply voltage of the first system is lowered in the future. Also, the first
Even in applications where the voltage of the system power supply is raised or lowered within the voltage range of the second system power supply, there is no fluctuation in the pull-up / pull-down resistance value of the second system power supply, so that consistency with peripheral circuits can be easily taken. Is possible.

In a semiconductor device, such as a gate array or an embedded array, which realizes a logic circuit by switching wirings using prefabricated transistors, inverters IN21, IN22, 331, 332, 112.
By separating the well of the PMOS transistor for forming 113 from other transistors and preparing a layout in which the sub-potential can be changed, it is possible to configure an inverter that uses a voltage of 3 V or 5 V as a power source by switching wiring. Therefore, it is not necessary to separately prepare transistors, and it is possible to suppress an increase in layout area.

FIG. 2 shows an overall chip layout showing the arrangement of input / output cells and power supply cells according to the present invention. The control signal from the control input terminal of the input potential fixing circuit provided in CELL1 shown in FIG. 2 is rotated counterclockwise from CELL1 to POWER1 by the buffering circuit as shown in FIG.
CELLn through CELL2, CELL3, and CELL4
And travels around the peripheral area of the semiconductor device. Then, the control signals are buffered by the buffering inverters formed in the input / output cells of the first system power supply and in the power supply cells. In this example, the input cell CELL1 having the control input terminal is arranged at the upper left corner of the chip, but it can be arranged at any position on the peripheral region of the semiconductor device.
Regarding the propagation direction of the control signal, there is no problem whether it is clockwise or counterclockwise. Inverter 331 for buffering
・ Inverter circuit row 1 including 332, 112, 113, etc. and level shift inverters IN21, IN22, etc.
The 0s are arranged so as to go around the chip, and the pull-up / pull-down resistors of all input circuits can be controlled by only one terminal. As shown in FIG. 1, if an even number of inverters are inserted in the input / output cells and the power supply cells on the side of the first system power supply, the inverter circuit array 10 is built in the input / output cells of the first system power supply. It can be used to control both pull-up and pull-down resistors.

In the example shown in FIGS. 1 and 2, since the cell 3 is the input cell of the first system power supply, the control signal of the input potential fixing circuit is buffered, but the inverter in the power supply cell performs the buffering. No, CELL4
When all the subsequent input / output cells are the input / output cells of the second system power supply, the buffering inverter in CELL3 drives all the remaining potential fixing circuits, and an excessive load is applied to this buffering inverter. It will take. On the other hand, for the purpose of ensuring stable operation of the circuit and supplying current to the output cell, the power supply cell for supplying the power supplied from the outside to the inside of the semiconductor device is the POWER1.
Since it is common to arrange an equal and sufficient number on the entire semiconductor chip as in the arrangement example of POWER2, POWER3, and POWER4, a buffering inverter should be provided in the power supply cell to buffer control signals. Thus, the parasitic capacitance and wiring inductance of the input potential fixing MOS transistor driven by the pair of buffering inverters can be reduced. Therefore, even if there is no input / output cell of the first system power supply after CELL4, buffering can be performed by the buffering inverter in the power supply cell, and there is a risk of destruction of the buffering inverter and a risk of disconnection of the control signal wiring. It plays a complementary role to avoid sex.

[0025]

According to the inventions described in Means 1 and 2, the buffering of the signal for controlling the input potential fixing circuit is constituted by the series connection circuit configuration of the inverter group using the highest voltage as the power source. It is possible to prevent the occurrence of short-circuit current that occurs when a signal of a lower voltage is input, and to realize stable operation of the circuit and prevention of quality deterioration.

According to the invention of the means 3, the control signal of a high voltage is stepped down by the inverter using the low voltage as a power source, and the circuit for controlling the ON / OFF of the input potential fixing MOS transistor is constituted, so that the low side is controlled. The pull-up / pull-down resistance of the input terminal that uses the voltage as the power source can realize the optimum resistance value without being affected by the highest voltage.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is an overall layout diagram of a chip according to an embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional technique.

FIG. 4 is a circuit diagram showing a conventional technique.

[Explanation of symbols]

10 ... Inverter circuit array 50 ... Semiconductor chip 51 ... Logic area 100, 200, 300, 301 ... Pad 111, 210 ... Input logic fixed circuit 112, 113, 320, 321, 331, 332, I
N21, IN22, 120, 121, 220, 221,
... Inverter circuits CELL1, CELL2 ... CELL (n-1), C
ELLn ... I / O cells POWER1, POWER2, POWER3, POWER
R4: Power cell

Claims (5)

(57) [Claims] 1. A logic area mainly formed in a central portion of a semiconductor chip for realizing a predetermined logic circuit, and a logic area formed around the logic area between the outside of the semiconductor chip and the logic circuit. Input cells that handle input and output signals with
Or at least two or more peripheral areas including output cells or bidirectional cells (hereinafter referred to as input / output cells) and an input potential fixing circuit for fixing the input potential of the input cells or bidirectional cells. Of the first power supply system having the highest potential and the second power supply system having a lower potential than the first power supply system as the power supply, A semiconductor device comprising the input potential fixing circuit control signal buffering circuit only in an input / output cell. 2. The first power supply system is used as a power supply in a power supply cell which is formed in the same peripheral region as the input / output cell according to claim 1 and which supplies power supplies having different potentials from the outside to the inside of the semiconductor device. A semiconductor device comprising the buffering circuit described above. 3. A logic area mainly formed in a central portion of the semiconductor chip for realizing a predetermined logic circuit, and a logic area formed around the logic area between the outside of the semiconductor chip and the logic circuit. Input cells that handle input and output signals with
Or at least two or more peripheral areas including output cells or bidirectional cells (hereinafter referred to as input / output cells) and an input potential fixing circuit for fixing the input potential of the input cells or bidirectional cells. Of the first power supply system having the highest potential and the second power supply system having a lower potential than the first power supply system, the buffering circuit output and , At least one or more of the same power supply as each input / output cell is supplied between the input / output cell and the control input of the input potential fixing circuit formed in the input / output cell using the second power supply system as a power supply. A semiconductor device having an inverting logic element. 4. A semiconductor device, wherein the buffering circuit according to any one of claims 1 to 3 is a non-inverting logic circuit composed of at least two or more inverting logic elements. 5. The buffering circuit output according to any one of claims 1 to 4 is connected to the buffering circuit which is arranged closest in the same direction, and on the peripheral region which constitutes an input / output cell. A semiconductor device, which is a multi-stage series connection circuit of inverters that make a round.