CN116718901B - Anti-fuse FPGA high-speed test circuit - Google Patents
Anti-fuse FPGA high-speed test circuit Download PDFInfo
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31704—Design for test; Design verification
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31705—Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
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- G—PHYSICS
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31719—Security aspects, e.g. preventing unauthorised access during test
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses an anti-fuse FPGA high-speed test circuit, which relates to the field of integrated circuits and comprises a test acquisition module and a test output module. The test acquisition modules are distributed in wiring resources on the anti-fuse FPGA chip and comprise an open drain output NMOS tube and a switch MOS module, and the output of the logic module and/or the IO module can be acquired and tested singly or in batches through the switch MOS module. The test output module comprises a phase inversion PMOS tube unit and a pull-down resistor unit which are mutually coupled, and the low level 0 and the high resistance output by the test acquisition module are converted into normal high and low logic levels. The invention can realize single or batch test of any logic module and/or IO module output inside the chip, and is convenient for users to debug and design. And after the user completes debugging, the special anti-fuse can be programmed, so that the test circuit is invalid, the internal node cannot be read, and the design safety is ensured.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to an anti-fuse FPGA high-speed test circuit.
Background
The anti-fuse FPGA is a one-time programmable device of a basic unit anti-fuse, design data is written into a chip for programming, so that user design can be realized, and the data is not lost after one-time programming. The anti-fuse FPGA can be programmed only once, and the internal node of the anti-fuse chip, especially the output of an important logic module and/or an IO module, needs to be ascertained, and the original output point signal needs to be tested, so the anti-fuse FPGA needs to design an on-chip test circuit, output the internal node signal to a specific test port of the anti-fuse FPGA, and realize the real-time debugging requirement.
Referring to the prior art of fig. 1, corresponding node signals are directly collected at output ports of a logic module and/or an IO module, and then signals of a node selected from a logic array and an IO array are output to a specific test port PO through selection of a row selection NMOS and a column selection NMOS, so as to obtain an original output of an internal array of the FPGA. However, since the antifuse array extends over almost the entire chip, the total length of the metal lines through which the test signals pass may be greater than the chip length and width, and the threshold voltage loss caused by the through holes, the row selection NMOS and the column selection NMOS is added, and a plurality of driving buffers must be added to the test path to enhance the driving capability, and these additional driving buffers increase the chip layout area due to the increase of the array modules. In addition, the distances from the output modules at different positions to the test port PO are different, and the number of driving buffers, parasitic capacitance and resistance of the signal transmission paths are different, so that the signal output speed is reduced, and meanwhile, the fan-out capability of the output of the logic module and/or the output of the IO module may be affected.
In summary, improvement of a circuit structure is urgently needed, and a test circuit which has a simple structure, does not increase logic resources, is high in speed and can detect the output value of a tested module in real time is designed.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and provides an anti-fuse FPGA high-speed test circuit which is used for detecting all logic modules and/or IO module output nodes in an anti-fuse singly or in batches and outputting internal node signals to a specific port, so that the real-time debugging requirement of a user is met, and the anti-fuse FPGA high-speed test circuit is further suitable for on-chip screening and finished product testing of chips.
The aim of the invention is realized by the following technical scheme:
an anti-fuse FPGA high-speed test circuit is used for testing output signals of a logic module and/or an IO module, wherein the IO module is a data input or output port connected with a chip pin processing module PAD of the FPGA, and comprises a test acquisition module and a test output module:
the test acquisition module comprises an open drain output NMOS tube and a switch MOS module;
the grid electrode of the open-drain output NMOS tube is connected with the output end of the logic module and/or the IO module, the source electrode of the open-drain output NMOS tube is grounded, and the drain electrode of the open-drain output NMOS tube is connected with the switch MOS module;
the switch MOS module is used for connecting or disconnecting the drain of the switch drain output NMOS tube and the input port IN of the test output module, and the switch MOS module does not contain a load driving circuit;
the test output module comprises a cross-coupled phase-inversion PMOS tube unit and a pull-down resistor unit, wherein a source electrode of a first PMOS tube IN the cross-coupled phase-inversion PMOS tube unit is connected with a source electrode of a second PMOS tube and then is connected with a VCC power supply, a drain electrode of the first PMOS tube is connected with a grid electrode of the second PMOS tube and is connected with an input port IN, a grid electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube and is connected with an output port OUT, and one end of the pull-down resistor unit is connected with the grid electrode of the first PMOS tube and the other end of the pull-down resistor unit is grounded.
Further, the FPGA chip is provided with a row selection signal end and a column selection signal end; the switch MOS module of the test acquisition module comprises a column selection NMOS tube and a plurality of row selection NMOS tubes, the drain electrodes of the row selection NMOS tubes are connected with the drain electrodes of the opening and drain output NMOS tubes IN a one-to-one correspondence manner, the source electrodes of the row selection NMOS tubes are connected with the drain electrodes of the column selection NMOS tubes, the source electrodes of the row selection NMOS tubes are connected with the input port IN of the test output module, the grid electrodes of the row selection NMOS tubes are connected with the row selection signal end, and the grid electrodes of the row selection NMOS tubes are connected with the column selection signal end.
Further, the FPGA chip is provided with a column selection enabling control end; the number of the column selection NMOS tubes is multiple, each column selection NMOS tube is connected with a plurality of row selection NMOS tubes, the switch MOS module further comprises a plurality of column selection enabling NMOS tubes, the drain electrodes of the column selection enabling NMOS tubes are connected with the drain electrodes of the column selection NMOS tubes in a one-to-one correspondence mode, the source electrodes of the column selection NMOS tubes are grounded, and the grid electrodes of the column selection enabling NMOS tubes are connected with column selection enabling signal ends.
Further, the test acquisition module also includes an anti-fuse point for connecting the output signals of the logic module and/or the IO module to ground after programming is blown through.
Further, the FPGA chip is also provided with an enable end OEN; the test output module further comprises a third PMOS tube, wherein a grid electrode of the third PMOS tube is connected with an enable end OEN, a drain electrode of the third PMOS tube is respectively connected with a source electrode of the first PMOS tube and a drain electrode of the second PMOS tube, and a source electrode of the third PMOS tube is connected with the VCC power supply.
Further, the test output module further comprises a first inverter, a second inverter and a buffer, wherein the input end of the first inverter is connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube respectively, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the buffer, and the output end of the buffer is connected with the output port OUT.
Further, the FPGA chip is provided with a debugging end A; the pull-down resistor unit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, the other end of the first resistor is respectively connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube, and the other end of the fourth resistor is grounded;
the drain electrode of the first NMOS tube is connected with the fourth resistor, the source electrode of the first NMOS tube is grounded, the drain electrode of the second NMOS tube is connected between the third resistor and the fourth resistor, the source electrode of the second NMOS tube is grounded, the drain electrode of the third NMOS tube is connected between the second resistor and the third resistor, the drain electrode of the fourth NMOS tube is connected between the first resistor and the second resistor, the source electrode of the fourth NMOS tube is grounded, the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a debugging end A, the debugging end A is used for inputting a switch control signal, and the switch control signal is used for gating one of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
Preferably, the pull-down resistor unit further comprises a 2-4 decoder, wherein the input of the 2-4 decoder is connected with the debugging end A, and the output of the 2-4 decoder is respectively connected with the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
The beneficial effects of the invention are as follows:
1) The test circuit module processes the collected high resistance state and low level by using the design of the cross-coupled phase-inversion PMOS tube, has the characteristics of high level state conversion speed and simple circuit structure, and improves the test efficiency.
2) Through the line and the characteristic of the open-drain output, whether the logic module and/or the IO module outputs low level or not can be tested in a large batch, so that the testing efficiency is improved, and meanwhile, the testing circuit can be used for chip screening and finished product testing, and is beneficial to improving the yield in chip production.
3) The debugging end is designed, so that a user can make a certain degree of trimming on the chip.
4) After the user debugging is finished, the specific anti-fuse point can be programmed, so that the test circuit is disabled, the internal node signal cannot be detected, and the design safety of the user is ensured.
Drawings
FIG. 1 is a schematic diagram of a logic module and/or IO module array direct-reading test circuit;
FIG. 2 is a schematic diagram of a test acquisition module according to the present invention;
FIG. 3 is a schematic circuit diagram of the test output module according to the present invention.
Detailed Description
The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by a person skilled in the art without any inventive effort, are intended to be within the scope of the present invention, based on the embodiments of the present invention.
Referring to fig. 1-3, the present invention provides a technical solution:
the basic unit antifuse of the antifuse FPGA is a one-time programmable device, data is not lost any more only by one-time programming, and a design bit stream for realizing functions is not required to be loaded from an external memory, and the design bit stream comprises a logic module, wiring resources, an IO module, a clock network, a control module, a test programming circuit, a safety/identification verification circuit, a charge pump and the like. The configurable module, the wiring resource and the antifuse array form an antifuse core; the IO module is externally connected with a chip pin processing module PAD and is a port for inputting or outputting a chip; the control module and the test programming circuit are used for chip test and chip programming. In the antifuse FPGA, a schematic diagram of a test circuit for directly reading the output of a logic module and/or an IO module array is shown in fig. 1.
As shown in fig. 2, an antifuse FPGA high-speed test circuit is configured to test output signals of a logic module and/or an IO module, where the IO module is a data input or output port connected to a chip pin processing module PAD of an FPGA, and the test circuit includes a test acquisition module and a test output module on an FPGA chip, where the FPGA chip has an output port OUT;
the test acquisition module comprises open drain output NMOS transistors N1 and N3 and a switch MOS module;
the gates of the open-drain output NMOS transistors N1 and N3 are connected with the output end of the logic module and/or the IO module, the sources of the open-drain output NMOS transistors N1 and N3 are grounded, and the drains of the open-drain output NMOS transistors N1 and N3 are connected with the switch MOS module;
the switch MOS module is used for connecting or disconnecting the drain of the switch drain output NMOS tube and the input port IN of the test output module, and the switch MOS module does not contain a load driving circuit;
the test output module comprises a cross-coupled phase-inversion PMOS tube unit and a pull-down resistor unit, wherein a source electrode of a first PMOS tube P1 IN the cross-coupled phase-inversion PMOS tube unit is connected with a source electrode of a second PMOS tube P2 and then is connected with a VCC power supply, a drain electrode of the first PMOS tube P1 is connected with a grid electrode of the second PMOS tube P2 and is connected with an input port IN, a grid electrode of the first PMOS tube P1 is connected with a drain electrode of the second PMOS tube P2 and is connected with an output port OUT, and one end of the pull-down resistor unit is connected with a grid electrode of the first PMOS tube P1 and the other end of the pull-down resistor unit is grounded.
Output signals of the logic module and/or the IO module are directly connected with an open drain output NMOS tube N1 to form an open drain OD circuit, so that the signal output states only have two states: high resistance and low. And then, using a cross coupling structure formed by the first PMOS tube P1 and the second PMOS tube P2 to process the acquired high resistance state and low level, and finally outputting logic level values of 0V and 5V from the ports. The level state switching circuit has the characteristics of high level state switching speed and simple circuit structure.
The test acquisition module is shown in fig. 2, and the FPGA chip is provided with a row selection signal end and a column selection signal end; IN this embodiment, the switch MOS module of the test collection module includes a column selection NMOS N5 and a plurality of row selection NMOS N2 and N4, where the drain of each row selection NMOS is connected to the drain of each open-drain output NMOS IN a one-to-one correspondence manner, the source of each row selection NMOS is connected to the drain of the column selection NMOS, the source of each column selection NMOS is connected to the input port IN of the test output module, the gate of each row selection NMOS is connected to the row selection signal terminal, and the gate of each column selection NMOS is connected to the column selection signal terminal.
The FPGA chip is provided with a column selection enabling control end; the number of the column selection NMOS tubes is multiple, each column selection NMOS tube is connected with a plurality of row selection NMOS tubes, the switch MOS module further comprises a plurality of column selection enabling NMOS tubes, such as NMOS tubes N6 and N8 in FIG. 2, the drain electrodes of the column selection enabling NMOS tubes are connected with the drain electrodes of the column selection NMOS tubes in a one-to-one correspondence manner, the source electrodes of the column selection enabling NMOS tubes are grounded, and the grid electrodes of the column selection enabling NMOS tubes are connected with a column selection enabling signal end.
The output value of the full-chip logic module and/or the output value of the IO module are acquired without the open-drain output of the pull-up resistor, so that the output load of the logic module and/or the IO module is reduced, and the chip area is saved. The open drain output has the characteristics of line and, so that whether the logic module and/or the IO module outputs low level or not can be tested in a large batch, and the testing efficiency is improved.
The test acquisition module also comprises an anti-fuse point, wherein the anti-fuse point is used for connecting output signals of the logic module and/or the IO module to ground after programming is melted. In this embodiment, the antifuse dots AF are respectively connected in parallel to two ends of the drain and source of the column selection enable NMOS. After user debugging is finished, the special anti-fuse can be programmed, so that a test circuit is invalid, an internal node cannot be read, and the design safety is ensured.
The test output module is shown in fig. 3, and in this embodiment, the FPGA chip further has an enable end OEN; the test output module further comprises a third PMOS tube P3, wherein a grid electrode of the third PMOS tube is connected with an enable end OEN, a drain electrode of the third PMOS tube is respectively connected with a source electrode of the first PMOS tube and a drain electrode of the second PMOS tube, and a source electrode of the third PMOS tube is connected with the VCC power supply. By controlling the enabling signal, the test output module can be started and stopped.
In addition, the test output module further comprises a first inverter I1, a second inverter I2 and a buffer I3, wherein the input end of the first inverter is respectively connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the buffer, and the output end of the buffer is connected with the output port OUT. The signal can be shaped by the same-direction series connection of the first inverter and the second inverter, so that the signal becomes standard level signal output; the buffer can enhance the driving capability of the signal.
In this embodiment, the FPGA chip has a debug terminal a; the pull-down resistor unit comprises a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first NMOS tube N21, a second NMOS tube N22, a third NMOS tube N23 and a fourth NMOS tube N24, wherein the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, the other end of the first resistor is respectively connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube, and the other end of the fourth resistor is grounded; the resistance value of the first resistor is set to be K omega magnitude and R1; the second to fourth resistors have smaller resistance values, and the resistance values are set to be R. It should be noted that the number of resistors connected in series to the pull-down resistor unit is not limited to four, and the accurate regulation of the node voltage value can be further completed by using a series-parallel structure of two or more resistors. The level at the connecting node (node N) of the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube can be regulated and controlled by connecting a plurality of resistors, so that the stable high level can be output under specific conditions.
The drain electrode of the first NMOS tube is connected with the fourth resistor, the source electrode of the first NMOS tube is grounded, the drain electrode of the second NMOS tube is connected between the third resistor and the fourth resistor, the source electrode of the second NMOS tube is grounded, the drain electrode of the third NMOS tube is connected between the second resistor and the third resistor, the drain electrode of the fourth NMOS tube is connected between the first resistor and the second resistor, the source electrode of the fourth NMOS tube is grounded, the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a debugging end A, the debugging end A is used for inputting a switch control signal, and the switch control signal is used for gating one of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
As shown in FIG. 3, the pull-down resistor unit further comprises a 2-4 decoder, wherein the input of the 2-4 decoder is connected with the debugging end A, and the output of the 2-4 decoder is respectively connected with the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
The pull-down resistor unit controls the resistance value of the access circuit through the on-off of the NMOS tube so as to further adjust the level at the connection node (node N) of the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube. The test value is manually set by a tester and is input into a 2-4 decoder, four paths of control signals output by the 2-4 decoder are respectively connected to the grid electrodes of the first NMOS tube to the fourth NMOS tube, when the value is 1, the NMOS tube is turned on, when the value is 0, the NMOS tube is turned off, the input of the 2-4 decoder is A <1:0>, the output is Z1<3:0>, and the truth table is shown in the following table 1.
Table 1 decoder truth table
As can be seen from Table 1, under normal conditions, only 1 of the first to fourth NMOS transistors are turned on, and the gate voltage of the NMOS transistor is high level 5V, the voltage between the source and drain is V DS Smaller, so they are in the linear region when on, and the current-voltage relationship satisfies the equation:
(1)
Wherein the method comprises the steps ofβIs the gain factor of the MOS,V GS is the gate-source voltage of the MOS tube,V T is the starting voltage of the MOS tube,I D is the current flowing from the drain electrode to the source electrode of the MOS tube.
The NMOS tube turned on at this time can be approximately an equivalent resistor R ON To reduce the quiescent current, the total resistance R of the node N to GND is derived 2 The following relationship is provided:
n21 on: r is R 2 =R1+3R +R ON
N22 guideAnd (3) communication: r is R 2 =R1+2R +R ON
N23 on: r is R 2 =R1+1R+R ON
N24 on: r is R 2 =R1+R ON
In the present embodiment, the total resistance R from node N to GND can be adjusted by gating the NMOS transistor 2 Causing node N to output a high level.
When the anti-fuse FPGA test circuit detects the output of a certain module or a specific node in the array, only the row-column coordinates of the anti-fuse FPGA test circuit are needed to be determined, the corresponding row NMOS tube and the corresponding column NMOS tube are selected to be opened, and the output of a single module or node is detected; for example, IN fig. 2, two NMOS transistors N2 and N5 are turned on, and the column selection enabling MOS transistor N6 is kept turned off, so that the output signal of the logic module/IO module 1 can be input to the IN end of the test output module.
The output principle of the antifuse FPGA test circuit detection logic module and/or the IO module is as follows:
IN the test acquisition module, when the output of the logic module/IO module is at a low level, the open drain output NMOS tube is closed, the drain end of the open drain output NMOS tube outputs wiring resources IN a high resistance state, and the input of the open drain output NMOS tube to the IN end of the test output module is also IN a high resistance state; when the output of the logic module/IO module is high level, the open-drain output NMOS tube is conducted, the drain end of the open-drain output NMOS tube outputs low level to the wiring resource, and after the corresponding row selection NMOS tube is opened, the level input to the IN end of the test output module is the sum of the starting voltages of the corresponding NMOS tubes. As shown IN fig. 2, IN this embodiment, if the output of the logic module/IO module 1 is to be tested, the NMOS transistors N1, N2 and N5 are turned on, and the level input to the IN terminal is:
(2)
V thN1 、 V thN2 、 V thN5 The turn-on voltages of N1, N2 and N5, respectively.
And in the test output module, converting the low-level or high-resistance output in the test acquisition module into normal logic level output. When the value of the module enable end OEN is 1, the third PMOS tube is cut off, and as one of the first NMOS tube to the fourth NMOS tube is always in a conducting state, the level at the connecting node (node N) of the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube is pulled down to GND, the output end OUT outputs a high level, and the function of the test output module is forbidden at the moment; when the value of the module enable end OEN is 0, the third PMOS tube is conducted, the sources of the first PMOS tube and the second PMOS tube are connected to the power supply VCC, the test function of the test output module is normally used, and the following two conditions exist:
(1) When the IN end inputs a high resistance state, the level of the node N is pulled down to GND through the resistor because the IN end has no driving capability, the first PMOS tube rapidly charges a connection node (node M) of the drain electrode of the first PMOS tube and the grid electrode of the second PMOS tube, the level value of the node M is lifted, and the second PMOS tube is turned off, so that the node N outputs a low level. The buffer I3 enhances the driving capability through the shaping of the first inverter I1 and the second inverter I2, and finally outputs a low level to an OUT terminal;
(2) When the input of the IN end is low level, the level value of the node M is the sum of the starting voltages of the corresponding NMOS tubes, the IN end is connected to the grid electrode of the second PMOS tube, and the input impedance is very large, so that the level value of the node M is continuously pulled down to GND and is close to GND; at the moment, the second PMOS tube is conducted, the voltage of the node N is raised, the level value of the node N is raised, and the first PMOS tube is further turned off. The voltage of the node N is lifted by the second PMOS tube, and the balance is finally achieved through the increase of the resistance. At this time, the second PMOS transistor is also in the linear region, and the current-voltage relationship is:
(3)
(4)
Wherein the method comprises the steps ofβIs the gain factor of the MOS,V GS is the gate-source voltage of the MOS tube,V T is the starting voltage of the MOS tube,I D to flow from the drain of the MOS transistorThe current at the source electrode is such that,R 2 as the resistance of the node N to GND,V D is the voltage at node N. Current on node NI D Both equations 3 and 4 are required to be satisfied. By setting the resistance values of the first to fourth resistors, the node N is caused to output a high level. The buffer I3 enhances driving capability by shaping the first inverter I1 and the second inverter I2, and finally outputs a high level to the OUT terminal.
In summary, the signal output process is as follows:
the logic module/IO module outputs a low level, the output NMOS tube outputs a high resistance state, the IN end (node M) is a high level, the node N outputs a low level, and the OUT end outputs '0'.
The logic module/IO module outputs high level, the output NMOS tube outputs low level, the IN end (node M) is high level, the node N outputs low level, and the OUT end outputs '1'.
The logic output is switched between 0 and 1, the high-resistance state and the low-level state are output by the open drain, and the logic inversion process is realized by the positive feedback effect of the cross-coupled phase-inversion PMOS tube units and is much faster than the process of switching from 5V to 0V, so that the signal transmission speed can be improved.
The anti-fuse FPGA test circuit can also perform batch test on output signals according to the capability of open-drain output of 'line AND', wherein 'line AND' refers to that a plurality of signal lines are directly connected together, any one or a plurality of signals are low level, and the bus is low level; when all signals are in high resistance state, the signals are in high resistance state on the bus. For example, when the outputs of the array or the plurality of logic modules are all low, if the modules need to be detected, only the set channels and positions in the row selection NMOS tube and the column selection NMOS tube are required to be opened simultaneously, and the output lines and operations can be carried out through the open-drain output, and whether the outputs of the plurality of logic modules are low or not can be judged simultaneously. As shown in fig. 2, the row selection NMOS N4, and the column selection NMOS N5 are turned on at the same time, so as to detect whether the outputs of the two modules are at low level.
When the chip is screened and the finished product is tested, the internal logic module of the FPGA is repeated in a large scale, the output of the plurality of modules is set to be low level by utilizing the line and the characteristics of the open-drain output, the test circuit is used for testing whether the output is normal or not, and meanwhile, the output of a large number of modules is detected, so that the detection efficiency is obviously improved, and the yield in the chip production is improved. The test circuit occupies little resources, acquires the node signals to be tested through the open-drain structure, and is connected to the special output module, so that the test circuit which has a simple structure and high speed and can output in real time is realized.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and environments and is capable of modifications within the scope of the inventive concept, either as taught or as a matter of routine skill or knowledge in the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (8)
1. The anti-fuse FPGA high-speed test circuit is used for testing output signals of a logic module and/or an IO module, wherein the IO module is a data input or output port connected with a chip pin processing module PAD of the FPGA, and is characterized in that the test circuit comprises a test acquisition module and a test output module which are positioned on an FPGA chip, and the FPGA chip is provided with an output port OUT;
the test acquisition module comprises an open drain output NMOS tube and a switch MOS module;
the grid electrode of the open-drain output NMOS tube is connected with the output end of the logic module and/or the IO module, the source electrode of the open-drain output NMOS tube is grounded, and the drain electrode of the open-drain output NMOS tube is connected with the switch MOS module;
the switch MOS module is used for connecting or disconnecting the drain of the switch drain output NMOS tube and the input port IN of the test output module, and the switch MOS module does not contain a load driving circuit;
the test output module comprises a cross-coupled phase-inversion PMOS tube unit and a pull-down resistor unit, wherein a source electrode of a first PMOS tube IN the cross-coupled phase-inversion PMOS tube unit is connected with a source electrode of a second PMOS tube and then is connected with a VCC power supply, a drain electrode of the first PMOS tube is connected with a grid electrode of the second PMOS tube and is connected with an input port IN, a grid electrode of the first PMOS tube is connected with a drain electrode of the second PMOS tube and is connected with an output port OUT, and one end of the pull-down resistor unit is connected with the grid electrode of the first PMOS tube and the other end of the pull-down resistor unit is grounded.
2. The anti-fuse FPGA high-speed test circuit according to claim 1, wherein the FPGA chip is provided with a row selection signal end and a column selection signal end; the switch MOS module comprises a column selection NMOS tube and a plurality of row selection NMOS tubes, the drain electrodes of the row selection NMOS tubes are connected with the drain electrodes of the opening drain output NMOS tubes IN a one-to-one correspondence manner, the source electrodes of the row selection NMOS tubes are connected with the drain electrodes of the column selection NMOS tubes, the source electrodes of the column selection NMOS tubes are connected with the input port IN of the test output module, the grid electrodes of the row selection NMOS tubes are connected with the row selection signal end, and the grid electrodes of the column selection NMOS tubes are connected with the column selection signal end.
3. The anti-fuse FPGA high-speed test circuit according to claim 2, wherein the FPGA chip is provided with a column selection enabling control end; the number of the column selection NMOS tubes is multiple, each column selection NMOS tube is connected with a plurality of row selection NMOS tubes, the switch MOS module further comprises a plurality of column selection enabling NMOS tubes, the drain electrodes of the column selection enabling NMOS tubes are connected with the drain electrodes of the column selection NMOS tubes in a one-to-one correspondence mode, the source electrodes of the column selection NMOS tubes are grounded, and the grid electrodes of the column selection enabling NMOS tubes are connected with column selection enabling signal ends.
4. The anti-fuse FPGA high-speed test circuit of claim 1, wherein the test acquisition module further comprises an anti-fuse point for connecting the output signals of the logic module and/or the IO module to ground after programming is blown.
5. The anti-fuse FPGA high-speed test circuit according to claim 1, wherein the FPGA chip is further provided with an enable end OEN; the test output module further comprises a third PMOS tube, wherein a grid electrode of the third PMOS tube is connected with an enable end OEN, a drain electrode of the third PMOS tube is respectively connected with a source electrode of the first PMOS tube and a drain electrode of the second PMOS tube, and a source electrode of the third PMOS tube is connected with the VCC power supply.
6. The antifuse FPGA high-speed test circuit of claim 1, wherein: the test output module further comprises a first inverter, a second inverter and a buffer, wherein the input end of the first inverter is respectively connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube, the output end of the first inverter is connected with the input end of the second inverter, the output end of the second inverter is connected with the input end of the buffer, and the output end of the buffer is connected with the output port OUT.
7. The antifuse FPGA high-speed test circuit of claim 1, wherein: the FPGA chip is provided with a debugging end A; the pull-down resistor unit comprises a first resistor, a second resistor, a third resistor, a fourth resistor, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube, wherein the first resistor, the second resistor, the third resistor and the fourth resistor are sequentially connected in series, the other end of the first resistor is respectively connected with the grid electrode of the first PMOS tube and the drain electrode of the second PMOS tube, and the other end of the fourth resistor is grounded;
the drain electrode of the first NMOS tube is connected with the fourth resistor, the source electrode of the first NMOS tube is grounded, the drain electrode of the second NMOS tube is connected between the third resistor and the fourth resistor, the source electrode of the second NMOS tube is grounded, the drain electrode of the third NMOS tube is connected between the second resistor and the third resistor, the drain electrode of the fourth NMOS tube is connected between the first resistor and the second resistor, the source electrode of the fourth NMOS tube is grounded, the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube are respectively connected with a debugging end A, the debugging end A is used for inputting a switch control signal, and the switch control signal is used for gating one of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
8. The antifuse FPGA high-speed test circuit of claim 7, wherein: the pull-down resistor unit also comprises a 2-4 decoder, wherein the input of the 2-4 decoder is connected with the debugging end A, and the output of the 2-4 decoder is respectively connected with the grid electrodes of the first NMOS tube, the second NMOS tube, the third NMOS tube and the fourth NMOS tube.
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