CN106324474A - Testing burning system for anti-fuse FPGA - Google Patents

Abstract

The invention belongs to the field of integrated circuits, and relates to a testing system for an anti-fuse FPGA. In particular, the system does not aim at the testing burning of a finished anti-fuse FPGA but for the testing of an anti-fuse FPGA before chip flowing, and can find the hidden dangers of the anti-fuse FPGA circuit earlier. The system can provide more precise FPGA burn estimation through combining with the process of chip flowing after rear simulation. Meanwhile, the system can be compatible with a full series of FPGAs, and the system can greatly improve the success rate of chip flowing.

Description

A kind of for anti-fuse FPGA test programming system

Technical field

The invention belongs to integrated circuit fields, relate to a kind of anti-fuse FPGA test programming system, particularly It is that this programming system is not directed to finished product anti-fuse FPGA to carry out testing burning, but for antifuse Test before the non-flow of FPGA, the internal hidden danger existed of anti-fuse FPGA circuit can be found earlier.

Background technology

FPGA i.e. field programmable gate array, it is the base at programming devices such as PAL, GAL, CPLD The product of development further on plinth.It is as a kind of semi-custom electricity in special IC (ASIC) field Road and occur, both having solved the deficiency of custom circuit, overcoming again original programming device gate circuit number has The shortcoming of limit.Abundant interconnection resource, interconnection resource connection institute within FPGA is had inside fpga chip There is unit, and the length of line and technique decide signal driving force on line and transmission speed.

Traditionally, the application of FPGA to a great extent by Communications Market dominate, but along with industrial intelligent, Automotive circuit diagram and the development of Internet of Things, increase to the FPGA demand possessing flexible programmable characteristic.But Common FPGA can not bear the shock of high energy particle, it is impossible to reply military project, the most aerospace Stringent environmental.

So anti-fuse FPGA arises at the historic moment, antifuse FPG uses antifuse switch element, has volume Feature little, that chip area is little, low radioprotective is anti-interference, interconnection line characteristic impedance is low, it is not necessary to external PROM Or EPROM, after power down, the configuration data of circuit will not be lost, and gets final product work after powering on.Anti-fuse FPGA Technology is as a kind of electronic component in Aero-Space and national defense and military fields with strategic importance, its core skill Art is monopolized with research institution by some offshore companies for a long time.Some high-end models specializing in aerospace applications by In the most substantially having been bought by external blockade and embargo.Domestic existed some institutes and University is engaged in the research work of correlation technique, if there is hidden danger in chip design stage in domestic development, Flow can bring massive losses.

Summary of the invention

The present invention provides a kind of brand-new method of testing, to solve or to improve said one or multiple problem.

The present invention in view of the foregoing, designs a kind of test system for anti-fuse FPGA, this test System can after rear imitative end can in conjunction with the technique of flow more accurate FPGA burning being provided to estimate, Simultaneously this system can compatible complete series FPGA, and this system can largely improve the one-tenth of chip flow Merit probability.

The method of the embodiment of the present invention can simulate multiple spot burning situation in the case of true burning, and can obtain The functional test of chip after burning.Breach general emulation and can only simulate single-point burning situation, and cannot Obtain the functional test of chip after burning.High degree saves the R&D costs of anti-fuse FPGA.

Accompanying drawing explanation

In order to be illustrated more clearly that the embodiment of the present invention or technical scheme of the prior art, below will be to enforcement In example or description of the prior art, the required accompanying drawing used is briefly described.It should be evident that describe below In accompanying drawing be some embodiments of the present invention, for those of ordinary skill in the art, do not paying wound On the premise of the property made is laborious, it is also possible to obtain other accompanying drawing according to these accompanying drawings.

Fig. 1 is the system block diagram that the present invention tests programming system

Fig. 2 is that the present invention tests anti-fuse cell equivalent model in programming system

Fig. 3 is that the present invention tests internal burning channel pattern in programming system

Fig. 4 is according to first example principles figure of principle of the present invention

Fig. 5 is according to second example principles figure of principle of the present invention

Fig. 6 is according to the 3rd example principles figure of principle of the present invention

Detailed description of the invention

For making the purpose of the embodiment of the present invention, technical scheme and advantage clearer, below in conjunction with the present invention Accompanying drawing in embodiment, is clearly and completely described the technical scheme in the embodiment of the present invention, it is clear that Described embodiment is a part of embodiment of the present invention rather than whole embodiments.Based in the present invention Embodiment, those of ordinary skill in the art obtained under not making creative work premise all its His embodiment, broadly falls into the scope of protection of the invention.

Fig. 1 is the system block diagram that the present invention tests programming system.The embodiment of the present invention can be applicable to antifuse FPGA tests burning, for analyzing before FPGA flow.As it is shown in figure 1, the including of the present embodiment: refer to Make set 11, cd-rom recorder system 12, interface between software and hardware/signal source 13, complete band parasitic parameter circuit 14, Output result treatment 15.The survey of corresponding function after wherein instruction set 11 is responsible for offer burning bit stream or burning Examination waveform.Cd-rom recorder system 12 is the program under real cd-rom recorder, and this system is also used in the test after flow, Cd-rom recorder system 12 received the order of instruction set 11 carry out transcoding produce corresponding specific time sequence with Specific information of voltage, these information enters interface between software and hardware/signal source 13.Interface between software and hardware/signal source 13 These information are changed into the hardware description language that circuit is read-write, inputs complete band parasitic parameter circuit 14. Test etc. merit after completely band parasitic parameter circuit 14 completes burning or completes burning after receiving information above Energy.Output result 15 is a special output result treatment, can be automatically performed waveform than reciprocity function.

Fig. 2 is that the present invention tests anti-fuse cell equivalent model in programming system, and this equivalent model can mate Actual burn situation, and after burning, keep burn through characteristic.This characteristic is that traditional simulation cannot realize, Also it is the committed step to processing of circuit in this system.Keep the resistance of K ohm up to a hundred before its burn through, burn After logical, resistance is reduced to hundreds of ohm.

Fig. 3 is that to test in programming system internal burning channel pattern be that Fig. 1 inputs complete band parasitism ginseng to the present invention Antifuse burning access diagram under number circuit 14.Wherein anti-fuse cell is that Fig. 2 tests programming system Middle anti-fuse cell, row selects module to select module to be really by opening with row to controlled interface to controlled interface Close what metal-oxide-semiconductor controlled.Different condition is chosen, by interface between software and hardware/signal source 13 by switching switch metal-oxide-semiconductor Signal configured.Precharge holding pattern, all passage row select module and row to being subject to controlled interface Control interface selects module all to select VPP/2；Look into sky pattern, looked into anti-fuse cell place line and be switched to VPP, Alignment is switched to GND；Burning pattern, anti-fuse cell place to be burnt line is switched to VPP, and alignment is switched to GND, pulsed impacts this antifuse；Test pattern and dynamic test pattern after burning, all line alignments are cut Change to connect to logical block.

Fig. 4 is first example principles figure of principle of the present invention.This example is for looking into sky or burning before burning Pattern.Looking into sky pattern, first instruction set 11 sends burning environment self-inspection order, and cd-rom recorder system 12 receives After instruction, burning environment is performed the detection such as voltage and burning condition, detects by return instruction set 11, inspection Survey not by pointing out unsuccessfully；Being sent by then instruction set 11 and look into vacancy flow, cd-rom recorder system 12 receives and refers to After order, mix corresponding time sequential pulse and corresponding voltage to looking into vacancy flow, give interface between software and hardware/signal source 13； These are configured to input the input of complete band parasitic parameter circuit 14 correspondence by interface between software and hardware/signal source 13 Mouthful；Input complete band parasitic parameter circuit 14 local such as Fig. 4, if to look into empty red some position, each line Alignment selects VPP/2 voltage to carry out preliminary filling, and then the internal burning channel pattern of Fig. 3 breaks all lines row Line options, allows each line alignment keep VPP/2 voltage, again selects H05 line to add vpp voltage, select Left side V03 line adds GND；If red point is by burn through, then on H05 or left side V03 line, voltage cannot be protected Hold, without by burn through, then can keep.Burning pattern, first burning environment self-inspection, by self-inspection again by Instruction set 11 sends burning figure four fixing redness point bit stream, and it is right that cd-rom recorder system 12 is mixed after receiving bit stream Answering time sequential pulse and corresponding voltage to give interface between software and hardware/signal source 13, interface between software and hardware/signal source 13 is by this The input port that a little configurations are corresponding, the most corresponding left V03 controlled interface selects module to select GND, H05 to be subject to Control interface selects module to select VPP, applies pulse voltage until this fuse burn through.

Fig. 5 is according to second example principles figure of principle of the present invention.This example is for the functional test after burning. In burn through figure after all red signal points, could be configured as a phase inverter by blue basic logic unit. Instruction set 11 completes sending function test file after burning environment self-inspection, after cd-rom recorder system 12 receives Being configured to input waveform, these input waveforms are poured into complete band parasitic parameter electricity by interface between software and hardware/signal source 13 Road 14, wherein function input waveform arrives waveform input pin in Fig. 5, other waveforms complete whole instead The configuration of array of fuses, such as figure are configured to CLKA, VCC, GND, CLKB, such basic logic The output of the waveform output pin of unit output antifuse port is arrived on chip PAD, and output result 15 obtains This output, with built-in correct output contrast, the most then prompting is correct, and mistake then points out mistake.

Fig. 5 is according to the 3rd example principles figure of principle of the present invention.This example is for the dynamic test after burning. All anti-fuse FPGA all possess dynamic function test for the abnormal conditions after burning.Instruction set 11 Sending respective modules dynamic test bit stream, cd-rom recorder system 12 is configured to input waveform after receiving, software and hardware connects These input waveforms are poured into complete band parasitic parameter circuit 14 by mouth/signal source 13.Such as Fig. 5, corresponding bit stream can To open EN_YA, EN_YB or EN_XA, EN_XB in circuit.So the output of internal module is just Being connected to output port by dynamic test network, output result 15 can be obtained by test result.This pattern Dysfunction or internal network after diagnosis anti-fuse FPGA burning are of great importance.

Last it is noted that above example is only in order to illustrate technical scheme, rather than it is limited System；Although the present invention being described in detail with reference to previous embodiment, those of ordinary skill in the art It is understood that the technical scheme described in foregoing embodiments still can be modified by it, or to it Middle part technical characteristic carries out equivalent；And these amendments or replacement, do not make appropriate technical solution Essence departs from the spirit and scope of various embodiments of the present invention technical scheme.

Claims (1)

1. test programming system for anti-fuse FPGA for one kind, it is characterised in that including:

Corresponding bit stream enters circuit by cd-rom recorder system and interface between software and hardware/signal source；

Antifuse point can maintain corresponding burning characteristic after burning, and completes functional test；

Antifuse array channel accesses voltage or logical block interface by switch metal-oxide-semiconductor switching.