CN107134994A - Suitable for the design for testability circuit of anti-fuse type programmable gate array - Google Patents
Suitable for the design for testability circuit of anti-fuse type programmable gate array Download PDFInfo
- Publication number
- CN107134994A CN107134994A CN201710301292.6A CN201710301292A CN107134994A CN 107134994 A CN107134994 A CN 107134994A CN 201710301292 A CN201710301292 A CN 201710301292A CN 107134994 A CN107134994 A CN 107134994A
- Authority
- CN
- China
- Prior art keywords
- switching tube
- test
- antifuse
- circuit
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
- H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
- H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318516—Test of programmable logic devices [PLDs]
- G01R31/318519—Test of field programmable gate arrays [FPGA]
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The present invention provides a kind of design for Measurability structure suitable for anti-fuse type programmable gate array, belongs to microelectronics technology.The design for Measurability structure includes control circuit and at least one switch ways, each switch ways include the antifuse being arranged in parallel and test switching tube, the test switching tube is opened or closed by the control circuit control, after the test switching tube is opened, the antifuse is short-circuited, after the test switching tube is closed, the antifuse is enabled.The present invention tests switching tube by one in parallel by antifuse, the opening of test switching tube of the control circuit optionally in controlling switch path can be allow, so as to ensure in test phase, the antifuse short circuit corresponding to measurement circuit will be needed, in service stage, test switching tube is closed, antifuse is enabled, the test switching tube of closing does not interfere with signal transmission, will not introduce extra power consumption yet.
Description
Technical field
Invention belongs to microelectronics technology, is related to a kind of suitable for anti-fuse type programmable gate array (English：
Field-Programmable Gate Arra, referred to as：FPGA design for Measurability structure).
Background technology
Anti-fuse type fpga chip is a kind of FPGA electricity of this particular device of use antifuse as programming Control unit
Road, antifuse act as channel selector in circuit.
Antifuse is embedded between top layer and secondary top-level metallic, and antifuse medium exists in the form of similar through hole, due to
Antifuse dielectric layer electric conductivity is very poor, therefore under normal circumstances, the connection of antifuse through hole is in open-circuit condition.But pass through high pressure
Programming, the antifuse medium can be breakdown, and now antifuse medium can dissolve each other and turn on metal medium.So before programming,
Antifuse through hole is in open-circuit condition, and after programming, antifuse through hole is in the conduction state, here it is the operation principle of antifuse.
For anti-fuse type FPGA circuitry, as a result of antifuse as programming unit, therefore it has that area is small, work(
The features such as consuming fast low, speed, high reliability and strong security.But, antifuse is unlike static RAM（English：
Static Random Access Memory, referred to as：SRAM）It is therefore, anti-molten or Flash possesses erasable characteristic like that
Wire type FPGA can only one-time programming, and program by user final using preceding progress.
One of anti-fuse type FPGA circuitry difficult point is exactly circuit test, does not possess any work(because FPGA circuitry is not configured
Can, and anti-fuse FPGA can only be programmed once, it is impossible to can be in test phase to electricity as SRAM or Flash types FPGA
Road programing function is tested.Therefore, anti-fuse type FPGA circuitry must possess design for Measurability, make circuit in the feelings not programmed
The test of high coverage rate can be carried out to the internal logic of circuit under condition.
The content of the invention
For the test problem of above-mentioned anti-fuse type FPGA circuitry, the present invention proposes a kind of for anti-fuse type FPGA's
Design for testability circuit, the purpose is to can ensure that anti-fuse type FPGA realizes internal functional elements in the case where not programming
Test.
In order to solve the above technical problems, the technical solution adopted by the present invention is：
A kind of design for testability circuit suitable for anti-fuse type FPGA, the design for testability circuit is including control circuit and extremely
Few switch ways, each switch ways include the antifuse being arranged in parallel and test switching tube, and test switching tube is controlled
Circuit control is opened or closed, and after test switching tube is opened, antifuse is short-circuited, and after test switching tube is closed, antifuse makes
Energy.
Optionally, test switching tube is metal-oxide-semiconductor, and switch ways are at least two, and control circuit includes the trigger of series connection
And with the one-to-one register of trigger, the output end of each trigger is connected to the data input of corresponding register
End, the output end of each register is both connected to the grid of the test switching tube of a switch ways.
Optionally, it is anti-in the source electrode and switch ways of the test switching tube in switch ways for each switch ways
The second end connection of antifuse in the first end connection of fuse, switch ways in the drain electrode and switch ways of test switching tube.
Optionally, the output end of i-th of trigger and the data input pin of i+1 trigger connect in the trigger of series connection
Connect, the first clock signal input is connected with the input end of clock of each trigger respectively.
Optionally, the output end of i-th of trigger also connects with the data input pin of i-th of register in the trigger of series connection
Connect, the input of second clock signal is connected with the clock signal input terminal of each register respectively.
Optionally, reset terminal of the reset signal input respectively with each trigger and each register is connected, reset signal
The reset signal of input controls each trigger and each register to enter reset state, after register enters reset state,
The test switching tube being connected with register is closed.
Optionally, in test mode, control circuit receives test patterns to open corresponding test switching tube, to being opened
The circuit that is turned on of test switching tube tested；In normal work, control circuit receives reset signal to close each
Switching tube is tested, each antifuse is enabled and is operated.
According to above-mentioned technical proposal, the beneficial effect that the present invention can be realized at least includes：
By that by antifuse test switching tube in parallel, can allow control circuit optionally in controlling switch path
The opening of switching tube is tested, so as to ensure in test phase, it would be desirable to the antifuse short circuit corresponding to measurement circuit, using rank
Section, closes test switching tube, antifuse is enabled, and the test switching tube of closing does not interfere with signal transmission, will not introduce volume yet
Outer power consumption.
It should be appreciated that the general description of the above and detailed description hereinafter are only exemplary, this can not be limited
Invention.
Brief description of the drawings
Accompanying drawing herein is merged in specification and constitutes the part of this specification, shows the implementation for meeting the present invention
Example, and for explaining principle of the invention together with specification.
The structure for the design for testability circuit suitable for anti-fuse type FPGA that Fig. 1 provides for one embodiment of the invention
Figure.
Embodiment
Here exemplary embodiment will be illustrated in detail, its example is illustrated in the accompanying drawings.Following description is related to
During accompanying drawing, unless otherwise indicated, the same numbers in different accompanying drawings represent same or analogous key element.Following exemplary embodiment
Described in embodiment do not represent and the consistent all embodiments of the present invention.On the contrary, they be only with it is such as appended
The example of the consistent apparatus and method of some aspects be described in detail in claims, the present invention.That is said in text " connects
Connect " to be electrically connected with, it can be direct electric connection or be electrically connected with indirectly；" at least one " said in text be
One, two or more；" at least two " said in text are two or more.
The structure for the design for testability circuit suitable for anti-fuse type FPGA that Fig. 1 provides for one embodiment of the invention
Figure, should include control circuit 110 and at least one switch ways suitable for anti-fuse type FPGA design for testability circuit
120。
In actual applications, many antifuse 122 may be included in anti-fuse type fpga chip, in anti-fuse type
Before fpga chip comes into operation, it usually needs some circuits in chip are tested, and the circuit tested if desired
On be provided with antifuse 122, then influenceed by the non-erasable characteristic used of antifuse 122, in order to avoid test when to anti-
It will need to carry out design for Measurability to the antifuse 122 on the circuit of test in the write-in coding of fuse 122, the present embodiment, will
These antifuse 122 test switching tube 121 in parallel, antifuse 122 and test switching tube 121 in parallel is formed as one and opened
Close path 120.That is, anti-fuse type fpga chip can set at least one switch ways 120 for antifuse 122.
In test mode, control circuit 110 can optionally in controlling switch path test switching tube 121 is beaten
Open, after the opening of switching tube 121 is tested, antifuse 122 in parallel is then in short-circuit condition, now openable test therewith
Switching tube 121 can form signal path, so as to realize the test to respective lines.
In the operational mode, control circuit 110 can then be made anti-molten with the test switching tube 121 in closing switch path 120
Silk 122 enables work.
Therefore this design, can avoid antifuse 122 from being encoded in test phase.
In a kind of possible implementation, test switching tube 121 can be realized from metal-oxide-semiconductor, in this case, right
In each switch ways 120, switch ways 120 test switching tube 121 source electrode with it is anti-in same switch ways 120
The drain electrode of the test switching tube 121 is melted with anti-in the switch ways 120 in the first end connection of fuse 122, switch ways 120
The second end connection of silk 122.
General, now may then it be corresponded to comprising many antifuse 122 for needing to test in anti-fuse type fpga chip
More switch ways 120 can be provided with, such as including at least two switch ways 120, and in order that must be to the institute of antifuse 122
Control circuit 110 in the test of circuit has specific aim, the present embodiment can include the trigger 111 of series connection and with touching
Send out the one-to-one register 112 of device 111.The output end of each trigger 111 is connected to the data of corresponding register 112
Input, the output end of each register 112 is both connected to the grid of the test switching tube 121 of a switch ways 120, so
The output of register 112 can then control to test the opening and closing of switching tube 121.
In actual applications, in order to ensure that the specific aim of each place circuit of antifuse 122 is tested, it is usually arranged as triggering
Device 111 is corresponded with register 112, and register 112 is corresponded with test switching tube 121.When there is more antifuse
122, it is necessary to be correspondingly arranged more multiple switch ways 120, for each switch ways 120, it is necessary to set one group of He of trigger 111
Register 112, therefore, multiple triggers 111 of series connection then form shift register chain.
It is worth noting that, multiple triggers 111 are carried out into series connection can reduce the setting of port and circuit, for core
For piece, the area of chip can be substantially reduced.
In one implementation, the output end of i-th of trigger 111 and i+1 trigger 111 in shift register chain
Data input pin is connected, and input end of clock of first clock signal input respectively with each trigger 111 is connected.
In order to which the corresponding position of test patterns is carried in register 112, shift register chain into the defeated of i-th trigger 111
Go out data input pin of the end also with i-th of register 112 to be connected.Second clock signal input respectively with each register 112
Clock signal input terminal is connected.
By the design of foregoing circuit, test patterns can be inputted by the serial input port TDI of shift register chain to
Circuit 110, namely test patterns is controlled to be inputted by the data input pin of first trigger 111 to control circuit 110.The
One clock signal input provides clock pulses（That is the serial clock TCK in Fig. 1）And input is defeated to the clock of each trigger 111
Enter end, such test patterns（That is the serial input TDI in Fig. 1）It can be shifted successively until last trigger 111.
After the completion of the displacement of all test patterns, tck clock stops, and the input of second clock signal provides an output control arteries and veins
Punching（That is the UPDATE in Fig. 1）, the data parallel of each trigger 111 is read out in the latch of rear class.Latch it is defeated
Going out signal controls the test switching tube 121 being connected to open or close, to realize the switch of signal path, now unprogrammed anti-
Fuse 122, in state is short-circuited, does not work in the case where test switching tube 121 is opened to signal transmission.By this
Mode, realization transmits test signal in the case where antifuse 122 is not programmed, and circuit is tested.
In order to ensure that each test switching tube 121 is closed under mode of operation, is additionally provided with reset signal in the present embodiment
Input, reset terminal of the reset signal input respectively with each trigger 111 and each register 112 is connected.
In the operational mode, the reset signal that reset signal input is provided controls each trigger 111 and each register
112 enter reset state, and after register 112 enters reset state, the test switching tube 121 being connected with register 112 is closed,
The antifuse 122 in parallel with the test switching tube 121 of closing is then enabled.
According to the displacement feature of the chain of shift register 112, test patterns are eventually displaced to last trigger 111, and
Each trigger 111 can export a position extremely simultaneously in the case where second clock signal inputs the control of the output control pulse provided
The register 112 of rear class, one test switching tube 121 of output correspondence control of each register 112, such as " 0 ", which is represented, to be closed,
" 1 ", which is represented, opens, so that the circuit tested as needed sets test patterns, it is real to realize the opening of correspondence test switching tube 121
Now correspond to the test of the test place circuit of switching tube 121.
In summary, the design for testability circuit provided in an embodiment of the present invention suitable for anti-fuse type FPGA, by inciting somebody to action
Test switching tube is arranged in parallel with antifuse, and by controlling circuit control to test the opening and closing of switching tube, so that
In the short-circuit antifuse of test phase, antifuse is enabled in working stage, to realize anti-fuse type FPGA in the case where not programming
Realize the test of internal functional elements.
Those skilled in the art will readily occur to its of the present invention after the invention that specification and practice are invented here is considered
Its embodiment.The application be intended to the present invention any modification, purposes or adaptations, these modifications, purposes or
Person's adaptations follow the general principle of the present invention and the common knowledge in the art do not invented including the present invention
Or conventional techniques.Description and embodiments are considered only as exemplary, and true scope and spirit of the invention are by following
Claim is pointed out.
It should be appreciated that the invention is not limited in the precision architecture for being described above and being shown in the drawings, and
And various modifications and changes can be being carried out without departing from the scope.The scope of the present invention is only limited by appended claim.
Claims (7)
1. a kind of design for testability circuit suitable for anti-fuse type programmable gate array, it is characterised in that described to survey
Property design circuit include control circuit and at least one switch ways, each switch ways include the antifuse being arranged in parallel and
Switching tube is tested, the test switching tube is opened or closed by the control circuit control, after the test switching tube is opened, institute
State antifuse to be short-circuited, after the test switching tube is closed, the antifuse is enabled.
2. design for testability circuit according to claim 1, it is characterised in that the test switching tube is metal-oxide-semiconductor, described
Switch ways are at least two, it is described control circuit include series connection trigger and with the one-to-one register of trigger,
The output end of each trigger is connected to the data input pin of corresponding register, and the output end of each register is both connected to
The grid of the test switching tube of one switch ways.
3. design for testability circuit according to claim 2, it is characterised in that for each switch ways, the switch
The source electrode of test switching tube in path is connected with the first end of the antifuse in the switch ways, institute in the switch ways
The drain electrode for stating test switching tube is connected with the second end of the antifuse in the switch ways.
4. according to claim 2 test design circuit, it is characterised in that touched for i-th in the trigger of the series connection
Hair device output end be connected with the data input pin of i+1 trigger, the first clock signal input respectively with each trigger
Input end of clock connection.
5. according to claim 2 test design circuit, it is characterised in that touched for i-th in the trigger of the series connection
Data input pin of the output end also with i-th of register for sending out device be connected, second clock signal input respectively with each register
Clock signal input terminal connection.
6. according to claim 2 test design circuit, it is characterised in that reset signal input is triggered with each respectively
The reset terminal of device and each register is connected, and the reset signal of the reset signal input controls each trigger and each deposit
Device enters reset state, after register enters reset state, and the test switching tube being connected with the register is closed.
7. described test design circuit according to any in claim 1 to 6, it is characterised in that
In test mode, the control circuit receives test patterns to open corresponding test switching tube, the test to being opened
The circuit that switching tube is turned on is tested；
In normal work, the control circuit receives reset signal to close each test switching tube, makes each antifuse
It can be operated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710301292.6A CN107134994A (en) | 2017-05-02 | 2017-05-02 | Suitable for the design for testability circuit of anti-fuse type programmable gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710301292.6A CN107134994A (en) | 2017-05-02 | 2017-05-02 | Suitable for the design for testability circuit of anti-fuse type programmable gate array |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107134994A true CN107134994A (en) | 2017-09-05 |
Family
ID=59716258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710301292.6A Pending CN107134994A (en) | 2017-05-02 | 2017-05-02 | Suitable for the design for testability circuit of anti-fuse type programmable gate array |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107134994A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108932408A (en) * | 2018-08-03 | 2018-12-04 | 广东工业大学 | A kind of enable signal control circuit and a kind of chip |
| CN111445943A (en) * | 2020-04-15 | 2020-07-24 | 武汉金汤信安科技有限公司 | On-chip one-time programmable circuit |
| CN116718901A (en) * | 2023-08-10 | 2023-09-08 | 成都市硅海武林科技有限公司 | Anti-fuse FPGA high-speed test circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101010762A (en) * | 2004-09-01 | 2007-08-01 | 国际商业机器公司 | Low voltage programmable eFuse with differential sensing scheme |
| US20150130506A1 (en) * | 2013-11-14 | 2015-05-14 | Case Western Reserve University | Defense against counterfeiting using antifuses |
| CN105988074A (en) * | 2015-02-12 | 2016-10-05 | 上海晟矽微电子股份有限公司 | One-time programmable microcontroller chip based test circuit and test method |
| CN106324474A (en) * | 2015-06-24 | 2017-01-11 | 华晋书 | Testing burning system for anti-fuse FPGA |
| CN106468758A (en) * | 2015-08-17 | 2017-03-01 | 华晋书 | A kind of microprobe Real-time and Dynamic test circuit for anti-fuse FPGA |
-
2017
- 2017-05-02 CN CN201710301292.6A patent/CN107134994A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101010762A (en) * | 2004-09-01 | 2007-08-01 | 国际商业机器公司 | Low voltage programmable eFuse with differential sensing scheme |
| US20150130506A1 (en) * | 2013-11-14 | 2015-05-14 | Case Western Reserve University | Defense against counterfeiting using antifuses |
| CN105988074A (en) * | 2015-02-12 | 2016-10-05 | 上海晟矽微电子股份有限公司 | One-time programmable microcontroller chip based test circuit and test method |
| CN106324474A (en) * | 2015-06-24 | 2017-01-11 | 华晋书 | Testing burning system for anti-fuse FPGA |
| CN106468758A (en) * | 2015-08-17 | 2017-03-01 | 华晋书 | A kind of microprobe Real-time and Dynamic test circuit for anti-fuse FPGA |
Non-Patent Citations (1)
| Title |
|---|
| 马金龙等: "基于反熔丝的FPGA的测试方法", 《微电子学与计算机》 * |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108932408A (en) * | 2018-08-03 | 2018-12-04 | 广东工业大学 | A kind of enable signal control circuit and a kind of chip |
| CN108932408B (en) * | 2018-08-03 | 2022-06-24 | 广东工业大学 | Enabling signal control circuit and chip |
| CN111445943A (en) * | 2020-04-15 | 2020-07-24 | 武汉金汤信安科技有限公司 | On-chip one-time programmable circuit |
| CN116718901A (en) * | 2023-08-10 | 2023-09-08 | 成都市硅海武林科技有限公司 | Anti-fuse FPGA high-speed test circuit |
| CN116718901B (en) * | 2023-08-10 | 2023-11-24 | 成都市硅海武林科技有限公司 | Anti-fuse FPGA high-speed test circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5083083A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US5223792A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US4873459A (en) | Programmable interconnect architecture | |
| Gattiker et al. | Current signatures [VLSI circuit testing] | |
| US5365165A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US4910417A (en) | Universal logic module comprising multiplexers | |
| CN101010762B (en) | Integrated circuit and method for low voltage programming and differential detection for eFuse | |
| JP2934149B2 (en) | Programmable integrated logic device | |
| US5208530A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US6373771B1 (en) | Integrated fuse latch and shift register for efficient programming and fuse readout | |
| Ni et al. | Non-intrusive online distributed pulse shrinking-based interconnect testing in 2.5 D IC | |
| CN101079420B (en) | Semiconductor device | |
| US5309091A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US5341092A (en) | Testability architecture and techniques for programmable interconnect architecture | |
| US8736291B2 (en) | Methods for defect testing of externally accessible integrated circuit interconnects | |
| US6601202B2 (en) | Circuit configuration with deactivatable scan path | |
| CN107134994A (en) | Suitable for the design for testability circuit of anti-fuse type programmable gate array | |
| US5970005A (en) | Testing structure and method for high density PLDs which have flexible logic built-in blocks | |
| CN101238382A (en) | Testing of an integrated circuit that contains secret information | |
| US6798272B2 (en) | Shift register for sequential fuse latch operation | |
| US8391091B2 (en) | Anti-fuse circuit and method for anti-fuse programming and test thereof | |
| US5572458A (en) | Multi-level vROM programming method and circuit | |
| CN106324474A (en) | Testing burning system for anti-fuse FPGA | |
| EP1586098B1 (en) | Multiple trip point fuse latch device and test method of the fuse | |
| CN101566669A (en) | Semiconductor integrated circuit device and device and method for reliability test thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170905 |