JP3241543B2 - Semiconductor circuit characteristic evaluation device and semiconductor circuit device provided with characteristic evaluation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit characteristic evaluation device for evaluating characteristics of a semiconductor logic circuit, and a semiconductor circuit device incorporating the characteristic evaluation device.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration of a conventional characteristic evaluation device for evaluating characteristics of a semiconductor circuit. In FIG. 5, an inverter logic circuit is taken as a semiconductor circuit.
n-channel MOS field effect transistor (hereinafter referred to as n-M
The gate and drain of an OSEFT 10 and a p-channel MOS field-effect transistor (hereinafter, p-MOSEFT) 20 are connected to each other. The connection point ti between the gates is used as an input terminal, the connection point to between the drains is used as an output terminal, and n-
A low-potential pad 107 for supplying a low-potential power supply voltage is connected to the source of the MOSEFT 10.
A high-potential pad 105 for supplying a high-potential power supply voltage is connected to the source of T, and the n-MOSFET 10 and the p-MO
An inverter logic circuit 30a is configured with the SFET.

In this manner, inverter logic circuits 30b, 30c... 30n (n is an odd number) having the same configuration are formed, and the respective inverter logic circuits 30a, 30b.
Are connected in series with each other, and the output terminal to of the last stage inverter logic circuit 30n is connected to the first stage inverter logic circuit 3n.
0a is connected to the input terminal ti to form a ring-shaped self-oscillation circuit. The output terminal to of the final stage inverter logic circuit 30n measures and evaluates the waveform change and frequency change of the signal waveform of the output terminal to. A measuring pad 106 for connecting a measuring instrument to be connected is connected.

According to the characteristic evaluation device having such a configuration,
The signal waveform and frequency of the self-oscillation are analyzed and evaluated by a measuring instrument such as an oscilloscope connected via the measuring pad 106 to the output terminal to of the final stage inverter logic circuit 30n, and the operation of the inverter logic circuits 30a to 30n is performed. P-MOS that constitutes the characteristics and thus the inverter logic circuit
The operation characteristics of the FET and the n-MOSFET can be evaluated. It is also possible to determine how much the oscillation frequency has changed from the initial oscillation frequency and determine the degree of characteristic deterioration of the p-MOSFET and the n-MOSFET constituting the inverter logic circuit.

[0005]

According to the above-described conventional characteristic evaluation apparatus, in the case of the inverter logic circuit 30a, a constant high potential power supply voltage is applied to the source of the p-MOSFET 20 and the source of the n-MOSFET 10 Oscillates in a state where a constant low potential power supply voltage is applied, and the operation characteristics of the inverter logic circuit are evaluated. However, in an actual circuit, for example, as is apparent from a frequently used NAND circuit or NOR circuit, n-
Normally, the source potential of the MOSFET and the source potential of the p-MOSFET change within a range from the ground potential to the power supply voltage Vcc during signal transmission. In this case, the substrate potential or well potential of each MOSFET is set to the ground potential in the n-MOSFET, and the p-MO
Since the SFET is fixedly connected to the potential of the power supply voltage Vcc, a change in the source potential of each MOSFET causes a substrate bias effect in each MOSFET, and causes each M
The threshold voltage of the OSFET will change. On the other hand, the above-described characteristic evaluation apparatus has a problem that the characteristic evaluation is not performed under the condition where the substrate bias effect actually occurs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned current situation of the evaluation of characteristics of semiconductor circuits.
It is an object of the present invention to provide a semiconductor circuit characteristic evaluation device capable of evaluating the characteristics of a semiconductor logic circuit under a condition of occurrence of a substrate bias effect that is practical in which the potential of an electrode of a semiconductor element changes.

A second object of the present invention is to provide a semiconductor circuit capable of evaluating the characteristics of a semiconductor logic circuit under the condition of the occurrence of a substrate bias effect in accordance with the fact that the potential of the transistor electrode changes. An object of the present invention is to provide a semiconductor circuit device incorporating a characteristic evaluation device.

[0008]

In order to achieve the first object, the present invention provides a semiconductor logic circuit comprising a semiconductor element, and a plurality of the semiconductor logic circuits are connected in series to each other in odd-numbered stages. The output terminal of the semiconductor logic circuit of the stage is
In a semiconductor circuit characteristic evaluation device that is connected to an input terminal of a first-stage semiconductor logic circuit and measures an oscillation waveform at the output terminal to evaluate characteristics of the semiconductor logic circuit, the semiconductor device is connected to an electrode of the semiconductor element. has a bias effect generating means for varying the power supply voltage applied to the electrodes, and a measuring means for measuring the oscillation waveform of the output terminals of the semiconductor logic circuit of the final stage.

According to the first aspect of the present invention, the semiconductor device includes a first p-channel type field effect transistor;
A second p-channel field-effect transistor having a common source and a common drain with the first p-channel field-effect transistor, and connected in parallel with the first p-channel field-effect transistor; A semiconductor logic circuit is a NAND logic circuit, an input terminal is provided at the common gate and a gate of the n-channel field effect transistor, and the common drain and An output terminal is provided at a drain of the n-channel type field effect transistor, and a bias effect generating means is connected to the common source, the first bias effect generating means for lowering the voltage of the source from a high potential power supply voltage. And a source of the n-channel field effect transistor, And a second bias effect generating means for raising the voltage of the NAND logic circuit from a low potential power supply voltage. The measuring means is connected to a measurement pad connected to an output terminal of the final stage NAND logic circuit. A high-potential pad for supplying the high-potential power supply voltage to the first bias-effect generating means; and a low-potential power supply for the second bias-effect generating means. And a low-potential pad for supplying a voltage.

According to the second aspect of the present invention, the semiconductor element is:
A first n-channel field-effect transistor; and a second n-channel field-effect transistor having a common source and a common drain with the first n-channel field-effect transistor and connected in parallel to the first n-channel field-effect transistor. an n-channel field-effect transistor, and a p-channel field-effect transistor having a drain connected to the common drain,
A semiconductor logic circuit is a NOR logic circuit, an input terminal is provided at a gate of the p-channel field-effect transistor and the common gate, and an output terminal is provided at a drain and the common drain of the p-channel field-effect transistor; A bias effect generating means connected to a source of the p-channel field effect transistor, a first bias effect generating means for lowering the voltage of the source below a high potential power supply voltage, and a bias effect generating means connected to the common source; A second bias effect generating means for raising the voltage of the source above a low potential power supply voltage, wherein the measuring means is connected to a measuring pad connected to the output terminal of the NOR logic circuit at the last stage; A measuring device for measuring an oscillation waveform for characteristic evaluation of a logic circuit, wherein the first bias effect generating means is provided with the high potential A high potential pad for supplying a source voltage,
And a low potential pad for supplying the low potential power supply voltage to the second bias effect generating means.

[0011] To achieve the second object, the present invention provides
The invention described in Item 4 is characterized in that the semiconductor circuit evaluation device of the present invention is incorporated in a semiconductor circuit device.

[0012]

According to the present invention, a plurality of semiconductor logic circuits each having a semiconductor element as a constituent element are connected in series to odd-numbered stages,
The output terminal of the last-stage semiconductor logic circuit is connected to the input terminal of the first-stage semiconductor logic circuit to constitute a characteristic evaluation device, and its oscillation waveform is measured at the output terminal by the measuring means, and the characteristic evaluation of the semiconductor logic circuit is performed. Done. In this case, the power supply voltage applied to the electrode of the semiconductor element to which the bias effect generating means is connected is changed by the bias effect generating means, and the characteristic evaluation apparatus performs the semiconductor logic operation under the actual condition of the bias effect. Evaluate the characteristics of the circuit.

[0013] Then, according to the first aspect of the invention, a first p-channel type field effect transistor, the first p
A second p-channel field-effect transistor having a channel-type field-effect transistor, a common source and a common drain, connected in parallel to the first p-channel-type field-effect transistor, and a drain connected to the common drain NAN with the n-channel type field effect transistor
A D logic circuit is configured. When the characteristics of the NAND logic circuit are evaluated, the first bias effect generator connected to the common source and supplied with a high-potential power supply voltage from a high-potential pad makes the source voltage higher than the high-potential power supply voltage. Is also reduced. A second bias effect generating means connected to the source of the n-channel field effect transistor and supplied with a low-potential power supply voltage from a low-potential pad causes the source voltage to rise above the low-potential power supply voltage. As a result, a bias effect is generated in the characteristic evaluation device.
Under such a bias effect generation condition, the common gate and the gate of the n-channel type field effect transistor are used as the input terminal, and the common drain and the drain of the n-channel type field effect transistor are used as the output terminal. The measuring device connected to the measuring pad connected to the terminal and measuring the oscillation waveform of the characteristic evaluation of the NAND logic circuit allows the characteristic evaluation device to determine the characteristic of the NAND logic circuit under the condition of the actual occurrence of the bias effect. Perform an evaluation.

[0014] According to the second aspect of the invention, the first
An n-channel field-effect transistor, a second n-channel transistor having a common source and a common drain with the first n-channel field-effect transistor, and connected in parallel to the first n-channel field-effect transistor. And a p-channel field effect transistor having a drain connected to the common drain constitutes a NOR logic circuit. When evaluating the characteristics of the NOR logic circuit, the first bias effect generating means connected to the source of the p-channel field-effect transistor and supplied with a high-potential power supply voltage from a high-potential pad reduces the voltage of the source. It is lowered below the high potential power supply voltage. Also,
The second bias effect generating means connected to the common source and supplied with a low-potential power supply voltage from a low-potential pad raises the voltage of the source above the low-potential power supply voltage, thereby biasing the characteristic evaluation device. The effect is generated. Under such a bias effect generation condition, the gate and the common gate of the p-channel field effect transistor are used as input terminals,
The drain and common drain of the p-channel field-effect transistor are connected as output terminals to a measurement pad connected to the output terminal of the NOR logic circuit at the final stage, and the N
The characteristic evaluation device performs the characteristic evaluation of the NAND logic circuit under the condition of the actual occurrence of the bias effect by using the measuring device that measures the oscillation waveform of the characteristic evaluation of the OR logic circuit.

In a semiconductor circuit evaluation device incorporated in a semiconductor circuit device according to a fourth aspect of the present invention, a plurality of semiconductor logic circuits each having a semiconductor element as a constituent element are connected in series to odd-numbered stages, and a final semiconductor The output terminal of the logic circuit is connected to the input terminal of the first-stage semiconductor logic circuit to form a characteristic evaluation device. The oscillation waveform is measured at the output terminal by the measuring means, and the characteristics of the semiconductor logic circuit are evaluated. In this case, the power supply voltage applied to the electrode of the semiconductor element to which the bias effect generating means is connected is changed by the bias effect generating means, and the characteristic evaluation apparatus performs the semiconductor logic operation under the actual condition of the bias effect. Evaluate the characteristics of the circuit.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a reference relating to a device for evaluating characteristics of a semiconductor circuit
Examples and embodiments will be described with reference to FIGS. FIG. 1 is a circuit diagram showing a configuration of a reference example , FIG. 2 is a circuit diagram showing a configuration of a first embodiment of the present invention, and FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the present invention.

REFERENCE EXAMPLE In FIG. 1, reference numerals 31a to 31n (n is an odd number) indicate inverter logic circuits including an inverter logic circuit composed of a p-MOSFET and an n-MOSFET whose characteristics are evaluated. Explaining in the section 31b, the high potential pad 105 is provided with p as a first bias effect generating means with respect to the conventional circuit already described with reference to FIG.
The source of the MOSEFT 22 is connected, and the p-MOSE
The drain of FT22 is connected to the source of p-MOSEFT20, and the gate of p-MOSEFT22 is connected to low potential pad 107. In addition, the low potential pad 10
7 shows an n-MOSF as a second bias effect generating means.
The source of the ET 21 is connected, the drain of the n-MOSFET 21 is connected to the source of the n-MOSFET 10, and the gate of the n-MOSFET 21 is connected to the high potential pad 10.
5 is connected. Other parts are the same as those of the conventional evaluation apparatus already described with reference to FIG.
-MOSFT20, n-MOSFET10, p-MOS
The EFT 22 and the n-MOSFET 21 constitute an inverter logic circuit, and the plurality of inverter logic circuits 31
The odd-numbered stages a to 31n are connected in a ring shape.

The operation of the reference example having such a configuration will be described. In this reference example , in the inverter logic circuit unit, n
Since the gate of the MOSFET 21 is connected to the high potential pad 105 and the gate of the p-MOSFET 22 is connected to the low potential pad 107, the n-MOSFET 21 and the p-MOSFET 22 are always on. In this reference example , the inverter logic circuit unit 31a in the preceding stage
If the signal level of the output terminal to is L level, n-
The MOSFET 10 is turned off, the p-MOSFET 20 is turned on, and the n-MOSFET 21 and the p-MOSF
Since the ET22 and the ET22 are in the ON state, the p-MOSFET22,
A high-potential power supply voltage is supplied from the high-potential pad 105 via 20, and the signal level of the output terminal to of the inverter logic circuit unit 31b becomes H level.

On the other hand, the preceding inverter logic circuit section 31a
Is at the H level, n-
MOSFET 10 is turned on, p-MOSFET 20 is turned off, and n-MOSFET 21 and p-MOSF are turned on.
Since the ET22 and the ET22 are on, the output terminal to of the inverter logic circuit unit 31b is connected to the n-MOSFET 21,
A low-potential power supply voltage is supplied from the low-potential pad 107 via 10, and the signal level of the output terminal to of the inverter logic circuit unit 31b becomes L level.

Thus, the inverter logic circuit unit 3
1b performs an inverter operation of outputting an output signal having an inverted input signal level, and a self-oscillation operation is induced in a characteristic evaluation device in which a plurality of inverter logic circuit units 31a to 31n are connected in an odd-numbered ring shape. You. In this case, for example, the output terminal to of the inverter logic circuit unit 31b
Changes from H level to L level, that is, n-MO
When the SFET 10 changes from the on state to the off state, the potential of the source of the n-MOSFET 10 becomes n-MO
The voltage drop of the SFET 21 causes the low potential pad 107
Does not become the ground potential (grounded substrate potential), but becomes slightly higher than the grounded substrate potential. Therefore,
Source of n-MOSFET 10 and n-MOSFET 10
A reverse bias voltage is applied between the n-MOSFET 10 and the substrate on which the substrate is formed, so that a substrate bias effect is set in the n-MOSFET 10.

On the other hand, when the signal at the output terminal to of the inverter logic circuit section 31b changes from the L level to the H level, that is, when the p-MOSFET 20 changes from the on state to the off state, the source potential of the p-MOSFET 20 becomes p
-Due to the voltage drop of the MOSFET 22, the power supply voltage Vcc of the high-potential pad 105 (substrate potential connected to the power supply voltage Vcc) does not become, but becomes slightly lower than the substrate potential. Therefore, between the source of the p-MOSFET 20 and the substrate on which the p-MOSFET 20 is formed,
When a reverse bias voltage is applied, a body bias effect is set in the p-MOSFET 20.

As described above, according to the present embodiment , a measuring device such as an oscilloscope for evaluating operating characteristics is connected to the measuring pad 106, and the inverter logic circuit 31a is connected.
The self-oscillation of an evaluation device in which n-stage rings are connected to each other under the measurement conditions close to the actual state in which the substrate bias effect is set, and thus the operation of the inverter logic circuit and the transistor constituting the inverter logic circuit. It is possible to accurately and accurately measure characteristics and operation deterioration characteristics and determine an operation state.

[ First Embodiment] Next, a first embodiment of the present invention will be described with reference to FIG. In FIG. 2, 32a to 32n (n is an odd number) are p-MOSFETs and n-Ms whose characteristics are evaluated in the present embodiment.
This is a NAND logic circuit section including a NAND logic circuit composed of an OSFET. In the NAND logic circuit section 32b, a common circuit is used instead of the p-MOSFET 20 with respect to the circuit of the reference example already described with reference to FIG. P-MOSF having a drain and a source and connected in parallel with each other
An ET 20a and a p-MOSFET 20b are provided, the common source is connected to the drain of the p-MOSFET 22, and the common drain is connected to the drain of the n-MOSFET 10. And the p-MOSFET 20a,
20b, n-MOSFET 10, p-MOSFET2
2, and the n-MOSFET 10 constitute a NAND logic circuit portion, and a plurality of NAND logic circuit portions 32a to 32n are connected in an odd-numbered stage ring shape. The configuration of the other parts of the present embodiment is the same as that of the reference example already described with reference to FIG.

Next, the operation of this embodiment having such a configuration will be described. In this embodiment, the NAND logic circuit section 32b will be described. The n-MOSFET 21 and the p-MO
The gate of the SFET 20b is connected to the high potential pad 105, and the gate of the p-MOSFET 22 is connected to the low potential pad 1
07, the n-MOSFET 21 and the p-MOSFET 22 are always on, and the p-MO
The SFET 20b is always off. In this embodiment,
When the signal level of the output terminal to of the NAND logic circuit unit 32a at the preceding stage is at the H level, the n-MOSFET 10 is turned on and the p-MOSFET 20a is turned off. At this time, the n-MOSFET 21 and the p-MOSFET
22 is in the ON state, the NAND logic circuit unit 32b
Is connected to the low potential pad 107 via the n-MOSFETs 10 and 21, and the signal level of the output terminal to becomes L level.

On the other hand, if the signal level of the output terminal to of the preceding NAND logic circuit section 32a is at L level, nM
OSFET 10 is turned off, and p-MOSFET 2
0a is turned on. At this time, since the n-MOSFET 21 and the p-MOSFET 22 are turned on, NAN
The output terminal to of the D logic circuit unit 32b is a p-MOSFE
It is connected to the high potential pad 105 via T20a, T22, and the signal level of the output terminal to becomes H level.

As described above, the NAND logic circuit section 32b of the present embodiment performs an inverter operation of outputting an output signal having an inverted level of the input signal level, and performs a plurality of NAN operations.
In the characteristic evaluation device in which the D logic circuit units 32a to 32n are connected in an odd-numbered ring shape, a self-oscillation operation is induced. In this case, for example, the output terminal t of the NAND logic circuit unit 32b
o changes from H level to L level, that is, n−M
When the OSFET 10 changes from the on state to the off state, the potential of the source of the n-MOSFET 10 becomes n-MO
The voltage drop of the SFET 21 causes the low potential pad 107
Does not become the ground potential (grounded substrate potential), but becomes slightly higher than the grounded substrate potential. Therefore,
Source of n-MOSFET 10 and n-MOSFET 10
A reverse bias voltage is applied between the n-MOSFET 10 and the substrate on which the substrate is formed, so that a substrate bias effect is set in the n-MOSFET 10.

On the other hand, the signal at the output terminal to of the NAND logic circuit 32b changes from L level to H level,
When the MOSFET 20a changes from the ON state to the OFF state, the potential of the source of the p-MOSFET 20a becomes
Due to the voltage drop of the p-MOSFET 22, the power supply voltage Vcc of the high potential pad 105 (substrate potential connected to the power supply voltage Vcc) does not become, but becomes slightly lower than the substrate potential. Therefore, a reverse bias voltage is applied between the source of the p-MOSFET 20a and the substrate on which the p-MOSFET 20a is formed, so that the p-MOSFET 2
The substrate bias effect is set to 0a.

As described above, according to the present embodiment, a measuring instrument such as an oscilloscope for evaluating operating characteristics is connected to the measuring pad 106 and the NAND logic circuit sections 32a to 32a are connected.
The self-oscillation of the evaluation device 32n connected in an n-stage ring shape enables the NAND logic circuit, and hence the operating characteristics of the transistors constituting the NAND logic circuit, under measurement conditions close to the actual state in which the substrate bias effect is set. And the deterioration characteristics of the operation can be accurately and accurately measured, and the operation state can be determined.

[0029] [Second Embodiment] Next, a second embodiment of the present invention with reference to FIG. In FIG. 3, 33a to 33n (n is an odd number) are p-MOSFETs and n-MOs whose characteristics are evaluated in the present embodiment.
This is a NOR logic circuit section including a NOR logic circuit composed of SFETs. When explained in the NOR logic circuit section 33b, the circuit of the reference example already described with reference to FIG.
An n-MOSFET 10 having a common drain and source and connected in parallel with each other instead of the MOSFET 10
a and an n-MOSFET 10b are provided, the common source is connected to the drain of the n-MOSFET 21 and the common drain is connected to the drain of the p-MOSFET 20. And p-MOSFET 20, n-MOS
FETs 10a, 10b, p-MOSFET 22, and n
-A NOR logic circuit section is constituted by the MOSFET 21, and a plurality of NOR logic circuit sections 33a to 33n are connected in an odd-numbered stage ring shape. The configuration of other parts of the present embodiment is as follows.
Since it is the same as the reference example already described with reference to FIG.

Next, the operation of this embodiment having such a configuration will be described. In this embodiment, the NOR logic circuit unit 33b will be described. The p-MOSFET 22 and the n-MOS
The gate of the FET 10b is connected to the low potential pad 107, and the gate of the n-MOSFET 21 is connected to the high potential pad 107.
5, the p-MOSFET 22 and n
-MOSFET 21 is always on and n-MOS
The FET 10b is always off. In this embodiment, when the signal level of the output terminal to of the NOR logic circuit unit 33a at the preceding stage is at the H level, the p-MOSFET 20 is turned off, the n-MOSFET 10a is turned on,
At this time, the p-MOSFET 22 and the n-MOSFET 21
Is in the ON state, the output terminal to of the NOR logic circuit 33b is connected to the n-MOSFETs 10a and 21 through
The output terminal to is connected to the low potential pad 107, and the signal level of the output terminal to becomes L level.

On the other hand, if the signal level of the output terminal to of the preceding NOR logic circuit section 32a is L level, n-MO
The SFET 10a is turned off, and the p-MOSFET 2
0 is in the ON state, and at this time, the p-MOSFET 22 and the n-MOSFET 21 are in the ON state. Therefore, the output terminal to of the NOR logic circuit 33b is connected to the p-MOSFET 2
It is connected to the high-potential pad 105 via 0 and 22, and the signal level of the output terminal to becomes H level.

As described above, the NOR logic circuit section 33b of this embodiment performs an inverter operation of outputting an output signal of an inverted level of the input signal level, and the plurality of NOR logic circuit sections 33a to 33n In the characteristic evaluation device connected in a ring shape, a self-oscillation operation is induced. In this case, for example, the signal at the output terminal to of the NOR logic circuit unit 33b changes from the L level to the H level, that is, the p-MOSF
When the ET 20 changes from the on state to the off state, p
-The source potential of the MOSFET 20 is p-MOSFE
Due to the voltage drop of T22, the potential of the power supply voltage Vcc of the high potential pad 105 (substrate potential of the power supply voltage Vcc) does not become, but becomes slightly lower than the substrate potential of the power supply voltage Vcc. Therefore, the source of n-MOSFET 10 and n-M
A reverse bias voltage is applied between the substrate on which the OSFET 10 is formed and a substrate bias effect is set in the n-MOSFET 10.

On the other hand, the signal at the output terminal to of the NOR logic circuit 33b changes from H level to L level, that is, n-
When the MOSFET 10a changes from the on state to the off state, the potential of the source of the n-MOSFET 10a becomes n
-Due to the voltage drop of the MOSFET 21, the ground voltage of the low-potential pad 107 (potential of the grounded substrate) is not attained, but a potential slightly higher than the substrate potential. Therefore, the source of the n-MOSFET 10a and the n-MOSFE
A reverse bias voltage is applied between the substrate on which T10a is formed and a substrate bias effect is set on the n-MOSFET 10a.

As described above, according to the present embodiment, the measuring pad 106 is connected to a measuring device such as an oscilloscope for evaluating operating characteristics, and the NOR logic circuit units 33a to 33a are connected.
By self-oscillating the evaluation device in which 3n is connected in an n-stage ring shape, the NOR logic circuit and hence the NO under the measurement condition close to the actual state where the substrate bias effect is set.
It is possible to accurately and accurately measure the operation characteristics and operation deterioration characteristics of the transistors constituting the R logic circuit and determine the operation state.

In each embodiment, a case has been described in which a one-stage p-MOSFET is provided as the first bias effect generating means and a one-stage n-MOSFET is provided as the second bias effect generating means. The present invention is not limited to these embodiments.
And an n-MOSFET. In the first embodiment, the case where the number of input terminals of the NAND logic circuit is 2 has been described. However, the present invention is not limited to this embodiment, and the number of input terminals of the NAND logic circuit can be three or more. It is. Similarly, the number of input terminals of the NOR logic circuit in the second embodiment is not limited to two, and the number of input terminals of the NOR logic circuit can be three or more.

Next, one embodiment of the present invention relating to a semiconductor circuit device having a characteristic evaluation device will be described with reference to FIG.
FIG. 4 is an explanatory diagram showing the configuration of the present embodiment. In this embodiment, as shown in the figure, a characteristic evaluation device 43 according to the embodiment is attached to a part of a semiconductor chip 41 as a semiconductor circuit device on which a semiconductor integrated circuit 42 is formed.

According to the present embodiment, when the semiconductor integrated circuit 42 is driven, the characteristic evaluation device 43 is also driven, and the characteristic evaluation device 43 measures the evaluation of the characteristics of the logic circuit and thus the transistors constituting the logic circuit. Pad 106
The characteristics of the transistors used in the semiconductor integrated circuit 42 can be easily and accurately evaluated by monitoring and evaluating the waveform of the output signal using an oscilloscope or the like connected to the oscilloscope. In FIG. 4, the high potential pad 10
5, the low potential pad 107 and the measurement pad 106 are provided separately from the pads connected to the semiconductor integrated circuit 42. However, the pads connected to the semiconductor integrated circuit 42 can be shared .

[0038]

According to the present invention, a plurality of odd-numbered stages of semiconductor logic circuits each including a semiconductor element are connected in series, and the output terminal of the last-stage semiconductor logic circuit is connected to the input terminal of the first-stage semiconductor logic circuit. The characteristic evaluation device is connected to the semiconductor device and the bias effect generating means changes the power supply voltage applied to the electrode of the semiconductor element under the condition of the occurrence of the bias effect. , And the characteristic evaluation of the semiconductor logic circuit is performed, so that the characteristic evaluation of the semiconductor logic circuit can be performed accurately and accurately under the actual condition of the occurrence of the bias effect.

[0039] According to the first aspect of the invention, a first p-channel type field effect transistor, a p-channel type field effect transistor of the first have a common source and common drain, the first p-channel type A NAND comprising a second p-channel field-effect transistor connected in parallel to the field-effect transistor and an n-channel field-effect transistor having a drain connected to the common drain
And against the logic circuit, in developmental conditions actually conformity bias effect, it becomes possible to perform the characterization of the NAND logic circuit precisely and accurately.

According to the second aspect of the present invention, the first n-channel type field-effect transistor has a common source and a common drain with the first n-channel type field-effect transistor, a second n-channel field effect transistor connected in parallel to the field effect transistor, and against the configured NOR logic circuit in the p-channel type field effect transistor having a drain to the common drain is connected, actually It is possible to accurately and accurately evaluate the characteristics of the NOR logic circuit under the condition where the appropriate bias effect occurs.

According to the fourth aspect of the present invention, a plurality of semiconductor logic circuits provided in the semiconductor circuit device and having semiconductor elements as constituent elements are connected in series to odd-numbered stages, and the output terminal of the last-stage semiconductor logic circuit is connected to the odd-numbered stages. In the characteristic evaluation device configured to be connected to the input terminal of the first-stage semiconductor logic circuit, the bias effect generating means changes the power supply voltage applied to the electrode of the semiconductor element under the condition of the occurrence of the bias effect. The oscillation waveform of the terminal is measured by the measuring means, and the characteristics of the semiconductor logic circuit are evaluated. For this reason, it becomes possible to accurately and accurately evaluate the characteristics of the semiconductor logic circuit provided in the semiconductor circuit device under the condition of the occurrence of the bias effect according to the actual condition.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a reference example according to a characteristic evaluation device.

FIG. 2 is a circuit diagram showing a configuration of a first embodiment of the invention relating to a characteristic evaluation device.

FIG. 3 is a circuit diagram showing a configuration of a second embodiment of the invention relating to a characteristic evaluation device.

FIG. 4 is an explanatory diagram showing a configuration of one embodiment of the invention relating to a semiconductor circuit device;

FIG. 5 is a circuit diagram showing a configuration of a conventional semiconductor circuit characteristic evaluation device.

[Explanation of symbols]

 10, 10a, 10b n-MOSFET 20, 20a, 20b p-MOSFET 21 n-MOSFET 22 p-MOSFET 31a to 31n inverter logic circuit 32a to 32n NAND logic circuit 33a to 33n NOR logic circuit 41 semiconductor chip 42 semiconductor Integrated circuit

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28, 31/26 H01L 21/66

Claims (4)

(57) [Claims] 1. A semiconductor logic circuit comprising a semiconductor element.
A plurality of the semiconductor logic circuits are connected in series with each other in odd-numbered stages.
The output terminal of the last semiconductor logic circuit is connected to the first
Connected to the input terminal of the semiconductor logic circuit, the output terminal
Measuring the oscillation waveform of the semiconductor logic circuit
In a semiconductor circuit characteristic evaluation device for evaluating characteristics of a semiconductor device, the semiconductor device is connected to an electrode of the semiconductor element and is applied to the electrode.
A bias effect generating means for changing a power supply voltage and an oscillation waveform at an output terminal of the last-stage semiconductor logic circuit are measured.
Measuring means for measuring, wherein the semiconductor element has a first p-channel field-effect transistor, a common source and a common drain with the first p-channel field-effect transistor, A second p-channel field-effect transistor connected in parallel to the channel-type field-effect transistor; and an n-channel field-effect transistor having a drain connected to the common drain, wherein the semiconductor logic circuit is a NAND logic circuit. An input terminal is provided at a gate of the first p-channel field-effect transistor and a gate of the n-channel field-effect transistor; and an output terminal is provided at the common drain and a drain of the n-channel field-effect transistor. The bias effect generating means is connected to the common source, and raises the voltage of the source. First bias effect generating means for lowering the potential from a power supply voltage, and second bias effect generating means connected to the source of the n-channel field effect transistor for raising the voltage of the source above a low potential power supply voltage. A measuring device connected to a measuring pad connected to an output terminal of a NAND logic circuit at a final stage, and measuring an oscillation waveform for evaluating the characteristics of the NAND logic circuit; and having a high potential pad for supplying a power supply voltage of the high potential to the first bias effect generating means, and said low-potential pads for supplying a power supply voltage of the low potential to the second bias effect generating means Equipment for evaluating the characteristics of semiconductor circuits. 2. A semiconductor logic circuit is constituted by semiconductor elements.
A plurality of the semiconductor logic circuits are connected in series with each other in odd-numbered stages.
The output terminal of the last semiconductor logic circuit is connected to the first
Connected to the input terminal of the semiconductor logic circuit, the output terminal
Measuring the oscillation waveform of the semiconductor logic circuit
In a semiconductor circuit characteristic evaluation device for evaluating characteristics of a semiconductor device, the semiconductor device is connected to an electrode of the semiconductor element and is applied to the electrode.
A bias effect generating means for changing a power supply voltage and an oscillation waveform at an output terminal of the last-stage semiconductor logic circuit are measured.
Measuring means for measuring, wherein the semiconductor element has a first n-channel field-effect transistor, a common source and a common drain with the first n-channel field-effect transistor, and A second n-channel field-effect transistor connected in parallel to the channel-type field-effect transistor; and a p-channel field-effect transistor having a drain connected to the common drain, wherein the semiconductor logic circuit is a NOR logic circuit. An input terminal is provided at a gate of the p-channel field-effect transistor and a gate of the first n-channel field-effect transistor; and an output terminal is provided at a drain and the common drain of the p-channel field-effect transistor. Wherein the bias effect generating means is connected to a source of the p-channel type field effect transistor. A first bias effect generating means connected to lower the voltage of the source below a high potential power supply voltage; and a second bias effect generating means connected to the common source and raising the voltage of the source above the low potential power supply voltage. And a bias effect generating means, wherein the measuring means is connected to a measuring pad connected to an output terminal of a NOR logic circuit in a final stage, and is a measuring instrument for measuring an oscillation waveform for evaluating the characteristics of the NOR logic circuit. , said first high-potential pad for supplying a power supply voltage of the high potential to the bias effect generating means, to have a low potential pad for supplying the low-potential power supply voltage to the second bias effect generating means Characteristic evaluation device for semiconductor circuits. Wherein said low-potential pads, the n connected to the substrate or well to form a channel-type field effect transistor, the high-potential pads, the substrate or well to form the p-channel type field effect DOO la Njisuta The device for evaluating characteristics of a semiconductor circuit according to claim 1 , wherein the device is connected. 4. A semiconductor circuit device incorporating the semiconductor circuit evaluation device according to claim 1, 2 or 3 .