JP2001091599A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit having a circuit accurately measuring a threshold voltage and current-voltage characteristics with no need of a specialized terminal. SOLUTION: In a measurement for a PMOS 11, a TEST 1 is set at a high level, a transfer gate 12 is set at an off state, and a transfer gate 13 is set at an on state. In this condition, an external input terminal 1 is set at a VDD potential, and an external input terminal 2 is lowered from the VDD level, a current value in the PMOS 11 is measured, then a threshold voltage and current-voltage characteristics of the PMOS 11 diode-connected are obtained. In an NMOS 14, a TEST 2 is set at a high level, a transfer gate 16 is set at an off state, and a transfer gate 15 is set an on state; then a measurement is done. In normal operation mode, both the TEST 1 for a first measurement mode signal and the TEST 2 for a second test mode signal are set at a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit having means for measuring the characteristics of constituent elements even after being sealed with a mold resin or the like.

[0002]

2. Description of the Related Art Conventionally, as means for measuring the characteristics of constituent elements of a semiconductor integrated circuit even after sealing, a MOS transistor for measurement arranged in an integrated circuit and a M transistor for measurement from outside are used.
2. Description of the Related Art There is known a semiconductor integrated circuit having measuring means including a measuring terminal for measuring a current by applying a voltage to an OS transistor.

FIG. 6 is a circuit diagram of the first prior art transistor characteristic measuring means. The source of the measuring PMOS 62 having the same characteristics as the P-channel MOS transistor (hereinafter abbreviated as PMOS) used in the internal circuit is a power supply V.
The gate and the drain are connected to the first measuring terminal 61. Similarly, the source of the measurement NMOS 64 having the same characteristics as the N-channel MOS transistor (hereinafter abbreviated as NMOS) used in the internal circuit is connected to the ground G.
The gate and the drain are connected to the second measuring terminal 63. When measuring the PMOS 62, the potential of the first measurement terminal 61 is decreased from the potential of the power supply VDD toward the potential side of the ground GND, and the current starts flowing out of the first measurement terminal 61 and the current value becomes a predetermined value. The threshold voltage can be obtained by measuring the gate voltage when the value becomes the value, and the voltage-current characteristics of the PMOS 62 in a so-called diode connection state in which the gate and the drain are connected can be measured. Similarly, the measurement of the NMOS 64 is performed by increasing the potential of the second measurement terminal 63 from the potential of the ground GND and measuring the current.
The voltage-current characteristics of the NMOS 64 in a diode-connected state can be measured.

As described above, in the transistor characteristic measuring means of the first conventional example shown in FIG. 6, not only the threshold voltage of the NMOS and the PMOS but also the voltage vs. the current in the diode connection which sensitively reflects the variation in the channel length of the MOS transistor. Since the characteristics can be measured, effective data can be obtained in a check of good / defective of the integrated circuit or an analysis of the cause of a defective product. On the other hand, two dedicated measuring terminals are required.
There was a drawback that required terminals.

On the other hand, a transistor characteristic measuring means which does not require a dedicated measuring terminal by using the measuring terminal also as an input terminal originally provided in the semiconductor integrated circuit is disclosed in Japanese Patent Application Laid-Open No. Hei 8-005702. Second conventional example).

FIG. 7 is a circuit diagram of a second conventional transistor characteristic measuring means. In FIG. 7, the transistor characteristic measuring means includes a first input circuit section including a first external input terminal 1, a protection resistor 3 and an input inverter 5, a second external input terminal 2, a protection resistor 4, and an input inverter 6. , A measuring PMOS 71 having a source connected to the power supply VDD and a gate connected to the input terminal of the input inverter 5, and a source connected to the ground GND and a gate connected to the input terminal of the input inverter 6. The connected measurement NMOS 74 and the measurement mode signal TE
ST is input, one end of a signal transmission terminal is connected to the drain of the PMOS 71, and the other end is connected to the second external input terminal 2. A transfer gate 72 is connected to the gate input terminal, and the measurement mode signal TEST is input to the gate input terminal. One end is NMO
A transfer gate 73 is connected to the drain of S74 and the other end is connected to the first external input terminal 1.

When the first external input terminal 1 and the second external input terminal 2 are used as normal input terminals, by setting the measurement mode signal TEST to a low level,
Transfer gates 72 and 73 are turned off, and P
Since no current flows through the MOS 71 and the NMOS 74, both the first external input terminal 1 and the second external input terminal 2 can be used as independent input terminals.

At the time of measuring the characteristics of the PMOS 71 and the NMOS 74, the measurement mode signal TEST is set to the high level, and the transfer gate 72 and the transfer gate 73 are turned on. In the measurement of the threshold voltage of the PMOS 71, the voltage of the first external input terminal 1 is changed to the power V
The threshold voltage of the PMOS 71 is obtained by measuring the voltage of the first external input terminal 1 when the current flowing from the second external input terminal 2 becomes a predetermined current value by lowering the potential from the potential of DD. Similarly, in the measurement of the threshold voltage of the NMOS 74, the voltage of the second external input terminal 2 is increased from the potential of the ground GND while an appropriate voltage higher than the ground GND is applied to the external input terminal 1, and the first external The threshold voltage of the NMOS 74 can be obtained by measuring the voltage of the second external input terminal 2 when the current flowing from the input terminal 1 reaches a predetermined current value.

In the transistor characteristic measuring means of the second conventional example shown in FIG. 7, the measurement mode signal TEST is generated internally by processing such as setting a flag in a specific register in the semiconductor integrated circuit, and the transistor characteristic shown in FIG. Since it can be supplied to the measuring means, there is an advantage that it is not necessary to add an external terminal as compared with the first conventional example.

However, the transistor characteristic measuring means of the second conventional example shown in FIG. 7 has a disadvantage that the measurement of the voltage-current characteristic becomes inaccurate. Although it has almost no effect on microamp-class minute current measurement like threshold voltage measurement, it measures like a voltage-current characteristic measurement because it measures current with the measurement transistor and transfer gate connected in series. In the measurement of the region where the current flowing through the transistor for measurement is equal to or greater than milliamps, the on-resistance of the transfer gate cannot be ignored, and the accurate voltage-current characteristics of the transistor for measurement cannot be measured.

[0011]

As described above, in order to mount the transistor characteristic measuring means of the first conventional example, it is necessary to add a dedicated measuring terminal to the semiconductor integrated circuit. In the conventional example, although the external input terminal also serves as the measurement terminal, it is not necessary to add the terminal, but there is a disadvantage that the measurement accuracy is reduced in the measurement of the voltage-current characteristics.

An object of the present invention is to eliminate the necessity of additional terminals for measurement and to remove elements other than a measurement transistor from a current path for measurement, thereby making it possible to measure a threshold voltage and a voltage-current characteristic. It is an object of the present invention to provide a semiconductor integrated circuit including a transistor characteristic measuring unit that does not cause a measurement error.

[0013]

A semiconductor integrated circuit according to a first aspect of the present invention has a first external input terminal and one end connected to the first external input terminal.
A first protection resistor connected to an external input terminal of
A first input circuit including an input terminal connected to the other end of the protection resistor, and a first input inverter for transmitting an inverted signal of the input signal from the first external input terminal to an internal circuit;
A second protection resistor having one end connected to the second external input terminal and an input terminal connected to the other end of the second protection resistor, and an input signal from the second external input terminal. A second input circuit including a second input inverter that transmits an inverted signal of the first input terminal to the internal circuit, and a measurement in which a source is connected to the first external input terminal and a drain is connected to the second external input terminal. A measuring N-channel MOS transistor having a source connected to the second external input terminal and a drain connected to the first external input terminal.
The OS transistor and one end are connected to a high-potential power supply and the other end is connected to the gate of the P-channel MOS transistor for measurement, and cut off in the first measurement mode for measuring the characteristics of the P-channel MOS transistor for measurement. N
A first switch circuit element that is conductive in the second measurement mode for measuring the characteristics of the channel MOS transistor and in the normal operation mode, and one end connected to the gate of the P-channel MOS transistor for measurement and the other end connected to the second external circuit A second switch circuit element that is connected to an input terminal and conducts in the first measurement mode and cuts off in the second measurement mode and the normal operation mode, and one end connected to the first external input terminal and the other end Is connected to the gate of the measurement N-channel MOS transistor, is turned on in the second measurement mode, and is cut off in the first measurement mode and the normal operation mode. The other end is connected to the ground potential power supply and is cut off in the second measurement mode and is connected to the gate of the channel MOS transistor. The constructed and a fourth switch circuit elements that conduct the measurement mode and the normal operation mode. Alternatively, the source of the measuring P-channel MOS transistor is connected to a high potential power supply,
The source of the OS transistor may be connected to a low-potential power supply. In addition, the second switch circuit element and the third switch are provided on the assumption that the measurement of the measurement P-channel MOS transistor and the measurement N-channel MOS transistor is performed simultaneously. The circuit element may be made conductive in the measurement mode, and the first switch circuit element and the fourth switch circuit element may be made conductive in the normal operation mode.

According to a second aspect of the present invention, there is provided a semiconductor integrated circuit having an external input terminal and a protection resistor having one end connected to the external input terminal, an input terminal connected to the other end of the protection resistor, and an input signal from the external input terminal. An input circuit including an input inverter for transmitting an inversion signal to the internal circuit, a measurement P-channel MOS transistor having a source connected to the high potential power supply and a drain connected to the external input terminal, and a source connected to the ground potential power supply. A measuring N-channel MOS transistor having a drain connected to the external input terminal and one end connected to the high potential power supply and the other end connected to the measuring P-channel MOS transistor
In the first measurement mode, which is connected to the gate of the S transistor and measures the characteristics of the measurement P-channel MOS transistor, it is cut off in the first measurement mode and in the second measurement mode in which the characteristics of the measurement N-channel MOS transistor is measured and in the normal operation mode. A first switch circuit element, one end of which is connected to the gate of the P-channel MOS transistor for measurement and the other end of which is connected to the external input terminal, and which conducts in the first measurement mode; A second switch circuit element which is cut off in a normal operation mode, one end of which is connected to the external input terminal and the other end of which is connected to the gate of the N-channel MOS transistor for measurement, and which conducts in the second measurement mode to be conductive; A third switch circuit element which is cut off in the measurement mode and the normal operation mode, and one end of which is connected to the measurement mode. A fourth switch circuit element which is connected to the gate of the N-channel MOS transistor and the other end of which is connected to the ground potential power supply, is cut off in the second measurement mode, and is conductive in the first measurement mode and the normal operation mode; It is configured with.

[0015]

FIG. 1 is a circuit diagram of a first embodiment of a transistor characteristic measuring means provided in a semiconductor integrated circuit according to the present invention. In FIG. 1, the transistor characteristic measuring means includes a first input circuit section including a first external input terminal 1, a protection resistor 3, and an input inverter 5, and a first input circuit section disposed adjacent to the first external input terminal 1. And a second input circuit section including a second external input terminal 2, a protection resistor 4 and an input inverter 6, and a measurement in which a source is connected to the first external input terminal 1 and a drain is connected to the second external input terminal 2. A PMOS 11 and a measuring NMOS 14 having a source connected to the second external input terminal 2 and a drain connected to the first external input terminal 1 are provided.

Further, the transistor characteristic measuring means shown in FIG.
Is supplied to the gate input terminal and one end of the signal transmission terminal is connected to the power supply VDD.
A first transfer gate 12 connected to the gate of the PMOS 11 and a first measurement mode signal TEST1 which operates as a second switch circuit element and is set to a high level when the PMOS 11 is measured. A second transfer gate 13 which is supplied to one end and one end of a signal transmission end is connected to the gate of the PMOS 11 and the other end is connected to the second external input terminal 2, and operates as a third switch circuit element to measure the NMOS 14 The second measurement mode signal TEST2 which is set to a high level when the signal is supplied to the gate input terminal and one end of the signal transmission terminal is connected to the first external terminal 1
A third transfer gate 15 connected to the gate of the NMOS 14 and the other end thereof, and a signal TEST2B which operates as a fourth switch circuit element and is set to a low level when the NMOS 14 is measured is supplied to the gate input terminal. A fourth transfer gate 16 having one end connected to the gate of the NMOS 14 and the other end connected to the ground GND; an inverter 17 that receives the first measurement mode signal TEST1 and outputs a signal TEST1B; And the signal TEST2B
And an inverter 18 that outputs the same.

The operation of this embodiment will be described below.
First, the operation when measuring the PMOS 11 will be described. The first measurement mode signal TEST1 is set to high level to turn off the first transfer gate 12 and turn on the second transfer gate 13. In this state, the first external input terminal 1 is set to the potential of the power supply VDD, the voltage of the second external input terminal 2 is reduced from the voltage level of the power supply VDD, and the current flowing through the PMOS 11 is changed to the second external input terminal. 2 and the second external input terminal 2
And a current value with respect to the potential difference between the first external input terminal 1 and the first external input terminal 1. A threshold voltage of the PMOS 11 can be obtained from a potential difference between the second external input terminal 2 and the first external input terminal 1 when a current starts flowing to the PMOS 11 and reaches a predetermined value.
Further, the voltage-current characteristics of the PMOS 11 can be obtained by measuring the current at each potential difference while reducing the voltage of the second external input terminal 2 to increase the potential difference. At the time of measurement of the PMOS 11, the second measurement mode signal TEST2 is fixed at a low level, the third transfer gate 15 is turned off, and the fourth transfer gate 16 is turned on.

Next, the operation for measuring the NMOS 14 will be described. The second measurement mode signal TEST2 is set to a high level to turn on the third transfer gate 15 and turn off the fourth transfer gate 16. In this state, the second external input terminal 2 is connected to the ground G
ND potential, and the voltage of the first external input terminal 1
The current value flowing from the NMOS 14 is measured at the first external input terminal 1 by increasing the voltage level from the voltage level of ND, and the current value with respect to the potential difference between the first external input terminal 1 and the second external input terminal 2 is obtained. The threshold voltage of the NMOS 14 can be obtained from the potential difference between the first external input terminal 1 and the second external input terminal 2 when a current starts flowing to the NMOS 14 and reaches a predetermined value. The voltage vs. current characteristics of the NMOS 14 can be obtained by measuring the current at each potential difference while increasing the potential by increasing the voltage of the NMOS 14. When measuring the NMOS 14, the first measurement mode signal TEST1 is fixed at a low level, the second transfer gate 13 is turned off, and the first transfer gate 12 is turned on.

In the normal operation mode, the first measurement mode signal TEST1 and the second test mode signal TE
By fixing both ST2 to the low level, both the PMOS 11 and the NMOS 14 are turned off, so that the operation as the input circuit is not affected, and the input inverter 5 receives the input from the first external input terminal 1 The input inverter 6 outputs the inverted level of the signal to the internal circuit of the semiconductor integrated circuit, and similarly outputs the inverted level of the signal input from the second external input terminal 2 to the internal circuit.

In this embodiment, the first measurement mode signal TE
The ST1 and the second test mode signal TEST2 are supplied from the inside of the integrated circuit as high level (active) by setting corresponding flags in a register (not shown) of the semiconductor integrated circuit and low level by resetting. As in the case of the transistor characteristic measuring means of FIG. 7 of the second conventional example, a dedicated external terminal is not required.

On top of that, the measuring transistor PM
A transfer gate 72 in the transistor characteristic measuring means of FIG. 7 which is a second conventional example is provided between the source and drain of each of the OS 11 and the NMOS 14 and the first external input terminal 1 or the second external input terminal 2. Since the elements 73 and 73 are not inserted, there is an effect that accurate measurement can be performed not only in the measurement of the threshold voltage but also in the measurement in which a large current flows as in the measurement of the voltage-current characteristic.

In FIG. 1, the transfer gates 12, 13, 15, and 16 are preferably complementary transfer gates. FIG. 2 is a circuit diagram in which the transfer gate 12 is configured in a complementary type.
The drain of the PMOS 12b whose drain is connected to the source of the PMOS 12b whose gate is connected to the first measurement mode signal TEST1 forms one end of a signal transmission end of the transfer gate 12, and the source of the NMOS 12a is connected to the drain of the PMOS 12b. The other end of the signal transmission end is formed.

FIG. 3 is a circuit diagram of a second embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention. The transistor characteristic measuring means of the present embodiment uses a PMO having a source shown in FIG.
S11 is a PMOS 31 whose source is connected to the power supply VDD.
And the NMOS 14 whose source is connected to the second external input terminal 2 is replaced with the NMOS 32 whose source is connected to the ground GND. The other circuit configuration is the same as that of FIG. In the operation at the time of measurement, P
In the measurement of the MOS 31, the source of the PMOS 31
DD, the first external input terminal 1
1 is the same as the operation of the first embodiment shown in FIG.
Is fixed to the potential of the ground GND,
The operation is the same as that of the first embodiment shown in FIG. 1 except that the external input terminal 2 need not be used.

In the first embodiment shown in FIG. 1, the first external input terminal 1 is used for measuring both the PMOS 11 and the NMOS 14.
Since the characteristics of the PMOS 11 and the NMOS 14 cannot be measured at the same time because both terminals of the external input terminal 2 and the second external input terminal 2 are used, in the present embodiment, the second external input terminal 2 Only the measurement voltage needs to be applied to measure the current, and when measuring the NMOS 32, the measurement voltage needs to be applied only to the first external input terminal 1 to measure the current.
The measurement of the OS 32 can be performed at the same time, and there is a new effect that the measurement time can be reduced in addition to the effect of the first embodiment.

FIG. 4 is a circuit diagram of a third embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention. In the second embodiment of FIG. 3, the measurement of the PMOS 31 is measured by setting the first measurement mode signal TEST1 to the high level, and the measurement of the NMOS 32 is measured by setting the second measurement mode signal TEST2 to the high level. P
Since the measurement of the MOS 31 and the measurement of the NMOS 32 can be performed at the same time, in the third embodiment of FIG. 4, the measurement mode signal TES is applied to the gate input terminal of the second transfer gate 13 and the gate input terminal of the third transfer gate 15.
T is input, and an inverted signal TESTB of the measurement mode signal TEST is input to the gate input terminal of the transfer gate 12 and the gate input terminal of the transfer gate 16, which is different from the third embodiment of FIG. The circuit configuration is the same. In the present embodiment, in addition to the effect of the third embodiment, a new effect that the number of measurement mode signals supplied from inside the semiconductor integrated circuit to the transistor characteristic measuring means can be reduced is produced.

FIG. 5 is a circuit diagram of a second embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention. In the first, second, and third examples of the first embodiment, two external input terminals are required as the external input terminals that also serve as the measurement terminals. In this example, only one external input terminal is used as a measurement terminal.

In FIG. 5, the transistor characteristic measuring means includes an input circuit section comprising an external input terminal 1, a protection resistor 3 and an input inverter 5, and a measurement in which the drain is connected to the external input terminal 1 and the source is connected to the power supply VDD. PMO for
S51, the drain is connected to the external input terminal 1 and the ground G
A measurement NMOS 54 whose source is connected to the ND is provided.

Further, in the transistor characteristic measuring means of FIG. 5, a signal TEST1B which is set to a low level when measuring the PMOS 51 is supplied to the gate input terminal, one end of the signal transmission end is connected to the power supply VDD, and the other end is connected to the gate of the PMOS 51. Connected first transfer gate 52, P
A first measurement mode signal TEST1 which is set to a high level when measuring the MOS 51 is supplied to the gate input terminal, and one end of a signal transmission end is connected to the gate of the PMOS 51 and the other end is connected to the external input terminal 1. The transfer gate 53 and the second measurement mode signal TEST2 which is set to a high level when measuring the NMOS 54 are supplied to the gate input terminal, and one end of the signal transmission end is connected to the external terminal 1 and the other end is connected to the gate of the NMOS 54. The third transfer gate 55 and a signal TEST2B which is set to a low level when measuring the NMOS 54 are supplied to the gate input terminal, one end of a signal transmission end is connected to the gate of the NMOS 54, and the other end is connected to the ground GND. 4 transfer gate 56 and the first measurement mode signal TEST1 An inverter 57 for outputting a second
Input the measurement mode signal TEST2
And an inverter 58 for outputting B.

When measuring the PMOS 51, the first
, The transfer gate 52 is turned off, and the transfer gate 53 is turned on. In this state, the voltage of the external input terminal 1 is reduced from the voltage level of the power supply VDD, and P
A current value flowing through the MOS 51 is measured at the external input terminal 1, and a current value corresponding to a potential difference between the external input terminal 1 and the power supply VDD is obtained. The threshold voltage of the PMOS 51 is obtained from the potential difference when the current starts flowing to the PMOS 51 and reaches a predetermined value. Further, the current at each potential difference is measured while reducing the voltage of the external input terminal 1 to increase the potential difference. Can be obtained. When the PMOS 51 is measured, the second measurement mode signal TEST2 is fixed at a low level, the transfer gate 55 is turned off, and the transfer gate 56 is turned on.

When the measurement of the NMOS 14 is performed, the second
The measurement mode signal TEST2 is set to a high level, the transfer gate 55 is turned on, and the transfer gate 56 is turned off. In this state, the voltage of the external input terminal 1 is increased from the voltage level of the ground GND, and N
The value of the current flowing through the MOS 54 is measured at the external input terminal 1, and the current value for the potential difference between the external input terminal 1 and the ground GND is determined. The threshold voltage of the NMOS 54 is obtained from the potential difference between the external input terminal 1 and the ground GND when the current starts flowing to the NMOS 14 and reaches a predetermined value. Further, the potential difference is increased while increasing the voltage of the external input terminal 1 to increase the potential difference. , The voltage-current characteristics of the NMOS 54 can be obtained. At the time of measurement of the NMOS 54, the first measurement mode signal TEST1 is fixed at a low level, and the transfer gate 53 is turned off.
The transfer gate 52 is turned on.

In the normal operation mode, the first measurement mode signal TEST1 and the second test mode signal TE
By fixing ST2 to a low level, both the PMOS 51 and the NMOS 54 are turned off, so that the operation as an input circuit is not affected.

In this embodiment, since only one external input terminal is used as a measurement terminal, the degree of freedom in layout design is large, and an increase in the area of the semiconductor integrated circuit chip due to the mounting of the transistor characteristic measuring means is suppressed. be able to. In the present embodiment, only the PMOS is used as the measurement transistor.
Alternatively, only the NMOS may be used.

[0033]

As described above, in the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention, since the external input terminal is also used as the measuring terminal, it is not necessary to add an additional terminal for the measurement, Since there is no element other than the measurement transistor in the current path at the time of the measurement, there is no factor of accuracy deterioration due to a parasitic voltage drop, so that accurate measurement can be performed even in a measurement where a large current flows as in the measurement of the voltage-current characteristic. This has the effect.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an example of a first embodiment of a transistor characteristic measuring means provided in a semiconductor integrated circuit of the present invention.

FIG. 2 is a detailed circuit diagram of a transfer gate.

FIG. 3 is a circuit diagram of a second embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention.

FIG. 4 is a circuit diagram of a third embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention.

FIG. 5 is a circuit diagram of an example of a second embodiment of the transistor characteristic measuring means provided in the semiconductor integrated circuit of the present invention.

FIG. 6 is a circuit diagram of a first conventional transistor characteristic measuring means.

FIG. 7 is a circuit diagram of a transistor characteristic measuring means of a second conventional example.

[Explanation of symbols]

1, 2 external input terminal 3, 4 protection resistor 5, 6 input inverter 11, 12b, 31, 51, 62, 71 PMOS 12, 13, 15, 16, 52, 53, 55, 56, 7
2,73 Transfer gate 12a, 14,32,54 NMOS 17,18,41,57,58,64,74 Inverter 61,63 Measurement terminal

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 21/822 H01L 27/04 E H03K 19/00 F term (reference) 2G003 AA01 AA02 AG09 2G032 AA01 AK14 5F038 BE01 BE05 BH02 BH07 DT02 DT08 EZ20 5J056 AA01 BB01 BB53 BB57 BB60 CC00 DD13 DD28 DD29 FF07 FF09

Claims (8)

[Claims] An input terminal connected to a first external input terminal and a first protection resistor having one end connected to the first external input terminal, and an input terminal connected to the other end of the first protection resistor; A first input circuit including a first input inverter for transmitting an inverted signal of an input signal from an external input terminal to an internal circuit; a second external input terminal and one end connected to the second external input terminal; And a second input inverter having an input terminal connected to the other end of the second protection resistor and transmitting an inverted signal of an input signal from the second external input terminal to an internal circuit. A second input circuit; a P-channel MOS transistor for measurement having a source connected to the first external input terminal and a drain connected to the second external input terminal; a source connected to the second external input terminal Connected to the first external input terminal. N-channel MOS transistor for measurement to which the transistor is connected, one end of which is connected to a high potential power supply and the other end is connected to the gate of the P-channel MOS transistor for measurement,
A first switch circuit element that is cut off in the first measurement mode for measuring the characteristics of the channel MOS transistor and is conductive in the second measurement mode for measuring the characteristics of the measurement N-channel MOS transistor and the normal operation mode; A second terminal connected to the gate of the P-channel MOS transistor for measurement and the other end connected to the second external input terminal, which conducts in the first measurement mode and cuts off in the second measurement mode and the normal operation mode; A switch circuit element having one end connected to the first external input terminal and the other end connected to the gate of the measurement N-channel MOS transistor, and conducting in the second measurement mode, A third switch circuit element which is cut off in a normal operation mode, and one end of which is the measurement N-channel MOS transistor A fourth switch circuit element which is connected to a gate and has the other end connected to a ground potential power supply, and cuts off in the second measurement mode and conducts in the first measurement mode and the normal operation mode. Semiconductor integrated circuit. A first external input terminal, a first protection resistor having one end connected to the first external input terminal, and an input terminal connected to the other end of the first protection resistor, A first input circuit including a first input inverter for transmitting an inverted signal of an input signal from an external input terminal to an internal circuit; a second external input terminal and one end connected to the second external input terminal; And a second input inverter having an input terminal connected to the other end of the second protection resistor and transmitting an inverted signal of an input signal from the second external input terminal to an internal circuit. A second input circuit, a measuring P-channel MOS transistor having a source connected to a high-potential power supply and a drain connected to the second external input terminal, and a first external input having a source connected to a ground potential power supply; Measurement N with drain connected to terminal A channel MOS transistor, one end of which is connected to the high-potential power supply and the other end of which is connected to the gate of the measurement P-channel MOS transistor, for measuring characteristics of the measurement P-channel MOS transistor;
A first switch circuit element that is turned off in the second measurement mode for measuring the characteristics of the measurement N-channel MOS transistor and turned on in the normal operation mode, and one end is connected to the gate of the measurement P-channel MOS transistor. A second switch circuit element which is connected and the other end of which is connected to the second external input terminal and which conducts in the first measurement mode and cuts off in the second measurement mode and the normal operation mode; A third switch which is connected to the external input terminal of the first and the other end is connected to the gate of the N-channel MOS transistor for measurement and conducts in the second measurement mode and cuts off in the first measurement mode and the normal operation mode. A circuit element having one end connected to the gate of the measurement N-channel MOS transistor and the other end connected to the ground potential power supply The semiconductor integrated circuit characterized by comprising a fourth switching circuit elements that conduct the Blocked the first measurement mode and the normal operating mode in the second measurement mode is. 3. A first protection resistor having one end connected to a first external input terminal and one end connected to the first external input terminal, and an input terminal connected to the other end of the first protection resistor. A first input circuit including a first input inverter for transmitting an inverted signal of an input signal from an external input terminal to an internal circuit; a second external input terminal and one end connected to the second external input terminal; And a second input inverter having an input terminal connected to the other end of the second protection resistor and transmitting an inverted signal of an input signal from the second external input terminal to an internal circuit. A second input circuit, a measuring P-channel MOS transistor having a source connected to a high-potential power supply and a drain connected to the second external input terminal, and a first external input having a source connected to a ground potential power supply; Measurement N with drain connected to terminal A channel MOS transistor, one end of which is connected to the high-potential power supply and the other end of which is connected to the gate of the measuring P-channel MOS transistor, for measuring characteristics of the measuring P-channel MOS transistor and the measuring N-channel MOS transistor A first switch circuit element that is cut off in the characteristic measurement mode and is turned on in the normal operation mode; and one end is connected to the gate of the P-channel MOS transistor for measurement and the other end is connected to the second external input terminal. A second switch circuit element that conducts in the measurement mode and shuts off in the normal operation mode; and one end connected to the first external input terminal and the other end connected to the gate of the measurement N-channel MOS transistor. Conducted in the measurement mode and in the normal operation mode A third switch circuit element to be cut off, one end connected to the gate of the measurement N-channel MOS transistor and the other end connected to the ground potential power supply, cut off in the transistor characteristic measurement mode and turned on in the normal operation mode; 4. A semiconductor integrated circuit, comprising: the switching circuit element according to claim 4. 4. The first switch circuit, wherein the second switch circuit element and the third switch circuit are complementary transfer gates that are turned on by a measurement mode signal that goes high in the transistor characteristic measurement mode. 4. The semiconductor integrated circuit according to claim 3, wherein the element and the fourth switch circuit are complementary transfer gates that conduct when the inverted signal of the measurement mode signal is at a high level. 5. A protection resistor having one end connected to the external input terminal and one end connected to the external input terminal, and an input terminal connected to the other end of the protection resistor for transmitting an inverted signal of an input signal from the external input terminal to an internal circuit. An input circuit including an input inverter, a P-channel MOS transistor having a source connected to a high-potential power supply and a drain connected to the external input terminal, and one end connected to the high-potential power supply and the other end connected to the high-potential power supply. A first switch circuit element which is connected to the gate of the P-channel MOS transistor for use and is cut off in the measurement mode for measuring the characteristics of the P-channel MOS transistor for measurement and turned on in the normal operation mode; And the other end is connected to the external input terminal and conducts in the first measurement mode, and is turned on in the normal operation mode. And a second switch circuit element for shutting off the semiconductor integrated circuit. 6. A protection resistor having one end connected to the external input terminal and one end connected to the external input terminal, and an input terminal connected to the other end of the protection resistor for transmitting an inverted signal of an input signal from the external input terminal to an internal circuit. An input circuit including an input inverter, an N-channel MOS transistor having a source connected to a ground potential power supply and a drain connected to the external input terminal, one end connected to the external input terminal and the other end connected to the measurement terminal. For N
A first switch circuit element that is connected to the gate of the channel MOS transistor and conducts in the measurement mode and cuts off in the normal operation mode; one end is connected to the gate of the measurement N-channel MOS transistor and the other end is connected to the ground potential power supply A second switch circuit element that is turned off in the measurement mode and turned on in the normal operation mode. 7. A protection resistor having one end connected to the external input terminal and one end connected to the external input terminal, and an input terminal connected to the other end of the protection resistor for transmitting an inverted signal of an input signal from the external input terminal to an internal circuit. An input circuit including: an input inverter; a P-channel MOS transistor having a source connected to a high potential power supply and a drain connected to the external input terminal; a drain connected to the external input terminal having a source connected to a ground potential power supply Is connected to the high-potential power supply and the other end is connected to the gate of the P-channel MOS transistor for measurement to measure characteristics of the P-channel MOS transistor for measurement.
A first switch circuit element that is turned off in the second measurement mode for measuring the characteristics of the measurement N-channel MOS transistor and turned on in the normal operation mode, and one end is connected to the gate of the measurement P-channel MOS transistor. A second switch circuit element that is connected and the other end is connected to the external input terminal and is conductive in the first measurement mode and cut off in the second measurement mode and the normal operation mode; one end is connected to the external input terminal The other end is connected to the measurement N
A third switch circuit element connected to the gate of the channel MOS transistor for conducting in the second measurement mode and shutting off in the first measurement mode and the normal operation mode; one end of the gate of the measurement N-channel MOS transistor And a fourth switch circuit element, the other end of which is connected to the ground potential power supply and cut off in the second measurement mode and turned on in the first measurement mode and the normal operation mode. Semiconductor integrated circuit. 8. The first switching circuit element according to claim 1, wherein
A complementary transfer gate that is turned on by a first measurement mode signal that is at a high level in the measurement mode described above, wherein the first switch circuit element is turned on when an inverted signal of the first measurement mode signal is at a high level. A complementary transfer gate, wherein the third switch circuit element is a complementary transfer gate that is turned on by a second measurement mode signal that goes high in the second measurement mode; and the fourth switch 8. The semiconductor integrated circuit according to claim 1, wherein said circuit element is a complementary transfer gate which conducts when an inverted signal of said second measurement mode signal is at a high level.