KR20000060215A - Threshold voltage measuring circuit - Google Patents

Abstract

PURPOSE: A threshold voltage measuring circuit is provided to reduce the fault rate of a semiconductor package by measuring the threshold voltage within each device. CONSTITUTION: A threshold voltage measuring circuit comprises a second PMOS transistor(P2) which receives a power voltage(Vdd) at a source and an enable signal(PE) at a gate. A gate of a first PMOS transistor(P1) is connected to a drain of the second PMOS transistor(P2). The first PMOS transistor(P1) receives the power voltage(Vdd) at a source. A drain of the first PMOS transistor(P1) is connected to a second port of an element. A first transmission gate(TRANS1) is provided to connect the drain of the second PMOS transistor(P2) to a first port of the element. A second NMOS transistor(N2) receives a disable signal(NE) at a gate. A source of the NMOS transistor(N2) is grounded. A gate of a first NMOS transistor(N1) is connected to the drain of the second NMOS transistor(N2). A second transmission gate(TRANS2) is provided to connect the drain of the second NMOS transistor(N2) to the first port of the element.

Description

Threshold Voltage Measuring Circuit {THRESHOLD VOLTAGE MEASURING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a threshold voltage measuring circuit, and more particularly, to a threshold voltage measuring circuit which enables to measure the threshold voltage of a corresponding device in any case of a wafer or package state.

FIG. 1 is a circuit diagram for measuring a threshold voltage of a device in a conventional wafer state. As shown in FIG. 1, a transistor for checking a threshold voltage Vt is checked in a surplus space SCRIBE LANE between elements of a wafer. Sample and check about 5 points per sheet.

In this case, the NMOS transistor has a gate voltage when the current (I _DS ) flowing from the drain to the source becomes 1 하여 by applying a voltage to the gate after applying 0 volts to the source and 5 volts to the drain. The gate voltage becomes the threshold voltage Vtn, and in the case of the PMOS transistor, -5 volts is applied to the source and 0 volts is applied to the drain, and the gate voltage at which the current I _DS flowing from the drain to the source becomes 1 ㎂ is the threshold voltage Vtp. )

However, in the conventional circuit, it is possible to check only in the wafer state, and because the sampling check is performed instead of all the devices in the wafer state, the reliability of the threshold voltage (Vt) for each device is lowered. There was a problem that the efficiency is lowered because it should be checked.

Accordingly, an object of the present invention is to provide a threshold voltage measuring circuit that can measure the threshold voltage of a corresponding device in any case of a wafer or a package state.

1 is a circuit diagram for measuring a threshold voltage of a device in a conventional wafer state.

2 is a circuit diagram illustrating a threshold voltage measurement according to the present invention.

*** Description of the symbols for the main parts of the drawings ***

P1, P2: PMOS transistor N1, N2: NMOS transistor

TRNS1: first transmission gate TRNS2: second transmission gate

According to an aspect of the present invention, there is provided a PMOS transistor (P2) for receiving a power supply voltage (Vdd) to a source and an enable signal (PE) to a gate; A PMOS transistor (P1) receiving a power supply voltage (Vdd) from the source, the drain of which is connected to a second port of the device, and whose gate is connected to the drain of the PMOS transistor (P2); A first transfer gate TRNS1 connected to the positive input terminal and the inverting input terminal to enable / disable signals PE and NE to connect the drain of the PMOS transistor P2 to the first port of the device; An NMOS transistor N2 having a source grounded and receiving a disable signal NE at a gate thereof; An NMOS transistor N1 having a source grounded, a drain connected to a first port of the device, and a gate connected to a drain of the NMOS transistor N2; The second transmission gate TRNS2 connects the drain of the NMOS transistor N2 and the first port of the device by receiving the disable / enable signals NE and PE at the positive input terminal and the inverting input terminal, respectively. As can be achieved, the circuit of the embodiment is well illustrated in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, when the enable signal PE is 1 (high) and the disable signal NE is 1 (high), the first transfer gate TRNS1 receives the input voltage from the port 1 as the PMOS transistor P1. The second transfer gate TRNS2 transfers the input voltage of the port 2 when the enable signal NE is 0 (low) and the disable signal NE is 0 (low). It serves to transfer the gate voltage of the MOS transistor N1.

When the threshold voltage is not measured, the enable / disable signal is set to 0 (low) and 1 (high), respectively.

The concrete contrast is shown in Table 1 below.

PE NE Test mode Vtp measurement One One Vtn measurement 0 0 User Mode (Disable) 0 One

First, as an example of the threshold voltage Vtp measurement process, when the enable signal PE and the disable signal NE are 1, the first transmission gate TRNS1 is turned on and the second transmission is performed. Gate TRNS2 is turned off.

At this time, if the power supply voltage Vdd is 5 volts, a voltage of 5 volts is applied to the port 1 from the outside (tester), and when the voltage is gradually lowered, the voltage of the port 1 is transferred through the first transfer gate TRNS1 to the PMOS transistor ( It is applied at the gate voltage of P1).

Next, the drain and source current I _DS flowing from the power supply voltage Vdd through the PMOS transistor P1 is measured at the port 2, and the drain and source current I _DS measured at the port 2 is 1. The threshold voltage Vtp can be known from the applied voltage of the port 1 at ㎂.

Next, in contrast to the above, in the process of measuring the threshold voltage Vtn, when the enable signal PE and the disable signal are both 0, the second transmission gate TRNS2 is turned on and the voltage is gradually increased from 0 volts to the port 2. Is applied to increase the gate voltage of the NMOS transistor N1 to measure the drain and source current I _DS of the NMOS transistor N1 at the port 1. The voltage applied to the port 2 when the current I _DS is 1 2 becomes the threshold voltage Vtn.

As described above, the threshold voltage measuring circuit of the present invention can measure the threshold voltage by being embedded in all devices other than the sampling method, thereby reducing the defect rate after shipment of the package and increasing the efficiency of failure analysis.

Claims (1)

A PMOS transistor P2 receiving a power supply voltage Vdd to the source and an enable signal PE to a gate thereof; A PMOS transistor (P1) receiving a power supply voltage (Vdd) from the source, the drain of which is connected to a second port of the device, and whose gate is connected to the drain of the PMOS transistor (P2); A first transfer gate TRNS1 connected to the positive input terminal and the inverting input terminal to enable / disable signals PE and NE to connect the drain of the PMOS transistor P2 to the first port of the device; An NMOS transistor N2 having a source grounded and receiving a disable signal NE at a gate thereof; An NMOS transistor N1 having a source grounded, a drain connected to a first port of the device, and a gate connected to a drain of the NMOS transistor N2; A second transfer gate TRNS2 configured to connect the drain of the NMOS transistor N2 and the first port of the device by receiving the disable / enable signals NE and PE at the positive input terminal and the inverting input terminal, respectively. Threshold voltage measuring circuit.