JP2894090B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device integrated using CMOS transistors.

[0002]

2. Description of the Related Art In a normal CMOS LSI, a static current hardly flows when the circuit operation is in a stable state, whereas a considerably large static current flows in the case of a failure in many cases. By taking advantage of this fact, C
As a test of a MOS circuit, a fault can be found by measuring a static current of a power supply.

[0003] This is usually called a current test, and current is generally measured by an external LSI tester. In this test, the power supply current at that time is measured while running the test pattern with the LSI tester. In this way, the current flowing through the switching of the output buffers also will be measured, normally, because it may be abnormal erroneous determination, to remove the current due to switching of the output buffer, the output terminal should be left as an open circuit condition, A test is performed to run the test pattern to the measurement pattern, stop the pattern there, and measure the power supply current. However, even in this test, the current flowing through the input terminal with the resistor is measured, so that it is difficult to determine the determination condition.

[0004]

As described above, when the power supply current is measured by an external LSI tester, a current other than the current caused by the LSI failure is also measured depending on the input / output state at the time of measurement. Therefore, it is difficult to simply determine whether or not there is a failure in the LSI simply by measuring the power supply current.

In the conventional test pattern creation method, the location of the fault location of the internal circuit and the fault information must be propagated to the output terminal, so that the circuit scale becomes large as in the current tendency of the gate array. As a result, a great deal of man-hours must be spent on creating test patterns.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
Operation and non-operation are controlled by a binary control signal externally input to the semiconductor chip, and in one state of the binary control signal, the original signal processing intended by the semiconductor device is performed.
The magnitude of the DC power supply current flowing between the high and low power supply lines of each internal gate provided on the semiconductor chip is detected as the level of the DC potential of the power supply wiring, and the binary signal
To be different from the signal output path of the internal gate.
A test circuit is provided for outputting to the outside of the semiconductor chip through an independent output path .

[0007]

Next, a preferred embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of a first embodiment of the present invention. Referring to FIG. 1, the present embodiment includes a test circuit 1 connected to a ground line 6 of an internal gate 4A.

[0008] As an example of the internal gate 4, PM
The CMOS inverter including the OS transistor P2 and the NMOS transistor N2 is shown. The internal gate 4 receives an input signal IN from a previous circuit (not shown) and transmits an output signal OUT to a next circuit (not shown). The internal gate 4 is not limited to a CMOS inverter, but may be another basic logic gate or a logic circuit combining the basic logic gates.

The test circuit 1 has a PMOS transistor P1 and an NMOS transistor N1 connected in series with a common drain electrode, and an N transistor having a drain electrode connected to the gate electrode of the NMOS transistor N1.
And a MOS transistor N3. Gate electrode of PMOS transistor P1 and NMOS transistor N
The gate electrode 3 is connected to a test switching terminal 3, to which a test signal TST is input from outside the chip. Gate electrode of NMOS transistor N1 and NMO
The drain electrode of the S transistor N3 is connected to the ground line 6. PMOS transistors P1 and N
The common drain electrode of the MOS transistor N1 is connected to the failure detection terminal 2, from which a test result signal E is output to the outside of the chip.

In the present embodiment, the test circuit 1 is provided near an internal gate 4 provided inside an LSI chip. On the other hand, the test switching terminal 3 and the failure detection terminal 2 are provided in the vicinity of the input / output circuit area of the LSI which is usually arranged at the periphery of the chip.

In this embodiment, during normal operation,
Fix the test switching terminal 3 to the high state,
S transistor P1 is turned off, NMOS transistor N3
Is turned on, the NMOS transistor N1 is turned off, and the failure detection terminal 2 is set to a high impedance state.

In the test mode, the test switching terminal 3 is set to low. Therefore, the NMOS transistor N3
Is turned off, the PMOS transistor P1 is turned on, and the NMOS transistor N1 is turned off, so that the potential of the failure detection terminal 2 is at V _DD (potential of the high power supply line 8). In this state, when turning the input signal IN of the level at the input end of the inner gate 4A, a defect such as a gate short-circuit, a current flows through the ground line 6 by the current gate potential V _G of the NMOS transistor increases I do. When the potential VG becomes higher than the threshold voltage of the NMOS transistor N1, the NMOS transistor N1 turns on and the potential of the output signal E of the failure detection terminal 2 becomes V _DD
It becomes closer to the ground level. This makes it possible to know that a failure has occurred.

In FIG. 1, a terminal 9 provided to prevent a decrease in performance in a normal operation state is kept open in a test mode.

Next, a second embodiment of the present invention will be described. FIG. 2 is a block diagram of a second embodiment of the present invention. Referring to FIG. 2, the present embodiment has a configuration in which a plurality of test circuits 1 are provided, and a decoder 7 can select test switching terminals of those test circuits.

In this embodiment, in the test mode, the decoder 7 performs a test for each of the internal gates 4B, 4C, 4D, and 4E, so that if there is a failure, the location of the failure can be narrowed down to some extent.

[0016]

As described above, according to the present invention,
By providing a test circuit for detecting a change in the potential of the power supply line inside the CMOS LSI, it is possible to improve the accuracy of detecting a failure of the internal gate.

In addition, since the test only requires the actualization of a failure, the number of test patterns can be significantly reduced as compared with a normal number of patterns, and the number of man-hours required for creating test patterns can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test circuit 2 Failure detection terminal 3 Test switching terminal 4A, 4B, 4C, 4D, 4E Internal gate 6 Ground line 7 Decoder 8 Higher power supply line 9 Terminal

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/26 G01R 31/28 H01L 21/66

Claims (2)

(57) [Claims] An operation and a non-operation are controlled by a binary control signal externally input to a semiconductor chip, and a semiconductor device is intended in one state of the binary control signal.
The magnitude of the DC power supply current flowing between the higher and lower power supply lines of each internal gate provided on the semiconductor chip for the original signal processing is detected as the level of the DC potential of the power supply wiring, and the binary signal is detected. Into the signal output of the internal gate
A semiconductor device, comprising: a test circuit that outputs a signal to an outside of a semiconductor chip through an independent output path different from the path . 2. A PMOS field-effect transistor and a first NMOS field-effect transistor having their drain electrodes connected to each other, and the drain electrode is connected to the first NM.
A second NMOS field-effect transistor connected to a gate electrode of the OS field-effect transistor; a high power supply potential applied to a source electrode of the PMOS field-effect transistor; a gate electrode of the PMOS field-effect transistor; Inputting a binary control signal from the outside of the semiconductor chip to the gate electrode of the NMOS field effect transistor, connecting the gate electrode of the first NMOS field effect transistor to the ground wiring of the internal gate provided on the semiconductor chip; A semiconductor device comprising: a test circuit configured to take out an output signal to the outside of the semiconductor chip from drain electrodes of the PMOS field effect transistor and the first NMOS field effect transistor.