JP2671832B2 - Input level test circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input level test circuit, and more particularly to a CMOS digital LSI input level test circuit.

[0002]

2. Description of the Related Art As shown in FIG. 3, a conventional input level test circuit includes a plurality of input terminals 31 to 33, input buffer circuits 35 to 36, an output buffer 38, and an output terminal 3.
4 and an internal circuit 39.

More specifically, referring to FIG. 3, the input buffers 35, 36, 37 have their input terminals connected to the input terminals 1, 2,
3 and the output terminals thereof are connected to the internal circuit 9. The output buffer 38 has its input terminal connected to the output of the internal circuit 9 and its output terminal connected to the output terminal 34.

Next, the operation of the conventional input level test will be described.

When measuring an input level in a semiconductor integrated circuit having a plurality of input terminals, a test vector is input to the input terminals 31 to 33 at a voltage corresponding to the input level standard.
The input level test is carried out by inputting to the input terminal, operating the internal circuit 39, and confirming that a normal signal is output from the output terminal 34.

[0006]

This conventional input level testing method is effective because the number of test vectors for testing is small and the number of circuits for testing is not increased when the circuit scale is small. It was

However, recently, as the scale of the circuit becomes larger and the number of test vectors for the test becomes enormous, it becomes difficult to test all the input pins.

Further, since the internal circuit is operated, noise is generated in the power supply and the ground, and the input level cannot be measured correctly.

The present invention has been made in view of the above problems, and when testing an input level in a CMOS digital LSI or the like, an input level test can be performed without being affected by noise due to internal circuit operation. It is an object of the present invention to provide an input level test circuit that can be performed.

[0010]

To achieve the above object, the present invention provides a semiconductor including a plurality of input buffer circuits, at least two first and second output buffer circuits, and an internal circuit. In a circuit for testing an input level of a device, the input buffer circuit and the output buffer circuit both input a control signal for controlling a test mode for testing the input level and a normal operation mode, and in the test mode, the output buffer The circuit outputs a logic level corresponding to the output levels of the plurality of input buffer circuits to the output terminal instead of the output signal of the internal circuit based on the control signal, and the defective buffer of the plurality of input buffer circuits is If there is, the logic level corresponding to the output level of the defective buffer is output according to the input logic level. Providing input level test circuit, characterized in that it is configured to be output to at least any one of an output terminal of the buffer.

The input level test circuit of the present invention preferably comprises a plurality of input buffer circuits and an output buffer circuit, and is a circuit for testing the input level of the input buffer circuit, wherein the plurality of input buffer circuits are provided. The circuits each include an input terminal for inputting an input signal, a control signal input terminal for inputting a control signal for controlling the test mode, and three output terminals, and the output buffer circuit outputs the control signal. Input control signal input terminal, output terminal, 2
At least two output buffer circuits each having one input terminal, the first output terminals of the plurality of input buffer circuits are connected to the first input terminals of the second output buffer circuits, and the second output terminals Are connected to the first input terminal of the first output buffer circuit, the third output terminals are connected to the input terminals of the internal circuit, respectively, and the second input terminal of the first output buffer circuit and the second input terminal of the first output buffer circuit are connected. Second output buffer circuit
Input terminals are respectively connected to the outputs of the internal circuits.

In the input level test circuit of the present invention, preferably, the input buffer circuit is an input buffer connected to an input terminal, and a first P channel having a gate terminal connected to an output of the input buffer. A MOS transistor and a first N-channel MOS transistor, a second P-channel MOS transistor connected between a power source and the first P-channel MOS transistor, and a connection between the first N-channel MOS transistor and ground. And a second N-channel MOS transistor connected to the second N-channel MO transistor, the control signal being input to the gate terminal of the second P-channel MOS transistor.
A signal obtained by inverting the control signal is input to the gate terminal of the S transistor, the drain terminal of the first P-channel MOS transistor is connected to the first output terminal, and the drain of the first N-channel MOS transistor is connected. A terminal is connected to the second output terminal, and an output of the input buffer is connected to the third output terminal.

Further, the input level test circuit of the present invention is
Preferably, the first output buffer circuit includes an output inverter, a tri-state inverter circuit, and a P-channel MOS transistor, and the P-channel MO transistor.
The control signal is input to the gate terminal of the S transistor, the drain terminal is connected to the input of the output inverter and the first input terminal, the source terminal is connected to the power supply, and the tri-state inverter circuit is connected to the control terminal. The control signal is input, the input end is connected to the second input terminal, the output end is connected to the input of the output inverter, and the output of the output inverter is connected to the output terminal. Characterize.

The input level test circuit of the present invention is
Preferably, the second output buffer circuit includes an output inverter, a tri-state inverter circuit, an inverter, and an N-channel MOS transistor, and the gate terminal of the N-channel MOS transistor is controlled by the inverter via the inverter. A signal input terminal, a drain terminal connected to the input of the output inverter and the first input terminal, a source terminal grounded, and a control terminal of the tri-state inverter circuit connected to the control signal input terminal. , Its input is connected to the second input terminal, and the output of the output inverter is connected to the output terminal.

In the present invention, the input buffer of the input buffer circuit is composed of an input inverter that inverts a signal, and the output inverters in the first and second output buffer circuits are output buffers that do not invert a signal. The state inverter may be composed of a tri-state buffer, and the inverter may be composed of a buffer.

[0016]

According to the present invention having the above-mentioned structure, during the input level test, the logic signal corresponding to the signal level of the input buffer is output to the output buffer, and the input level is checked regardless of the output result of the internal circuit. Can test. Therefore, the influence of noise due to the operation of the internal circuit is avoided, and
It is possible to suppress and stabilize the variation of the input level measurement, and to suppress the increase of the test vector even when the internal circuit of the semiconductor integrated circuit further increases in scale. That is, according to the present invention, all input pins can be measured without requiring a huge number of test vectors.

Further, according to the present invention, when a level defect occurs in any of the plurality of input buffer circuits, the logic level corresponding to the level defect is output from the output buffer, so that the input level test is performed. To improve efficiency of defect detection and reduce test cost.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

[0019]

First Embodiment FIG. 1 shows a first input level test circuit of the present invention.
FIG. 3 is a block diagram showing an embodiment.

Referring to FIG. 1, input buffer circuit 200
The output terminal 301 of is connected to the bus and is connected to the input terminal 501 of the second output buffer circuit 203. Also,
The output terminal 302 of the input buffer circuit 200 is bus-connected and connected to the input terminal 401 of the output buffer circuit 202. The output terminal 303 of the input buffer circuit 200 is connected to the input terminal of the internal circuit 19.

The control signal input terminal 300 of the input buffer circuit 200, the control signal input terminal 400 of the output buffer circuit 202, and the control signal input terminal 500 of the second output buffer circuit 203 are connected to the control signal input terminal 100. . The input of the input buffer circuit 200 is connected to the pad 14.

The input terminal 402 of the output buffer circuit 202 is connected to the output of the internal circuit 19, and the output terminal of the output buffer circuit 202 is connected to the pad 16.
The input terminal 502 of the second output buffer circuit 203 is connected to the output of the internal circuit 19, and the second output buffer circuit 2
The output terminal 03 is connected to the pad 17.

In the input buffer circuit 200, the gate terminal of the P-channel MOS transistor 1 is connected to the control signal input terminal 300, the source terminal is connected to the power supply 600, and the drain terminal is connected to the source terminal of the P-channel MOS transistor 2. Has been done.

The gate terminal of the P-channel MOS transistor 2 is connected to the output of the input buffer (also called "buffer") 5, and the drain terminal is connected to the output terminal 301.

The gate terminal of the N-channel MOS transistor 4 is connected to the output of the inverter 12. The input of the inverter 12 is connected to the control signal input terminal 300. The source terminal of the N-channel MOS transistor 4 is connected to the ground (ground), and the drain terminal is N
It is connected to the source terminal of the channel MOS transistor 3.

The gate terminal of the N-channel MOS transistor 3 is connected to the output of the input buffer 5, and the drain terminal is connected to the output terminal 302.

The output of the input buffer 5 is connected to the output terminal 303 and input to the internal circuit 19.

As shown in FIG. 1, a plurality of input buffer circuits are provided, and these are provided in the input buffer circuit 200.
Shall be followed.

In the first output buffer circuit 202,
The gate terminal of the P-channel MOS transistor 6 is connected to the control signal input terminal 400, and the drain terminal is connected to the output of the tri-state inverter circuit 8 and the input of the output inverter 7 and the input terminal 401.

The control terminal of the tri-state inverter circuit 8 is connected to the control signal input terminal 400, and its input is connected to the output of the internal circuit 19 via the input terminal 402. The output of the output inverter 7 is an output terminal (pad)
16 is connected.

In the second output buffer circuit 203,
The gate terminal of the N-channel MOS transistor 11 is connected to the output of the inverter 13, and the drain terminal thereof is connected to the output of the tri-state inverter circuit 9 and the output inverter 10.
, And the input terminal 501, and the source terminal is connected to the ground. The input of the inverter 13 is connected to the control signal input terminal 500.

The control terminal of the tri-state inverter circuit 9 is connected to the control signal input terminal 500, and its input is connected to the output of the internal circuit 19 via the input terminal 502.
Its output is connected to the output inverter 10.

First and second output buffer circuits 202, 2
The tri-state inverters 8 and 9 used in 03 are
When the control signal is "L", its output is in a high impedance state, and when the control signal is "H", it operates as a normal inverter.

Next, the circuit operation of this embodiment will be described with reference to FIG.

In this embodiment, the control signal input terminal 1
The test mode of the input level test and the normal operation mode are switched based on the logic level of the control signal input to 00.

First, in the normal operation mode, the control signal input terminal 100 is set to "H", and the input buffer circuit 2
00 P-channel MOS transistor 1, N-channel MOS transistor 4, first output buffer circuit 202
P channel MOS transistor 6 and the N channel MOS transistor 11 of the second output buffer circuit 203.
Are rendered non-conductive, and the tri-state inverter 8 of the first output buffer circuit 202 and the tri-state inverter 9 of the second output buffer circuit 203 are
The signal that operates as an inverter and is input to the pad 14 is transmitted only to the internal circuit 19 via the output terminal 303 of the input buffer circuit 200.

The output signal from the internal circuit 19 is output to the pads 16 and 17 via the input terminal 402 of the first output buffer circuit 202 and the input terminal 502 of the second output buffer circuit 203.

Next, the operation during the input level test will be described.

When testing a low level input voltage, the control signal input terminal 100 is set to "L".

Then, P of the first output buffer circuit 202
The channel MOS transistor 6, the N-channel MOS transistor 11 of the second output buffer circuit 203, the P-channel MOS transistor 1 of the input buffer circuit 200, and the N-channel MOS transistor 4 are all in the conductive state, and the first output buffer The tri-state inverter circuit 8 of the circuit 202 and the second output buffer circuit 2
The outputs of the tri-state inverter circuit 9 of 03 are both in a high impedance state.

In this state, the low level standard voltage is applied to all the input terminals 14 and 15.

When the input buffer circuit is normally manufactured, the output of the buffer 5 of the input buffer circuit 200 outputs "L" level, the N-channel MOS transistor 3 becomes non-conductive, and the P-channel MOS transistor 2 becomes It becomes conductive.

The input of the output inverter 7 of the first output buffer circuit 202 becomes "H" level and outputs "L" because the P-channel MOS transistor 6 is conductive.

A voltage determined by the resistance ratio (ratio of ON resistances) of the P-channel MOS transistors 1 and 2 and the N-channel MOS transistor 11 is applied to the input of the output inverter 10 of the second output buffer circuit 203. It

Here, if the voltage at the time of conduction is set in advance to a voltage higher than the logic threshold level of the output inverter 10, the output inverter 10 becomes
Output "L" level.

When a level abnormality occurs in at least one of the plurality of input buffer circuits, for example, assuming that the buffer 5 of the input buffer circuit 200 is abnormal (defective), a low level is applied to the terminal 14. The output of the buffer 5 outputs "H" when the N channel M
The OS transistor 3 becomes conductive.

Then, P of the first output buffer circuit 202
A current flows from the channel MOS transistor 6 to the N-channel MOS transistors 3 and 4, and the resistance ratio of the N-channel MOS transistors 3 and 4 and the P-channel MOS transistor 6 of the first output buffer circuit 202 to the input of the output inverter 7 ( A voltage determined by the on-resistance ratio) is applied.

In advance, the N-channel MOS transistor 3,
4 and the P channel MO of the first output buffer circuit 202.
If the transistor ratio of the S-transistor 6 is set to a voltage lower than the logic threshold level of the output inverter 7, the output inverter 7 outputs "H" even if there is any abnormality in the input level.

Regarding the second output buffer circuit 203, the P-channel MOS transistor 2 of the defective input buffer circuit 200 becomes non-conductive, but at the time of low level input, the non-defective input buffer circuit 201 is present.
Since the P-channel MOS transistor 2 of 1 is turned on, the output inverter 10 outputs "L" as in the case where there is no failure.

Next, when testing a high level input voltage, the control signal input terminal 100 is set to "L" in the same manner as the low level test described above, and the input terminals 14 and 15 are there.
A voltage corresponding to the high level standard voltage is applied to all.

When the input buffer circuit is normally manufactured, the input buffer 5 of the input buffer circuit 200 is
The "H" level is output, the P-channel MOS transistor 2 is non-conductive, and the N-channel MOS transistor 3 is conductive, so that the second output buffer circuit 203 is provided.
The input of the output inverter 10 becomes "L" because the N-channel MOS transistor 11 is conductive, and the output of the output inverter 10 becomes "H".

A voltage determined by the resistance ratio of the N channel MOS transistors 3 and 4 and the P channel MOS transistor 6 is applied to the input of the output inverter 7 of the first output buffer circuit 202.

In advance, the voltage at the time of conduction is output to the output inverter 7
The output inverter 7 of the first output buffer circuit 202 outputs "H" because the voltage is set to be lower than the logic threshold level.

If an abnormality occurs in the input buffer of the input buffer circuit 200, for example, the input buffer circuit 2
Assuming that the buffer 5 of 00 has an abnormality, the output of the buffer 5 outputs "L", and the N-channel MOS transistor 2 becomes conductive.

Then, current flows from the P channel MOS transistors 1 and 2 of the input buffer circuit 200 to the N channel MOS transistor 11 of the second output buffer circuit 203, and the input of the output inverter 10 of the second output buffer circuit 203 is input. At the end, the second output buffer circuit 203
A voltage determined by the resistance ratio of the N channel MOS transistor 11 and the P channel MOS transistors 1 and 2 of the input buffer circuit 200 is applied.

The N-channel MOS transistor 11 of the second output buffer circuit 203 and the input buffer circuit 20 are preset.
The P-channel MOS transistors 1 and 2 of 0 are set to have a voltage higher than the logic threshold level of the output inverter 10 when the transistor ratio of the P-channel MOS transistors 1 and 2 is turned on. The output of the output buffer 10 becomes "L".

Regarding the first output buffer circuit 202, the N-channel MOS transistor 3 of the input buffer circuit 200 which has a failure is rendered non-conductive, but the N-channel MOS transistor 3 of the input buffer which has not failed is conductive. The first output buffer circuit 2
The input of the No. 02 output inverter 7 is set to a level determined by resistance division, and the output of the output inverter 7 becomes "H" as in the case of no failure.

In this embodiment, the input level can be stably measured without operating the internal circuit 19, and all the input pins can be measured.

[0059]

Second Embodiment Next, a second embodiment of the present invention will be described. FIG. 2 is a diagram showing the circuit configuration of the second embodiment of the present invention.

This embodiment is the same as the first embodiment.
The buffer 5 in the input buffer circuit 200 is provided to the inverter 23, and the first and second output buffer circuits 202 and 20 are provided.
3 to the tri-state buffers 25 and 27, and the output inverters 7 and 10.
Are replaced with buffers 24 and 26.

Regarding the operation of this embodiment, the tri-state buffer 25 of each output buffer circuit 202, 203,
When the control signal input terminal 100 is "L" (in the test mode), its output is in a high impedance state, and when the control signal input terminal 100 is "H", it operates as a normal buffer. The normal operation of this embodiment is the same as that of the first embodiment.

In this embodiment, when a low level input voltage is tested, the control signal input terminal 100 is set to "L" and a plurality of input terminals 14 and 15 are used as in the first embodiment.
Apply low level standard voltage to all.

When the input buffer circuit is normally manufactured, the inverter 23 of the input buffer circuit 200 is "H".
Is output, the N-channel MOS transistor 3 is rendered conductive, the P-channel MOS transistor 2 is rendered non-conductive, and the buffer 26 of the second output buffer circuit 203 is output.
Is output as “L”, and the output buffer 24 of the first output buffer circuit 202 outputs “L”. In addition,
A voltage determined by the resistance ratio (ratio of ON resistances) of the N-channel MOS transistors 3 and 4 and the P-channel MOS transistor 6 is applied to the input of the output buffer 24 of the first output buffer circuit 202. Since the voltage when conducting is set to the “L” level in advance, the output buffer 2 of the first output buffer circuit 202 is
4 outputs "L".

Here, if a level abnormality occurs in at least one of the plurality of input buffer circuit inverters, assuming that the inverter 23 of the input buffer circuit 200 is abnormal, the input buffer circuit 200 The inverter 23 outputs “L”, the P-channel MOS transistor 2 is rendered conductive, the buffer 26 of the second output buffer circuit 203 outputs “H”, and, for example, N of the normal input buffer circuit 201 is output. Since the channel MOS transistor 3 is turned on, the buffer 24 of the first output buffer circuit 202 outputs "L" as in the normal state. Note that the input of the output buffer 26 of the second output buffer circuit 203 is the N channel M
A voltage determined by the resistance ratio (ratio of ON resistances) between the OS transistor 11 and the P-channel MOS transistors 1 and 2 is applied, and these transistors are set in advance so that the voltage at the time of conduction becomes the “H” level. Therefore, the output buffer 26 of the second output buffer circuit 203 outputs “H”.

When testing a high level input voltage,
Similar to the first embodiment, the control signal input terminal 100 is set to "L" and the high level standard voltage is applied to all the input terminals 14 and 15.

When the input buffer circuit is normally manufactured, the inverter 23 of the input buffer circuit 200 has the "L" level.
Is output, the N-channel MOS transistor 3 is turned off, and the P-channel MOS transistor 6 is turned on in the first output buffer circuit 202, so the buffer 24 outputs “H” and the second output. The buffer 26 of the buffer circuit 203 outputs "H".

Here, if the level is abnormal in any one of the input inverters of the plurality of input buffer circuits, for example, if the inverter 23 of the input buffer circuit 200 is abnormal, the high level standard voltage input is performed. At some time, the inverter 23 of the input buffer circuit 200 outputs “H”, the output of the buffer 26 of the second output buffer circuit 203 is “L”, and the output of the buffer 24 of the first output buffer circuit 202 is output. Outputs "H" as in the normal state.

[0067]

As described above, according to the present invention (Claim 1), during the input level test, the logic signal corresponding to the signal level of the input buffer is output to the output buffer, and the output result of the internal circuit is output. The input level can be tested regardless of this, so that the effects of noise, etc. due to the internal circuit operation are avoided, the variation of the input level is suppressed and stabilized, and the internal circuit of the semiconductor integrated circuit is enlarged. It is possible to suppress an increase in the length of the test vector even when the progress of the test. That is, according to the present invention, it is possible to measure all the input pins without requiring huge test vectors.

Further, according to the present invention (claim 1), when a level defect occurs in any of the plurality of input buffer circuits, the logic level corresponding to the level defect is output from the output buffer. , The efficiency of defect detection in the input level test is improved, and the test cost is reduced.

A preferred embodiment of the present invention (claim 2)
According to 5), according to the input buffer circuit and the output buffer circuit, it is possible to stabilize the input level measurement by adding simple and few circuit configurations and terminals, and to increase the scale of the circuit. This has the effect that all input pins can be measured without the need for different test vectors.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a conventional input level test circuit.

[Explanation of symbols]

 1, 2, 6 P-channel MOS transistor 3, 4, 11 N-channel MOS transistor 5 Input buffer (buffer circuit) 7, 10 Output inverter 8, 9 Tri-state inverter circuit 12, 13 Inverter 14, 15 Pad (input terminal) 16 , 17, 20, 22 Pads (output terminals) 18, 21, 24, 26 Output buffer 19 Internal circuit 23 Input inverter 25, 27 Tri-state buffer circuit 31-33 Input terminal 34 Output terminal 35-37 Input buffer 38 Output buffer 39 Internal circuit 100 Control signal input terminal 200 Input buffer circuit 202, 203 Output buffer circuit 300, 400, 500 Control signal input terminal 301, 302, 303 Output terminal 401, 402, 501, 502 Input terminal 600 Power supply

 ─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-2-77667 (JP, A) JP-A-61-38576 (JP, A) JP-A-6-11547 (JP, A) JP-A-8- 43492 (JP, A) JP 5-256910 (JP, A) JP 5-243361 (JP, A) JP 4-95885 (JP, A) JP 3-144385 (JP, A) JP-A-5-26981 (JP, A)

Claims (5)

(57) [Claims] 1. An input buffer circuit and two first and second
Half including at least an output buffer circuit and an internal circuit
A conductor device, wherein the input buffer circuit has an input buffer for inputting an input signal from an input terminal, and a first terminal in which a gate terminal is connected to an output of the input buffer.
P-channel MOS transistor and first N-channel
MOS transistor, first power supply terminal, and first P-channel MOS transistor
A second P-channel MOS transistor connected between
And registers, the first N-channel MOS transistor and a second power supply
A second N-channel MOS transistor connected between
Includes a register, a gate terminal of said second P-channel MOS transistor
Includes a test mode to test the input level and a normal operation mode.
A control signal for controlling the gate voltage of the second N-channel MOS transistor is input.
A signal obtained by inverting the control signal is input to the drain terminal of the first P-channel MOS transistor.
A second end connected to a first output terminal, and a drain end of the first N-channel MOS transistor
A child is connected to the second output terminal and the output of the input buffer is from the third output terminal to the internal
Circuit, and wherein the first output terminal of the input buffer circuit is
First output buffer circuit is connected to a first input terminal, and the second output terminal of the input buffer circuit is connected to the first input terminal .
2 is connected to the first input terminal of the output buffer circuit.
Ri, the first output buffer circuit receives the first output inverter, a signal obtained by inverting the control signal to the gate terminal, de
The rain terminal is connected to the input end and the front of the first output inverter.
Connected to the first input terminal of the first output buffer circuit
The third terminal having the source terminal connected to the second power terminal.
Includes a N-channel MOS transistor, wherein the first output buffer an output signal from said internal circuit
Input to the second input terminal of the circuit, the control signal
In the working mode, the signal input to the second input terminal
The inverted signal through the first output inverter
Output to the output terminal of the first output buffer circuit and test
In the mode, the signal input to the second input terminal is
Serial not propagate to the first output inverter, the second output buffer circuit includes a second output inverter, the control signal is input to the gate terminal, the drain terminal
The input terminal of the second output inverter and the second output
The source terminal is connected to the first input terminal of the buffer circuit.
A third P-channel M having a child connected to the first power supply terminal
Includes a OS transistor, the said second output buffer an output signal from said internal circuit
Input to the second input terminal of the circuit, the control signal
In the working mode, the signal input to the second input terminal
The inverted signal through the second output inverter
Output to the output terminal of the second output buffer circuit and test
In the mode, the signal input to the second input terminal is
A built-in input level test circuit configured so that it does not propagate to the input terminal of the second output inverter.
Semiconductor device. 2. The first output buffer circuit comprises a first transistor.
In addition to the line-state inverter circuit and the inverter,
Wherein the first tri-state inverter circuit, a control
The control signal is input to the terminal, and the input end of the control signal is the first
Connected to the second input terminal of the output buffer circuit of
The output terminal is connected to the input terminal of the first output inverter.
The inverter receives the control signal as an input, and the control signal
The inverted output of the third N-channel MOS transistor
The second output buffer circuit is connected to the gate terminal of
An inverter circuit is further provided, and the second tri-state inverter circuit controls the second tri-state inverter circuit.
The control signal is input to the terminal, and the input end thereof is the second
Connected to the second input terminal of the output buffer circuit of
Its output is connected to the input of the second output buffer.
The input level test according to claim 1, wherein
A semiconductor device with a built-in test circuit. 3. An input buffer circuit and two first and second
Half including at least an output buffer circuit and an internal circuit
A conductor device, wherein the input buffer circuit is an inverting input buffer for inputting an input signal from an input terminal.
And a gate terminal is connected to the output of the inverting input buffer
First P-channel MOS transistor and first N-channel transistor
And channel MOS transistors, said first power supply terminal first P-channel MOS transients
A second P-channel MOS transistor connected between
And registers, the first N-channel MOS transistor and a second power supply
A second N-channel MOS transistor connected between
Includes a register, a gate terminal of said second P-channel MOS transistor
Includes a test mode to test the input level and a normal operation mode.
A control signal for controlling the gate voltage of the second N-channel MOS transistor is input.
A signal obtained by inverting the control signal is input to the drain terminal of the first P-channel MOS transistor.
A second end connected to a first output terminal, and a drain end of the first N-channel MOS transistor
A child is connected to the second output terminal and the output of the input buffer is from the third output terminal to the internal
Circuit, and wherein the first output terminal of the input buffer circuit is
First output buffer circuit is connected to a first input terminal, and the second output terminal of the input buffer circuit is connected to the first input terminal .
2 is connected to the first input terminal of the output buffer circuit.
Ri, the first output buffer circuit receives the first output buffer, a signal obtained by inverting the control signal to the gate terminal, de
The rain terminal is connected to the input end of the first output buffer and the
Connected to the first input terminal of the first output buffer circuit
The third terminal having the source terminal connected to the second power terminal.
Includes a N-channel MOS transistor, wherein the first output buffer an output signal from said internal circuit
Input to the second input terminal of the circuit, the control signal
In the working mode, the signal input to the second input terminal
Through the output buffer to the first output buffer times
Output to the output terminal of the path, and in the test mode, the second
The signal input to the input terminal is sent to the first output buffer.
Does not propagate, and the second output buffer circuit receives the second output buffer and the gate terminal to which the control signal is input, and the drain terminal
The input end of the output buffer and the second output buffer
Connect to the first input terminal of the circuit and connect the source terminal to the
A third P-channel MOS transistor connected to the first power supply terminal
Includes a Njisuta, wherein the output signal from the internal circuit second output buffer
Input to the second input terminal of the circuit, the control signal
In the working mode, the signal input to the second input terminal
To the output terminal via the second output buffer,
In the test mode, the signal input to the second input terminal is
Signal is not propagated to the input end of the second output buffer , and an input level test circuit is built in.
Semiconductor device. 4. The first output buffer circuit comprises a first transistor.
In addition Bei and the tristate buffer circuit, and the inverter, the
For example, the first tri-state buffer circuit, a control terminal
The control signal is input to the child, the input end of which is the first
Connected to the second input terminal of the output buffer circuit,
A power terminal is connected to an input terminal of the first output buffer, the inverter receives the control signal,
The inverted output of the third N-channel MOS transistor
The second output buffer circuit is connected to the gate terminal of
A buffer circuit, wherein the second tri-state buffer circuit has a control terminal
The control signal is input to the child, the input end of which is the second
Connected to the second input terminal of the output buffer circuit,
Has its output connected to the input of the second output buffer.
Input level test according to claim 3, characterized in that Te
A semiconductor device with a built-in circuit. 5. The first power supply terminal has a power supply voltage (VDD).
Terminal, and the second power supply terminal is a ground terminal.
5. The method according to any one of claims 1 to 4, characterized in that
A semiconductor device with a built-in input level test circuit.