JPH0568103B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that can shorten the time required for checking DC characteristics.

[Prior Art] The direct current characteristics of a semiconductor integrated circuit are checked by directly measuring the voltages at input/output terminals and the currents passing through them. When checking the direct current characteristics of a conventional semiconductor integrated circuit, a test pattern for function check is used to measure the voltage or current at a predetermined input/output terminal. for example,
When checking the input voltage margin, input a test pattern for function check to the input terminal. In this case, the voltage input during normal operation as the input voltage of the test pattern (for example,
Apply a voltage (for example, 2V for low level and 3V for high level) that takes into consideration the case where noise is mixed in (low level is 0V, high level is 5V). Elements that are directly related to the input terminal should be guaranteed to operate correctly when such a voltage is applied, and therefore, when this voltage is applied to the input terminal, the output terminal The quality of the input voltage margin of this element is checked based on whether a predetermined output is obtained from the element.

When checking the output current characteristics, a test pattern is applied to the input terminal, and when the terminal to be measured reaches a predetermined level based on the test pattern, the output current of that terminal is measured.

[Problems to be Solved by the Invention] However, in conventional semiconductor integrated circuits, when checking DC characteristics, a test pattern input from an input terminal is output from an output terminal via an internal circuit. However, it is not possible to estimate an abnormality in the internal circuit by checking such DC characteristics, and only the quality of elements directly related to the input/output terminals can be determined based on the DC characteristics. Although it is not possible to detect abnormalities in the internal circuit, due to the presence of the internal circuit, when checking the DC characteristics,
Setting input conditions to obtain a predetermined output becomes complicated.

For example, when checking the input voltage margin, a test pattern is applied to the input terminal and the input voltage is measured when a specified output is made from the output terminal, but even if the input signal changes, the internal circuit logic In some cases, the output may not change. Therefore, in order to obtain a predetermined output, it is necessary to use a considerable number of test patterns.

Further, as a matter of course, the test pattern is not set so that the signal level changes at all input terminals at an early stage after the start of the test. Therefore, it is necessary to use all test patterns in the input voltage margin check. Since tens of thousands of test patterns are normally used, the test takes a long time.

Also, in checking the output current characteristics, a test pattern is run until the output terminal to be measured reaches a predetermined output level. Therefore, depending on the function of the semiconductor integrated circuit, if the logic depth is deep, it is necessary to use a considerable number of patterns for each output terminal. Furthermore, the output voltage of the semiconductor integrated circuit is not stable at the moment the output pattern changes, so it is not possible to check the output current characteristics based on the current value immediately after the change. Therefore, the current is measured after waiting for several tens of milliseconds until the state stabilizes. If multiple output terminals cannot be measured using the same test pattern, the test time is the test pattern running time and measurement waiting time (several tens of milliseconds) required for each output terminal multiplied by the number of output terminals. becomes. Since a semiconductor integrated circuit normally has several hundred output terminals, the test time thereof is long.

As described above, conventional semiconductor integrated circuits have the problem that checking their DC characteristics requires a long time.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a semiconductor integrated circuit whose DC characteristics can be measured in a short time.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention includes a plurality of input terminals, an output terminal, an internal circuit constituted by a logic circuit, and a circuit between the plurality of input terminals and the internal circuit. a plurality of input buffers each connected in series;
A semiconductor integrated circuit having a plurality of output buffers connected in series between the plurality of output terminals and an internal circuit, respectively, a test terminal, and when a test signal is input to the test terminal, the input buffer a first switching means for electrically connecting the output end of the output buffer and the input end of the output buffer; and a switch between the output end of the input buffer and the internal circuit when a test signal is input to the test terminal; The apparatus is characterized by comprising a second switching means for electrically disconnecting between the internal circuit and the input end of the output buffer.

[Function] In the present invention, when a high-level signal is input to the test terminal, for example, the first switching means electrically connects the output end of the input buffer and the output end of the output buffer. The second switching means electrically disconnects between the output end of the input buffer and the internal circuit, and between the internal circuit and the input end of the output buffer. As a result, changes in the input signal are not affected by the internal circuit and are output to the output terminal via the input buffer and output buffer, so that when checking the DC characteristics of a semiconductor integrated circuit, the output terminal can obtain a predetermined output. This can be done by changing the input pattern applied to the input terminal several times.

[Embodiments] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a circuit diagram showing a semiconductor integrated circuit according to a first embodiment of the present invention. An input buffer 1 is provided between the input terminal 1 and the internal circuit 25.
and 77 transmission gates (hereinafter referred to as TG) 7 are connected in series. A TG 12 and an output buffer 19 are connected in series between the internal circuit 25 and the output terminal 3. Input buffer 17
TG8 and TG11 are connected in series between the connection point between TG12 and TG7 and the connection point between TG12 and output buffer 19.

TG7, 8, 11, and 12 are all composed of parallel connections of PMOS transistors and NMOS transistors, and the gates of the PMOS transistors of TG7 and 12 and the gates of the NMOS transistors of TG8 and 11 are connected to the input from the test terminal 5. The signal T output via the input buffers 21 and 22 is input. On the other hand, TG7 and 12
A signal inputted from the test terminal 5 and inverted by the input buffer 21 is inputted to the gates of the NMOS transistor and the PMOS transistors of TG8 and TG12. The TGs 7 and 12 are conductive when the signal T is at a low level (hereinafter referred to as "L"), and cut off when the signal T is at a high level (hereinafter referred to as "H"). Conversely, for TG8 and 11, the signal T is “H”
It is conductive when it is "L", and it is cut off when it is "L". These TG7 and 8 constitute a selector circuit 26, and TG11 and 12 constitute a selector circuit 28.
is configured.

Next, the operation of the semiconductor integrated circuit configured as described above will be explained. Now, when an "L" signal is applied to the test terminal 5, TG7 and TG12 become conductive, and TG8 and TG11 become non-conductive.
Therefore, the signal applied to input terminal 1 is input to internal circuit 25 via input buffer 17 and TG7, and the output of internal circuit 25 is output to output terminal 3 via TG12 and output buffer 19.
Since this is the same as the normal operation, by inputting the test pattern to the input terminal 1, a function test, a DC characteristic check, etc. can be performed.

Next, when test terminal 5 is set to “H”, TG
8 and 11 are conductive, and TG7 and 12 are disconnected. Therefore, the signal input to the input terminal 1 is output to the output terminal 3 via the input buffer 17, TG8, TG11 and the output buffer 19. Therefore, even in this case, since the input signal passes through the input buffer 17 and the output buffer 19, it is possible to check the DC characteristics to check the input/output status. For example, the input voltage margin of the input buffer 17 can be checked by checking the voltage at the input terminal 1 that takes into account noise (for example, when "L" is
If 0V and “H” are 5V, for example, “L” is 2V.
A voltage such as 3 V is applied thereto, and the determination can be made based on whether or not a predetermined output voltage is obtained from the output terminal 3. In this embodiment, the input signal is output to the output terminal 3 without passing through the internal circuit, so when the input signal changes from "L" to "H", the output signal changes from "L" to "L". , "H" also changes.
Therefore, by changing the voltage applied to the input terminal 1 in several patterns, for example from 2V to 3V to 2V, the output terminal 3 will change accordingly, for example from 0V.
Check the input voltage margin depending on whether it changes from →5V →0V. In this way, the input voltage margin can be checked by changing the input voltage in several patterns, making it possible to significantly shorten the test time.

Similarly, when checking the output current characteristics and output voltage characteristics of the output buffer 19, the output signal changes in response to changes in the input signal, so if the signal to the input terminal 1 is changed in several patterns, the output Current characteristics and output voltage characteristics can be checked. Therefore, the output current characteristics and output voltage characteristics can be checked in a short time.

FIG. 2 is a circuit diagram showing a semiconductor integrated circuit according to a second embodiment of the present invention. In Figure 2, the first
Components that are the same as those in the drawings are designated by the same reference numerals and descriptions thereof will be omitted. This embodiment is an example in which the number of input terminals is greater than the number of output terminals. Input buffer 17 and TG7 are connected in series between input terminal 1 and internal circuit 25, and input buffer 18 and TG9 are connected in series between input terminal 2 and internal circuit 25. . Further, a TG 12 and an output buffer 19 are connected in series between the internal circuit 25 and the output terminal 3. TG8, 15, and 11 are connected in series between the connection point between input buffer 17 and TG7 and the connection point between TG12 and output buffer 19, and the connection point between input buffer 18 and TG9,
TGs 10, 16, and 11 are connected in series between the connection point between TG 12 and output buffer 19. TG7 to 12 and TG15, 16 are PMOS
Consists of parallel connections of transistors and NMOS transistors, PMOS of TG7, 9, 12
The signal T input to the test terminal 5 is input to the gates of the transistors via input buffers 21 and 22, and the signal T input to the test terminal 5 is input to the gates of the NMOS transistors of TG7, 9, and 12. The signal is inverted by the input buffer 21 and inputted as a signal. Also, TG8, 10, 11
The signal T input to the test terminal 5 is applied to the gate of the NMOS transistor through input buffers 21 and 22.
Input via PMOS of TG8, 10, 11
A signal T input from the test terminal 5 and inverted by the input buffer 21 is input to the gate of the transistor. After being input to the test terminal 6, the signal T ₁ is passed through the input buffers 23 and 24.
is the gate of PMOS transistor of TG15 and
Signal ₁ is input to the gate of the NMOS transistor of TG16 and is inverted by the input buffer 23 after being input to the test terminal 6.
Gate of NMOS transistor and TG16
Input to the gate of PMOS transistor.

When test terminal 5 is “L”, TG7,
9 and 12 are conductive, and TG8, 10, and 11 are disconnected. When test terminal 5 is “H”,
TG8, 10, 11 are conductive, TG7, 9, 12
breaks continuity. When the test terminal 6 is "L", TG15 is conductive and TG16 is disconnected. When test terminal 6 is “H”, TG1
6 is conductive, and TG15 is conductive. TG7,
8, TG9, 10, TG11, 12 and TG15,
16 respectively selector circuits 26, 27, 28,
30 are configured.

Now, if test terminal 5 is “L”, TG
7, 9, and 12 become conductive, so input terminal 1
The input signal input to the input buffer 17 and
The input signal input to input terminal 2 via TG7 is input to internal circuit 25 via input buffer 18 and TG9, respectively. The output of the internal circuit 25 is then output to the output terminal 3 via the TG 12 and the output buffer 19. This is the same signal flow as during normal operation.

Next, when the test terminal 5 is set to "H", the input signals of the input terminals 1 and 2 are both input to the selector circuit 30 by the selector circuits 26 and 27. The main power of the selector circuit 30 is outputted to the output terminal 3 via the TG 11 and the output buffer 19. Therefore, when the test terminal 6 is "L", the input signal of the input terminal 1 is outputted to the output terminal 3, and when the test terminal 6 is "H", the input signal of the input terminal 2 is outputted.

In this way, also in this embodiment, when the test terminal 5 is set to "H", the input signals at the input terminals 1 and 2 are transferred to the input buffer 1 without passing through the internal circuit.
7 and 18 and the output buffer 19, and is output to the output terminal 3. As in the first embodiment, the DC characteristics can be checked by changing several patterns of input to the input terminal. This can significantly reduce testing time.

FIG. 3 is a circuit diagram showing a semiconductor integrated circuit according to a third embodiment of the present invention. In Figure 3, the first
Components that are the same as those in the drawings are designated by the same reference numerals and descriptions thereof will be omitted. The circuit shown in FIG. 3 is an example where the number of output terminals is greater than the number of input terminals, and in contrast to the circuit shown in FIG.
3 and 14 are added. In other words, internal circuit 2
A TG 14 and an output buffer 20 are connected in series between TG 5 and the output terminal 4, and a TG 13 is connected between a connection point between TG 14 and output buffer 20 and a connection point between TG 8 and TG 11. T.G.
13 and 14 are both PMOS transistors and
It is composed of a parallel connection of NMOS transistors, and when the test terminal 5 is "L",
TG14 is conductive and TG13 is conductive.
When the test terminal 5 is "H", TG13 is conductive and TG14 is disconnected. TG13,1
4 constitutes a selector circuit 29.

Also in this embodiment, when the test terminal 5 is "L", the operation is the same as in normal operation, and when the test terminal 5 is "H", the input signal is transferred to the internal circuit 2.
5, but through the input buffer 17, selector circuits 26, 28, and output buffer 19,
In addition, input buffer 17, selector circuits 26, 2
9 and output buffer 20 to output terminals 3 and 4, respectively. Therefore, in this embodiment as well, it is possible to check the DC characteristics by changing the input signal in several patterns.

[Effects of the Invention] As explained above, according to the present invention, when a test signal is input to the test terminal, the output end of the input buffer and the input end of the output buffer are electrically connected by the first switching means. At the same time, the second switching means electrically disconnects between the output end of the input buffer and the internal circuit and between the internal circuit and the input end of the output buffer, so that the direct current of the semiconductor integrated circuit is Characteristics can be checked in a short time. Particularly, this method has a great effect on reducing test time for semiconductor integrated circuits having packages with several hundred pins and tens of thousands of test patterns.

[Brief explanation of the drawing]

1 to 3 are circuit diagrams showing semiconductor integrated circuits according to first to third embodiments of the present invention. 1, 2; input terminal, 3, 4; output terminal, 5,
6; Test terminal, 7-16; Transmission gate (TG), 17, 18, 21-24; Input buffer, 19, 20; Output buffer, 25; Internal circuit, 26-30; Selector circuit.

Claims (1)

[Scope of Claims] 1. A plurality of input terminals and an output terminal, an internal circuit constituted by a logic circuit, and a plurality of input buffers connected in series between the plurality of input terminals and the internal circuit, respectively; A semiconductor integrated circuit having a plurality of output buffers connected in series between the plurality of output terminals and an internal circuit, respectively, a test terminal, and when a test signal is input to the test terminal, the input buffer a first switching means for electrically connecting the output end of the output buffer and the input end of the output buffer; and a switch between the output end of the input buffer and the internal circuit when a test signal is input to the test terminal; A semiconductor integrated circuit comprising: second switching means for electrically disconnecting between the internal circuit and the input end of the output buffer.