JPH04172273A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH04172273A JPH04172273A JP2298692A JP29869290A JPH04172273A JP H04172273 A JPH04172273 A JP H04172273A JP 2298692 A JP2298692 A JP 2298692A JP 29869290 A JP29869290 A JP 29869290A JP H04172273 A JPH04172273 A JP H04172273A
- Authority
- JP
- Japan
- Prior art keywords
- output
- logical
- logical level
- terminals
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000001514 detection method Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
Abstract
PURPOSE: To facilitate a manufacturing test on a user's side by controlling an output logical level on the basis of an input logical level output detection circuit outputting a predetermined logical level when all of the control signals supplied from the outside and an input terminal are set to the same logical level.
CONSTITUTION: When a control signal input terminal 7 is set to 'L', the outputs of all of logical output cut-off gates 91 of an output logical level control circuit 9 become an 'L' level regardless of the output of an internal logical circuit part 6. Therefore, the output logical levels of the terminals θ1 - θn-1 among output terminals 3 can be controlled on the basis of the logical level given to a control signal input terminal 8. When the same logical level is applied to all input terminals 2, the output of an input logical level output detection circuit 10 also becomes the same logical level. By this constitution, the output logical levels of several output terminals θ1 - θn-1 can be controlled by the terminals 7, 8 and function detecting the same logical levels of several input terminals to apply a predetermined logical level to the other output terminal θn is provided and a manufacturing test becomes easy.
COPYRIGHT: (C)1992,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2298692A JPH04172273A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2298692A JPH04172273A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04172273A true JPH04172273A (en) | 1992-06-19 |
Family
ID=17863050
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2298692A Pending JPH04172273A (en) | 1990-11-02 | 1990-11-02 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04172273A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07182201A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Information processor |
JP2009092529A (en) * | 2007-10-10 | 2009-04-30 | Elpida Memory Inc | Semiconductor circuit and inspection method of the same |
-
1990
- 1990-11-02 JP JP2298692A patent/JPH04172273A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07182201A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Information processor |
JP2009092529A (en) * | 2007-10-10 | 2009-04-30 | Elpida Memory Inc | Semiconductor circuit and inspection method of the same |
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