US5225774A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- US5225774A US5225774A US07/731,754 US73175491A US5225774A US 5225774 A US5225774 A US 5225774A US 73175491 A US73175491 A US 73175491A US 5225774 A US5225774 A US 5225774A
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- US
- United States
- Prior art keywords
- input
- output
- circuit
- buffer circuit
- terminals
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31712—Input or output aspects
- G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
Definitions
- This invention relates to a semiconductor integrated circuit having a plurality of functional devices, and more particularly to, a semiconductor integrated circuit having an input buffer and an output buffer in which operation characteristics are tested easily in a short time.
- a conventional semiconductor integrated circuit includes a plurality of functional devices formed on a chip, an input buffer circuit including a plurality of inverters connected between input terminals and the functional devices, and an output buffer circuit including a plurality of inverters connected between output terminals and the functional devices.
- This IC pattern test is carried out separately for each one of functional devices provided in the semiconductor integrated circuit, because the functional devices are connected through input and output buffers to corresponding ones of the input and output terminals. In this IC pattern test, interconnections of the functional devices are also checked in the same manner as described above.
- a predetermined pattern of voltage signals consisting of, for instance, V DD ⁇ 0.7(V IH ) and V DD ⁇ 0.3 (V IL ) is applied to the input terminals as high and low signals.
- V DD voltage DD ⁇ 0.7(V IH )
- V DD voltage DD ⁇ 0.3
- V IL voltage IL
- V DD ⁇ 0.7 (V OH ) and V DD ⁇ 0.3 (V OL ) are used as reference voltage for high and low levels, and output voltages are detected by measuring voltage up (increase) and decrease (drop) between a tester and each output terminal, to which the tester is connected to draw current therefrom and to supply current thereto dependent on levels of the output terminals.
- an output characteristic of the output buffer is examined.
- an input and output characteristic of the input and output buffers is examined by applying a predetermined pattern of voltage signals consisting of the V IH and V IL levels to the input terminals and detecting a pattern of voltage signal at the output terminals according to the reference voltages of the V OH and V OL levels.
- a semiconductor integrated circuit comprises:
- an input buffer circuit connected to input terminals to supply input signals therefrom to the functional devices
- FIG. 1 is a circuit diagram showing a conventional semiconductor integrated circuit
- FIG. 2 is a circuit diagram showing a semiconductor circuit of a first preferred embodiment to the invention
- FIG. 3 is a truth table showing test patterns used in the first preferred embodiment shown in FIG. 2;
- FIG. 4 is a circuit diagram showing a semiconductor integrated circuit of a second preferred embodiment according to the invention.
- FIG. 5 is a truth table showing test patterns used in the second preferred embodiment shown in FIG. 4;
- FIG. 6 is a circuit diagram showing a semiconductor circuit of a third preferred embodiment according to the invention.
- FIG. 7 is a truth table showing test patterns used in the third preferred embodiment shown in FIG. 6;
- the semiconductor integrated circuit 301 includes functional devices 302 and 303 having predetermined functions, respectively, a separation circuit 304 connected with the functional devices 302 and 303 by lines 341 and 342, respectively, an input buffer circuit 305 connected with input terminals 307 to 315, and an output buffer circuit 306 connected with output terminals 316 to 321.
- the functional devices 302 and 303 are connected by lines 337 to 340 each other, so that predetermined signals are transferred therebetween.
- the separation circuit 304 applies separation signals to the functional devices 302 and 303 to separate them in an IC pattern test, etc..
- the input buffer circuit 305 includes inverters 322 to 330, among which the inverters 322 to 324 are connected between the input terminals 307 to 309 and the functional device 302, the inverters 325 is connected between the input terminal 310 and a common node of the functional devices 302 and 303, the inverters 327 to 329 are connected between the input terminals 311 to 313 and the functional device 303, and the inverters 329 and 330 are connected between the input terminals 314 and 315 and the separation circuit 304, respectively.
- the output buffer circuit 306 includes inverters 331 to 336, among which the inverters 331 to 333 are connected between the functional device 302 and the output terminals 316 to 318 and the inverters 334 to 336 are connected between the functional device 303 and the output terminals 319 to 321.
- an IC pattern including the functional devices 302 and 303 is tested, test signals of low ("0") level are applied to the input terminal 314 and 315, so that signals of high (“1") level are applied to the separation circuit 304 by the inverters 329 and 330. Then, the separation signals are applied to the functional devices 302 and 303, so that the devices 302 and 303 are separated. After that, the IC pattern including the functional devices 302 and 303 is checked by applying predetermined patterns of voltage signals to the input terminals 307 to 310, and 310 to 313, and detecting patterns of voltage signals at the output terminals 316 to 318, and 319 to 321, as described above.
- test using applied voltage such as V IH /V IL and reference voltages such as V OH /V OL is carried out, as described before (not explained here).
- the inverters 322 to 328 of the input buffer circuit 305 and the inverters 331 to 336 of the output buffer circuit 306 are not connected with both of the functional devices 302 and 303 except for the inverter 325 of the input buffer circuit 305, so that the characteristic tests of the buffer circuits 305 and 306 are required to be carried out separately in respective functional devices 302 and 303. Therefore, the disadvantages occur as described before.
- FIG. 2 shows a semiconductor integrated circuit of a first preferred embodiment according to the invention.
- the semiconductor integrated circuit 101 includes functional devices 102 and 103, a separation circuit 105 connected with the functional devices 102 and 103 by lines 156 and 157, an input buffer circuit 106 connected with input terminals 108 to 116, an output buffer circuit 107 connected with output terminals 117 to 122, and a test circuit 104 connected between the input buffer circuit 106 and the output buffer circuit 107.
- the functional devices 102 and 103 are connected by lines 152 to 155, so that predetermined signals are transferred therebetween.
- the separation circuit 105 applies separation signals to the functional devices 102 and 103 to separate them in an IC pattern test, etc..
- the input buffer circuit 106 includes inverters 123 to 131, among which the inverters 123 to 125 are connected between the input terminals 108 to 110 and the functional device 102, the inverters 126 to 128 are connected between the input terminals 111 to 113 and the functional device 103, the inverters 129 and 130 are connected between the test signal input terminals 114 and 115 and the separation circuit 105 and inverter 131 is connected between the test signal input terminal 116 and the test circuit 104.
- the output buffer circuit 107 includes inverters 146 to 151 connected at outputs to the output terminals 117 to 122 and at inputs through transfer gates 139 to 144 to the functional devices 102 and 103, respectively.
- the ON/OFF of the transfer gates 139 to 144 are controlled by a signal supplied via an inverter 145 from the test circuit 104.
- the test circuit 104 includes an inverter 132 connected with the inverter 131 in the input buffer circuit 106 and clocked inverters 133 to 138 connected between the inverters 123 to 128 in the input buffer circuit 106 and the inverters 146 to 151 in the output buffer circuit 107, respectively.
- the ON/OFF of the clocked inverters 133 to 138 are controlled by the signal supplied from the inverter 132.
- signals of "1" or "0" level are applied to the input terminals 108 to 113 by the LSI tester in accordance with a test pattern shown in FIG. 3, wherein the levels “1” and “0” are set to be V DD and ground level for the first test, and V DD ⁇ 0.7 (V IH ) and V DD ⁇ 0.3 (V IL ) for the second test. Then, levels of the output voltage at the output terminals 117 to 122 are detected. If the voltage levels correspond to the reference pattern as shown in FIG. 3, the input buffer circuit 106 (inverters 123 to 128) is determined to stand the test.
- the buffer circuits 106 and 107 are separated from the functional devices 102 and 103, and the buffer circuits 106 and 107 are directly connected by the test circuit 104, when characteristics of the buffer circuits 106 and 107 are tested. Therefore, the number of test patterns are decreased, so that characteristics of the buffer circuits 106 and 107 are tested easily in a short time and exactly.
- FIG. 4 shows a semiconductor integrated circuit of a second preferred embodiment according to the invention.
- the semiconductor integrated circuit 201 fundamentally includes functional devices 202 and 203, a separation circuit 205 connected with the functional devices 202 and 203 by lines 277 and 278, an input/output buffer circuit 206 connected with input, input/output and test signal input terminals 208 to 217, an output buffer circuit 207 connected with output terminals 218 to 221, and a test circuit 204 connected between the input/output buffer circuit 206 and the output buffer circuit 207.
- the functional devices 202 and 203 are connected each other by lines 273 to 276.
- the separation circuit 205 applies separation signals to the functional devices 202 and 203 via the lines 277 and 278 to separate them in an IC pattern test, etc.
- the input/output buffer circuit 206 includes inverters 222 to 234, among which the inverters 222 to 224 are applied with input signals from the input terminals 208 to 210, wherein the inverters 222 and 223 apply signals to the test circuit 204 and the functional device 202 and the inverter 224 applies a signal to the test circuit 204 and the functional device 203.
- the inverters 225 to 230 are connected with input/output terminals 211 to 213, among which the inverters 225 to 227 applies signals to the test circuit 204 and the functional device 202, and the inverters 228 to 230 of clocked inverters receive signals therefrom.
- the ON/OFF of the clocked inverters 228 to 230 are controlled by signals from the test signal input terminals 214 and 215 (to be explained later).
- the inverter 228 is applied with signals from the test circuit 204 and the functional device 202 via a transfer gate 256, and supplies an output signal to the input/output terminal 211.
- the inverters 229 and 230 are applied with signals from the test circuit 204 and the functional device 203 via transfer gates 257 and 258, and supply output signals to the input/output terminals 212 and 213, respectively.
- the inverters 231 to 234 are connected with the test signal input terminals 214 to 217.
- An input signal transferred through the inverter 231 is applied via an inverter 235 to NOR gates 260 to 262 and an inverter 259.
- An input signal transferred through the inverter 232 is applied via an inverter 236 to NOR gates 263 to 265.
- Signals supplied from the NOR gate 260 to 262 are transferred to the clocked inverters 228 to 230 via NOR gates 263 to 265 and inverters 266 to 268 to control ON/OFF of the inverters 228 to 230, respectively.
- input and output states of the input/output terminals 211 to 213 are changed by the changing signals 282 to 284 (outputs of the inverters 266 to 268).
- a signal transferred through the inverter 259 is applied to transfer gates 252 to 255, and each signal through the transfer gates 252 to 255 is applied to the test circuit 204 via an inverter 251.
- Test signals transferred through the inverters 233 and 234 are applied to the separation circuit 205.
- the output buffer circuit 207 includes inverters 269 to 272, among which the inverters 269 to 272 are applied with signals from the test circuit 204 and the functional devices 202 and 203 via the transfer gates 252 to 255, respectively.
- the test circuit 204 includes clocked inverters 244 to 250 the ON/OFF of which is controlled by a signal from the inverter 251 and NAND gates 237 to 243, and applies signals to the output terminals 218 to 221 via the output buffer circuit 207 and to the input/output terminals 211 to 213 via the clocked inverters 228 to 230 of the input/output buffer circuit 206. It is notice that each of the NAND gates 237 to 243 has two input gates, and two signals from the input/output buffer circuit 206 are applied to the gates 237 to 243 connected by intersecting points shown as black point on input lines, respectively.
- output signals supplied from the functional devices 202 and 203 are transferred to the output terminals 218 to 221 and the input/output terminals 211 to 213 via the output buffer circuit 207 and the input/output buffer circuit 206, respectively.
- no signal is supplied from the test circuit 204.
- a signal of "1" level is applied to the test signal input terminal 214, so that a signal of "0" level is supplied from the inverter 231, a signal of "1” level is supplied from the inverter 235. Then, the inverter 259 applies a signal of "0" level to the transfer gates 252 to 255 in response to the signal from the inverter 235, so that the transfer gates 252 to 255 become OFF state. At the same time the clocked inverters 244 to 250 become ON state in response to the signal from the inverter 251.
- the input terminals 208 to 213 are connected with the output terminals 218 to 221 and 211 to 213 by a logic circuit consisting of the input/output buffer circuit 206, the test circuit 204 and the output buffer circuit 207. That is, output signals of the functional devices 202 and 203 are not transfered to the output buffer 207.
- input signals applied to the input terminals 208 to 210 and the input/output terminals 211 to 213 are transferred to the output terminals 218 to 221 and the input/output terminals 211 to 213 via the input/output buffer circuit 206, the test circuit 204 and the output buffer circuit 207.
- an input characteristic of the input/output buffer circuit 206 is tested in accordance with the level detection of the input terminals 208 to 210 and the input/output terminals 211 to 213.
- the consecutive test patterns are stopped at the test pattern No. 9 to provide the input/output terminals 211 to 213 and the output terminals 218 to 221 with output signals of "0", so that the V OL test thereof is carried out in accordance with current flowing thereinto from an LSI tester.
- the consecutive test patterns are stopped at the test pattern No. 16 to provide the input/output terminals 211 to 213 and the output terminals 218 to 221 with output signals of "1", so that the V OH test thereof is carried out in accordance with current flowing therefrom to the LSI tester.
- FIG. 6 shows a semiconductor integrated circuit of a third preferred embodiment according to the invention.
- the test circuit 204 includes transfer gates 285 to 290 and inverters 291 to 297 in place of the NAND gates 237 to 243.
- the ON/OFF of the transfer gates 285 to 287 and 288 to 290 are controlled by the change signals 282 to 284 and 282a to 284a, respectively.
- the transfer gates 285 to 287 are controlled by the input/output changing signals 282 to 284, while the transfer gates 288 to 290 are controlled by the input/output changing signals 282a to 284a. Accordingly, when the input/output terminals 211 to 213 are used as input terminals, the transfer gates 285 to 287 are OFF, while the transfer gates 288 to 290 are ON. On the other hand, when the input/output terminals 211 to 213 are used as output terminals, the transfer gates 285 to 287 are ON, while the transfer gates 288 to 290 are OFF.
- FIG. 7 shows a truth table of test patterns used in this embodiment.
- “ " indicates that the input/output terminals 211 to 213 are under an input state, and " " indicates that a signal of any level may be applied to the input terminals 208 to 210.
Abstract
Description
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2187755A JPH0474977A (en) | 1990-07-16 | 1990-07-16 | Semiconductor integrated circuit |
JP2-187755 | 1990-07-16 |
Publications (1)
Publication Number | Publication Date |
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US5225774A true US5225774A (en) | 1993-07-06 |
Family
ID=16211638
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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US07/731,754 Expired - Lifetime US5225774A (en) | 1990-07-16 | 1991-07-16 | Semiconductor integrated circuit |
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US (1) | US5225774A (en) |
JP (1) | JPH0474977A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815511A (en) * | 1995-10-13 | 1998-09-29 | Fujitsu Limited | Semiconductor integrated circuit equipped with test circuit |
US6477674B1 (en) * | 1999-12-29 | 2002-11-05 | Intel Corporation | Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements |
US20040049721A1 (en) * | 2002-09-09 | 2004-03-11 | Kevin Laake | Method and apparatus for improving testability of I/O driver/receivers |
US20040153795A1 (en) * | 2002-10-01 | 2004-08-05 | Toshio Teraishi | Analog voltage output driver LSI chip having test circuit |
US20040183563A1 (en) * | 2003-03-17 | 2004-09-23 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit including test pins and method for testing thereof |
US6873926B1 (en) * | 2001-02-27 | 2005-03-29 | Cisco Technology, Inc. | Methods and apparatus for testing a clock signal |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0725738U (en) * | 1993-10-22 | 1995-05-16 | 敏夫 阪中 | Tree pot |
US5715197A (en) | 1996-07-29 | 1998-02-03 | Xilinx, Inc. | Multiport RAM with programmable data port configuration |
EP1515345A1 (en) | 1999-02-02 | 2005-03-16 | Fujitsu Limited | Test method and test circuit for electronic device |
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US5012185A (en) * | 1988-10-14 | 1991-04-30 | Nec Corporation | Semiconductor integrated circuit having I/O terminals allowing independent connection test |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH01111365A (en) * | 1987-10-26 | 1989-04-28 | Nec Corp | Semiconductor integrated circuit |
JPH01228322A (en) * | 1988-03-09 | 1989-09-12 | Nec Corp | Gate array |
JP2595029B2 (en) * | 1988-03-30 | 1997-03-26 | 株式会社日立製作所 | LSI with diagnostic facilitation circuit |
-
1990
- 1990-07-16 JP JP2187755A patent/JPH0474977A/en active Pending
-
1991
- 1991-07-16 US US07/731,754 patent/US5225774A/en not_active Expired - Lifetime
Patent Citations (11)
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US4357703A (en) * | 1980-10-09 | 1982-11-02 | Control Data Corporation | Test system for LSI circuits resident on LSI chips |
US4527115A (en) * | 1982-12-22 | 1985-07-02 | Raytheon Company | Configurable logic gate array |
US4864165A (en) * | 1985-03-22 | 1989-09-05 | Advanced Micro Devices, Inc. | ECL programmable logic array with direct testing means for verification of programmed state |
US4698588A (en) * | 1985-10-23 | 1987-10-06 | Texas Instruments Incorporated | Transparent shift register latch for isolating peripheral ports during scan testing of a logic circuit |
US4931722A (en) * | 1985-11-07 | 1990-06-05 | Control Data Corporation | Flexible imbedded test system for VLSI circuits |
US4780666A (en) * | 1986-08-04 | 1988-10-25 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor integrated circuit device having rest function |
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US4870345A (en) * | 1986-08-04 | 1989-09-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor intergrated circuit device |
US4782283A (en) * | 1986-08-22 | 1988-11-01 | Aida Corporation | Apparatus for scan testing CMOS integrated systems |
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US5012185A (en) * | 1988-10-14 | 1991-04-30 | Nec Corporation | Semiconductor integrated circuit having I/O terminals allowing independent connection test |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5815511A (en) * | 1995-10-13 | 1998-09-29 | Fujitsu Limited | Semiconductor integrated circuit equipped with test circuit |
US6477674B1 (en) * | 1999-12-29 | 2002-11-05 | Intel Corporation | Method and apparatus for conducting input/output loop back tests using a local pattern generator and delay elements |
US6873926B1 (en) * | 2001-02-27 | 2005-03-29 | Cisco Technology, Inc. | Methods and apparatus for testing a clock signal |
US20040049721A1 (en) * | 2002-09-09 | 2004-03-11 | Kevin Laake | Method and apparatus for improving testability of I/O driver/receivers |
US6986087B2 (en) * | 2002-09-09 | 2006-01-10 | Hewlett-Packard Development Company, L.P. | Method and apparatus for improving testability of I/O driver/receivers |
US20040153795A1 (en) * | 2002-10-01 | 2004-08-05 | Toshio Teraishi | Analog voltage output driver LSI chip having test circuit |
US20080265930A1 (en) * | 2002-10-01 | 2008-10-30 | Toshio Teraishi | Semiconductor device including analog voltage output driver LSI chip having test circuit |
US7548079B2 (en) * | 2002-10-01 | 2009-06-16 | Oki Semiconductor Co., Ltd. | Semiconductor device including analog voltage output driver LSI chip having test circuit |
US20040183563A1 (en) * | 2003-03-17 | 2004-09-23 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit including test pins and method for testing thereof |
US7057411B2 (en) * | 2003-03-17 | 2006-06-06 | Samsung Electronics Co., Ltd. | Semiconductor integrated circuit including test pins and method for testing thereof |
Also Published As
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