JPS6218051A - Integrated circuit - Google Patents

Abstract

PURPOSE:To enable a static consumption current IDD to be easily measured to realize speeding-up of characteristic evaluation or fault analysis in CMOS integration, by composing a means in which all input terminals are fixed on either source-voltage or ground level when a test mode is selected. CONSTITUTION:An integrated circuit is composed of P-channel MOS FETs whose sources are connected with VDD, and N-channel MOS FETs whose sources are connected with GND, with all input gates of this circuit connected with their drains, and having an IDD measurement test circuit comprising its test signal connected with its gate terminals. All the input terminals are fixed on a GND level by making the test signal 4 to be on a high level in a certain test mode. The test signal 4 may be applied from an external input terminal, and only connecting an input pin with VDD enables all the input terminals to become on a GND level, to widely simplify the measurement of IDD. Besides, both T1 and T2 are composed as test signals so that the input terminals can be adjusted on either VDD or GND level. Hence, a static consumption current IDD can be easily measured, to realize speeding-up of characteristic evaluation and fault analysis in CMOS integration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS integrated circuit, and particularly to an 0MO8 integrated circuit whose leakage current can be easily measured.

[Conventional technology]

The 0MO8 integrated circuit is characterized in that when each input terminal is fixed at vDD or C peak, that is, when the internal circuit is not operating, it consumes no power other than a small amount of power due to leakage current. Ninth of these characteristics, static power consumption fIrf (referred to as IDD) is an important parameter for evaluating the characteristics of CMOS integrated circuits.

It can also be used to judge the quality of the LSI and the acceptability of circuit connections. -When trying to measure D using the sword manual,
All input terminals must be fixed to VDD or GND voltage, and as the number of bins is increasing recently, 1°D
The reality is that preparing VC for measurement requires a lot of man-hours.

[Inventive power; Problems to be solved] In the above-mentioned nine conventional DD manual measurements, attach lead wires to all the input bins of the IC socket and connect them to VDD or GND. This process requires a lot of man-hours and there is a rare possibility that wiring errors will be introduced.In particular, there has been a remarkable trend towards increasing the number of pins, as typified by gate arrays, and the man-hours have reached a point where it cannot be ignored.

[Means for solving problems]

The integrated circuit of the present invention has a P-channel/I/
It has a 7tN channel MO8FET'i whose source is connected to GND, and whose gate terminal is connected to a test signal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a schematic diagram of a chip showing an embodiment of the present invention.

1 is a bonding pad, 2 is an N-channel M (JSFET) for fixing the 1 input terminal to GND, 3 is a wiring to the input gate, 4 is a test signal, and this signal is set to high in the test mode. By setting the level, all input terminals are fixed at 1GND level.Adding this test signal from the external input terminal is good.With this, all input terminals can be set to 1OND level by connecting only one input bin to vDD. , ■DD measurement is greatly simplified 1. Figure 2 shows the circuit side of one input terminal. 5 is input protection, resistor, 6 is P channel, MOSFET, 7 is manual gate protection element, 8 represents input buffer 1. In the example of FIG. 2, there are two test signals, T1 and T2, and the configuration is such that they can be connected to either the input terminal e VDD or HGND level.

〔Effect of the invention〕

As explained above, the present invention has the effect of being able to fix the input terminal voltage to VDD or GND with a small circuit scale, and easily measuring the static current consumption by stopping the internal operation. Accumulation characterization or failure analysis is speeded up.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of a chip showing an embodiment of the present invention. Figure 2 is a diagram showing the circuit side near the input terminal. 1...Ponding pad, 2...N
Channel M (JSFET, 3... Wiring to internal gate, 4... Test signal wiring, 5...
...Input protection resistor, 6...P channel MO8F
ET, 7... Gate protection element, 8...
input buffer, T1. T2...Test signal.

Claims (1)

[Claims] An integrated circuit having a test mode for testing the function of an LSI, characterized in that the integrated circuit is provided with means for fixing all input terminals to a power supply voltage or ground level when a certain test mode is selected.