JP2968642B2 - Integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device used for an integrated circuit device, and more particularly to an integrated circuit device sealed with a mold package or the like.

[0002]

2. Description of the Related Art FIG. 4 is a circuit diagram showing a main part of a conventional example, and FIG. 5 is a configuration diagram showing an outline thereof.

As shown in FIGS. 4 and 5, a conventional integrated circuit device 54 has an independent check transistor 41 for measuring transistor characteristics which is not connected to an input / output terminal 42. And the check transistor 41
Are connected to a drain electrode pad 61, a source electrode pad 62, and a gate electrode pad 63, respectively, so that the characteristics of the transistor can be measured by connecting a measuring needle.

In FIGS. 4 and 5, reference numeral 44 denotes V
DD terminal, 45 is a GND terminal, 47 is an input buffer, and 48 is an output buffer.

Next, a method for measuring transistor characteristics will be described. FIG. 6 is an explanatory diagram of an N-channel MOS transistor characteristic measuring method.

[0006] If the threshold voltage of the checking transistors 41 illustrates an example of a case of measuring the V _T (transistor gate voltage when the "on" state from the "off" state), grounding the source electrode pad 62 0V And a constant voltage (5
V). In this state, the gate voltage is increased from 0 V to the gate electrode pad 63 by using the variable DC power supply 74, and a current starts flowing through the DC ammeter 72 (for example, 1 μm).
The gate voltage at the time of A) is read by the DC voltmeter 73. The gate voltage at this time is the threshold voltage V _T. The connection with each of the electrode pads 61, 62 and 63 is about 20 μm.
Perform with a small φ needle.

[0007]

In this conventional integrated circuit device, since the check transistor is not connected to the input / output terminal, there is a problem that the transistor characteristics cannot be measured when the device is sealed in a mold package or the like. Further, since the electrode pad of the check transistor does not need to be bonded, the electrode pad of the check transistor has a required minimum size of, for example, about 40 μm square, and there is a problem that it is difficult to connect a needle for measuring transistor characteristics. Was.

An object of the present invention is to solve the above-mentioned problems, so that a measuring needle can be easily connected when measuring the check transistor characteristic, and the transistor characteristic can be easily measured even after the package is sealed. It is to provide an integrated circuit device capable of measuring the temperature.

[0009]

SUMMARY OF THE INVENTION The present invention provides a check transistor for checking characteristics formed on the same substrate,
In an integrated circuit device having an input / output terminal, a power supply terminal, and a ground terminal, the check transistor is connected between the power supply terminal and the ground terminal, and is electrically disconnected from the connected circuit by a switching signal. Said
I / O terminals are P-channel transistor and N-channel transistor
The source and the drain are connected to the transistor
A test switching circuit electrically connected to a control electrode of the check transistor via an electronic switch configured as described above, and an external circuit for inputting the switching signal to the test switching circuit.
And wherein the kite and a terminal.

[0010]

The test switching circuit electrically disconnects an input / output terminal (input terminal and output terminal may be separate) from a connected circuit by a switching signal given from an input terminal also serving as a test terminal. , Check transistor is N
In the case of a channel MOS transistor, the drain electrode is electrically connected to the power supply terminal, and the source electrode is electrically connected to the gate of the MOS transistor connected to the ground terminal.

Thus, a test voltage is applied to the check transistor from the input / output terminal and the current or voltage appearing between the power supply terminal and the ground terminal is measured, so that the transistor characteristics can be easily measured.

At this time, the pads for the terminals to which the measuring needles are connected have a large area for bonding (about 100 μm square), so that they can be easily connected. Further, even after the package is sealed, the transistor characteristics can be easily measured similarly using the external terminals.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention, and FIG. 2 is a configuration diagram showing an outline thereof.

In the first embodiment, a check transistor 1 comprising an N-channel MOS transistor, an input / output terminal 2, a VDD terminal 4 as a power supply terminal, a GND terminal 5 as a ground terminal, a P-channel MOS transistor, An input buffer 7 including an N-channel MOS transistor whose input is connected to the input / output terminal 2;
In an integrated circuit device 14 including an S transistor, an N-channel OS transistor, an output buffer 8 including a NAND gate and a NOR gate, and an output connected to the input / output terminal 2, the drain of the check transistor 1, which is a feature of the present invention, The source is connected to the VDD terminal 4 as a power supply terminal, the source is connected to the GND terminal 5 as a ground terminal, and the input / output terminal 2 is electrically disconnected from the connected input buffer 7 and output buffer 8 by the switching signal 13. Electronic switches 6 and 6a, a NAND gate 9, and inverter gates 10, 11 and 12 as a test switching circuit electrically connected to a gate as a control electrode of the check transistor 1, and a switching signal 13 for externally inputting a switching signal 13. Test terminal 3 as external terminal
And

The electronic switch 6 is a P-channel MO
An S transistor and an N-channel MOS transistor are connected to each other at the source and the drain. One of these common connection points is connected to the input / output terminal 2 and the other is connected to the gate of the check transistor 1, respectively. Is connected to the test terminal 3, the gate of the P-channel MOS transistor is connected to the output of the inverter gate 10,
Is connected to the test terminal 3. Electronic switch 6a
Comprises an N-channel MOS transistor, the drain of which is the gate of the check transistor 1 and the source of which is GN.
The gate of the D terminal 5 is connected to the output of the inverter 10. The NAND gate 9 has two inputs, one input is connected to the output of the inverter gate 10 and the other is connected to the input / output switching signal, and the output is connected to one input of the output buffer 8. The inverter gate 11 has an input connected to the NAND gate 9 and an output connected to the other input of the input buffer 7 and the output buffer 8, respectively. The inverter gate 12 has an input connected to the test terminal 3 and an output connected to the input buffer 7.

Next, the operation of the first embodiment will be described.

The input / output terminal 2 has functions as a normal input / output terminal and a transistor characteristic measuring terminal, and these functions are switched by a switching signal 13 from the test terminal 3. When the switching signal 13 is at "H" level (VDD level), the electronic switch 6 is turned on, the electronic switch 6a, the input buffer 7 and the output buffer 8 are turned off, and the input / output terminal function is disconnected. As a result, a voltage can be applied to the gate of the check transistor 1 from the input / output terminal 2. In this state, the VDD terminal 4 or GN
By connecting a DC ammeter to the D terminal 5, transistor characteristics can be measured.

The input / output terminal 2, test terminal 3, VDD terminal 4, and GND terminal 5 are bonding pads and have a large area, so that a measuring needle can be easily connected. Further, even after sealing with a mold package or the like, the transistor characteristics can be easily measured because the transistor is connected to an external lead via a bonding wire.

On the other hand, when the switching signal 13 from the test terminal 3 is at "L" level (GND level), the electronic switch 6 is turned off, the electronic switch 6a is turned on, and the check transistor 1 is turned on. It will be in the "off" state. The input buffer 7 and the output buffer 8 are connected to the input / output terminal 2, and the input / output terminal 2 can function as a normal input / output terminal function.

In general, integrated circuit devices are generally mass-produced, and a pass / fail test is always performed by using an LSI tester or the like after a wafer state and after a package is sealed. The integrated circuit device of the present invention can measure the transistor characteristics by adding the transistor characteristics measurement items to the test program. Variations in the distribution of characteristics can be easily understood.

FIG. 3 is a block diagram showing the outline of the second embodiment of the present invention.

The second embodiment shows a case where the present invention is applied to an integrated circuit device 34 having a high voltage detection circuit 35.

In the second embodiment, the drain of the check transistor 21 composed of an N-channel MOS transistor is connected to the VDD terminal 24, the source is connected to the GND terminal 25, and the switching signal 33 is a feature of the present invention.
The electronic switches 26 and 26a as test switching circuits for electrically disconnecting the input buffer 27 and the output buffer 28 from the input / output terminal 22 and electrically connecting the gate of the check transistor 21 to the input / output terminal 22 And inverter gates 29a and 30
a. The input terminal 23 of the high voltage detection circuit 35 also serves as a test terminal.

The high-voltage detecting circuit 35 has a P-channel MOS transistor and an N-channel MOS transistor
The switching signal 33 includes transistors connected in series.
Is a P-channel MOS transistor and an N-channel MOS
It is taken out from the common connection point of the transistors via inverter gates 36 and 37.

Next, the operation of the second embodiment will be described.

When a high voltage about twice as high as VDD is applied to the input terminal 23, the switching signal 33 becomes a VDD level signal.
Is electrically disconnected from the input / output terminal 22. On the other hand, the electronic switch 26 is turned on, the electronic switch 26a is turned off, and the gate of the check transistor 21 is electrically connected to the input / output terminal 22 to be in an operating state.

That is, by applying a high voltage of about twice VDD to the input terminal 23, the input / output terminal 22 is switched to a transistor characteristic measurement terminal. When the potential of the input terminal 23 is between the GND potential and the VDD potential, the input / output terminal 22 becomes a normal input / output terminal.

As described above, in the second embodiment,
There is an advantage that the integrated circuit device of the present invention can be configured with the same number of terminals as the conventional integrated circuit device.

[0030]

As described above, according to the present invention,
Since there is a means to use the normal input / output terminal as the characteristic measurement terminal of the check transistor, the measurement of the transistor characteristics can be easily performed not only before the package sealing but also after the package sealing, and the effect is great. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing an outline thereof.

FIG. 3 is a configuration diagram showing an outline of a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a main part of a conventional example.

FIG. 5 is a configuration diagram showing the outline thereof.

FIG. 6 is an explanatory diagram of a method for measuring transistor characteristics.

[Explanation of symbols]

1, 21, 41 Check transistor 2, 22, 42 Input / output terminal 3 Test terminal 4, 24, 44 VDD terminal 5, 25, 45 GND terminal 6, 6a, 26, 26a Electronic switch 7, 27, 47 Input buffer 8, 28, 48 Output buffer 9 NAND gate 9a, 10, 10a, 11, 12, 29a, 30a, 3
6, 37 Inverter gate 13, 33 Switching signal 14, 34, 54 Integrated circuit device 35 High voltage detection circuit 61 Drain electrode pad 62 Source electrode pad 63 Gate electrode pad 71 DC power supply 72 DC ammeter 73 DC voltmeter 74 DC variable power supply

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int. Cl. ⁶ , DB name) G01R 31/26 G01R 31/28 H01L 21/66

Claims (1)

(57) [Claims] 1. An integrated circuit device having a check transistor for checking characteristics formed on the same substrate, an input / output terminal, a power supply terminal, and a ground terminal, wherein the check transistor is provided between the power supply terminal and the ground terminal. The input / output terminal is electrically disconnected from the connected circuit by a switching signal, and the input / output terminal is connected to a P-channel transistor.
Source and the N-channel transistor
A test switching circuit electrically connected to a control electrode of the check transistor via an electronic switch formed by connecting the power supply terminals to each other; and an external terminal for inputting the switching signal to the test switching circuit. /> an integrated circuit device comprising a kite comprising a.