JPH05114636A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH05114636A
JPH05114636A JP27422291A JP27422291A JPH05114636A JP H05114636 A JPH05114636 A JP H05114636A JP 27422291 A JP27422291 A JP 27422291A JP 27422291 A JP27422291 A JP 27422291A JP H05114636 A JPH05114636 A JP H05114636A
Authority
JP
Japan
Prior art keywords
pull
resistor
transistor
pch
nch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27422291A
Other languages
Japanese (ja)
Inventor
Hiroyoshi Ohira
廣吉 大平
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP27422291A priority Critical patent/JPH05114636A/en
Publication of JPH05114636A publication Critical patent/JPH05114636A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To contrive to enhance efficiency of test and to improve quality and reliability thereof by a method wherein a function of a pull-up resistor and a pull-down resistor is stopped by an external terminal. CONSTITUTION:All terminals containing a pull-up resistor and a pull-down resistor are provided with a Pch MOS transistor on the pull-up resistor side in series with a VDD power supply 18, and an Nch MOS transistor on the pull-down resistor side in series with a VSS power supply 19. These control transistors are semiconductor integrated circuits having a circuit function so that, when a control signal from an external unit is in Hi, both the Pch transistor and Nch transistor may be turned ON, and when the control signal is in Lo, both the Pch transistor and Nch transistor may be turned OFF.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置(以下ICと
呼ぶ)の検査方法の改良に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor device (hereinafter referred to as IC) inspection method.

【0002】[0002]

【従来の技術】従来、図2のようなプルアップ抵抗付き
入力端子をもつICの検査も、プルアップ抵抗を持たな
いICの検査と同様に、各端子に機能をチェックするた
めのテストパターンを入力し、期待される出力パターン
を検定する機能チェック(以後AC測定と呼ぶ)と、電
圧印加時に回路に流れる電流チェック(以後DC測定と
呼ぶ)の双方を行なうことによりICの良否を判定して
いた。
2. Description of the Related Art Conventionally, an IC having an input terminal with a pull-up resistor as shown in FIG. 2 is inspected with a test pattern for checking the function of each terminal, similarly to an IC having no pull-up resistor. The quality of the IC is judged by performing both a function check (hereinafter referred to as AC measurement) for inputting and verifying an expected output pattern and a current check (hereinafter referred to as DC measurement) flowing in the circuit when a voltage is applied. It was

【0003】[0003]

【発明が解決しようとする課題】しかし従来の技術で
は、プルアップ抵抗付き入力端子を持つICの検査を行
なう場合、AC測定時には特に問題はないが、DC測定
時に、入力端子にLowレベルを与えたとき、プルアッ
プ抵抗を介して電流が流れ、その電流がトランジスタの
OFFリークに上乗せされるため、ICの信頼性を確保
するのに重要なトランジスタのOFFリークを正確に測
定できないという問題点がある。
However, in the prior art, when inspecting an IC having an input terminal with a pull-up resistor, there is no particular problem during AC measurement, but a low level is applied to the input terminal during DC measurement. At this time, a current flows through the pull-up resistor, and the current is added to the OFF leak of the transistor, so that the OFF leak of the transistor, which is important for ensuring the reliability of the IC, cannot be accurately measured. is there.

【0004】本発明はこのような問題点を解決するもの
で、その目的とするところは、プルアップ抵抗もしくは
プルダウン抵抗に直列にスイッチを付加し、検査時に必
要に応じスイッチをOFFする事により、プルアップ抵
抗もしくはプルダウン抵抗に流れる電流を遮断し、IC
のOFFリークのみの測定を可能にし、ICの品質、信
頼性の向上を図ることである。
The present invention solves such a problem. An object of the present invention is to add a switch in series to a pull-up resistor or a pull-down resistor and turn off the switch if necessary at the time of inspection. The current flowing through the pull-up resistor or pull-down resistor is cut off, and the IC
It is to improve the quality and reliability of the IC by making it possible to measure only the OFF leak.

【0005】[0005]

【課題を解決するための手段】本発明の半導体装置は、
半導体集積回路に使用されている、プルアップ抵抗もし
くはプルダウン抵抗の機能を停止させるスイッチを、同
一半導体基板上に内蔵することを特徴とする。
The semiconductor device of the present invention comprises:
A switch for stopping the function of a pull-up resistor or a pull-down resistor used in a semiconductor integrated circuit is built in on the same semiconductor substrate.

【0006】[0006]

【実施例】以下、本発明を実施例に基づき説明してい
く。
EXAMPLES The present invention will be described below based on examples.

【0007】図1は、本発明の半導体装置の入力端子部
分の回路図である。ICの内部ゲート11に接続されて
いる入力端子17は、VDD電源18に接続されているP
ch側の静電気保護ダイオード14とVSS電源19に接
続されているNch側の静電気保護ダイオード15およ
び静電気保護抵抗16で構成されている静電気保護回路
を持ち、また、入力端子17をプルアップするためのプ
ルアップ抵抗12とプルアップ抵抗に直列に接続された
プルアップ制御トランジスタ13を持つ。このプルアッ
プ制御トランジスタ13はPchのMOSトランジスタ
でできておりゲートにコントロール信号Hiを与えるこ
とによりプルアップ抵抗12を電気的にVDD電源18か
ら切り離す役目をする。
FIG. 1 is a circuit diagram of an input terminal portion of a semiconductor device of the present invention. The input terminal 17 connected to the internal gate 11 of the IC has a P terminal connected to the VDD power source 18.
It has an electrostatic protection circuit composed of an electrostatic protection diode 14 on the ch side, an electrostatic protection diode 15 on the Nch side connected to the VSS power supply 19 and an electrostatic protection resistor 16, and also for pulling up the input terminal 17. It has a pull-up resistor 12 and a pull-up control transistor 13 connected in series with the pull-up resistor. The pull-up control transistor 13 is made of a Pch MOS transistor, and serves to electrically disconnect the pull-up resistor 12 from the VDD power source 18 by applying a control signal Hi to the gate.

【0008】実際のアプリケーションでは、プルアップ
抵抗、プルダウン抵抗を含む端子は複数存在するため、
プルアップ抵抗、プルダウン抵抗を持つ全端子に、プル
アップ抵抗側にはプルアップ抵抗と直列にPchのMO
SトランジスタをVDD電源18と接続し、またプルダウ
ン抵抗側にはプルダウン抵抗と直列にNchのMOSト
ランジスタをVSS電源19と接続した。そしてそれらの
制御トランジスタには、外部からのコントロール信号が
Hiの時Pchトランジスタ、Nchトランジスタがと
もにONし、コントロール信号がLoの時はPchトラ
ンジスタ、NchトランジスタがともにOFFするよう
に回路機能をもたせた。これによりプルアップ抵抗とプ
ルダウン抵抗を、外部端子からの制御により同時にそれ
ぞれの電源と接続したり、切り離したりすることができ
るようになった。
In an actual application, since there are a plurality of terminals including pull-up resistors and pull-down resistors,
MO of Pch is connected in series with the pull-up resistor on all terminals with pull-up resistor and pull-down resistor.
The S transistor was connected to the VDD power source 18, and the Nch MOS transistor was connected to the VSS power source 19 in series with the pull-down resistor on the pull-down resistor side. Then, these control transistors have a circuit function so that both the Pch transistor and the Nch transistor are turned on when the external control signal is Hi, and both the Pch transistor and the Nch transistor are turned off when the control signal is Lo. . As a result, the pull-up resistor and pull-down resistor can be connected to or disconnected from each power source at the same time by controlling from the external terminal.

【0009】ICの検査を行なう場合、AC測定は、外
部からのコントロール信号がHiもしくはLoのどちら
の状態でも行なうことができるが、コントロール信号が
Loの状態ではプルアップ抵抗、プルダウン抵抗が切り
離された状態にあり、入力状態が不定となるため機能評
価ができない場合がある。これを避けるためプルアップ
抵抗を持つ端子、プルダウン抵抗を持つ端子入力につい
ては入力状態が不定とならないように入力状態を固定す
る必要がある。また、DC測定をする場合、外部からの
コントロール信号がHiの場合には、例えば、プルアッ
プされた入力端子では、プルアップ抵抗に直列に接続さ
れている制御トランジスタはONしているため、入力端
子の信号がLoの状態になった時、電源VDDからプルア
ップ抵抗を通して入力端子に流れる電流がVDD側の電流
計を流れる電流に上乗せされ、ICの信頼性を確保する
ために必要なOFFリークを分離して測定できない。こ
のような場合は、本発明により、外部からのコントロー
ル信号をLoにし、プルアップ抵抗を電気的に切り離し
DC測定を行なう。こうすることによりICのOFFリ
ークを分離し測定することができる。また、入力端子の
リークも分離して測定することができる。
When the IC is inspected, the AC measurement can be performed when the external control signal is either Hi or Lo, but when the control signal is Lo, the pull-up resistor and pull-down resistor are disconnected. Since the input status is undefined, the function evaluation may not be possible. To avoid this, it is necessary to fix the input state so that the input state of the terminal with pull-up resistor and the terminal with pull-down resistor does not become undefined. Further, in the case of DC measurement, when the control signal from the outside is Hi, for example, at the input terminal pulled up, the control transistor connected in series to the pull-up resistor is ON, so When the signal at the terminal is in the Lo state, the current flowing from the power supply VDD through the pull-up resistor to the input terminal is added to the current flowing through the ammeter on the VDD side, and the OFF leakage required to secure the reliability of the IC Cannot be measured separately. In such a case, according to the present invention, the control signal from the outside is set to Lo, the pull-up resistor is electrically disconnected, and DC measurement is performed. By doing so, the OFF leakage of the IC can be separated and measured. In addition, the leak of the input terminal can be measured separately.

【0010】[0010]

【発明の効果】上述のように本発明の半導体装置によれ
ば、ICのプルアップ抵抗、プルダウン抵抗の機能を停
止できることから、ICのOFFリークや入力リークの
測定が可能となり、品質、信頼性の大幅な向上が期待で
きる。
As described above, according to the semiconductor device of the present invention, since the functions of the pull-up resistor and the pull-down resistor of the IC can be stopped, the OFF leak and the input leak of the IC can be measured, and the quality and the reliability can be improved. Can be expected to improve significantly.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例である半導体装置の入力部の回
路図。
FIG. 1 is a circuit diagram of an input section of a semiconductor device that is an embodiment of the present invention.

【図2】従来の半導体装置の入力部の回路図。FIG. 2 is a circuit diagram of an input section of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

11 ICの内部ゲート 12 プルアップ抵抗 13 プルアップ制御トランジスタ 14 Pch側静電気保護ダイオード 15 Nch側静電気保護ダイオード 16 静電気保護抵抗 17 入力端子 18 VDD電源供給線 19 VSS電源供給線 21 ICの内部ゲート 22 プルアップ抵抗 23 Pch側静電気保護ダイオード 24 Nch側静電気保護ダイオード 25 静電気保護抵抗 26 入力端子 27 VDD電源供給線 28 VSS電源供給線 11 IC internal gate 12 Pull-up resistor 13 Pull-up control transistor 14 Pch side static electricity protection diode 15 Nch side static electricity protection diode 16 Static electricity protection resistor 17 Input terminal 18 VDD power supply line 19 VSS power supply line 21 IC internal gate 22 Pull Up resistance 23 Pch side static electricity protection diode 24 Nch side static electricity protection diode 25 Static electricity protection resistor 26 Input terminal 27 VDD power supply line 28 VSS power supply line

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体集積回路に使用されている、プル
アップ抵抗、プルダウン抵抗の機能を停止させるスイッ
チを、同一半導体基板上に内蔵することを特徴とする半
導体装置。
1. A semiconductor device comprising a switch for stopping the functions of a pull-up resistor and a pull-down resistor, which are used in a semiconductor integrated circuit, built in on the same semiconductor substrate.
JP27422291A 1991-10-22 1991-10-22 Semiconductor device Pending JPH05114636A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27422291A JPH05114636A (en) 1991-10-22 1991-10-22 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27422291A JPH05114636A (en) 1991-10-22 1991-10-22 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH05114636A true JPH05114636A (en) 1993-05-07

Family

ID=17538728

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27422291A Pending JPH05114636A (en) 1991-10-22 1991-10-22 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH05114636A (en)

Similar Documents

Publication Publication Date Title
US5570034A (en) Using hall effect to monitor current during IDDQ testing of CMOS integrated circuits
JPS61265829A (en) Semiconductor integrated circuit
JP3587300B2 (en) Integrated circuit device
US5721495A (en) Circuit for measuring quiescent current
JPH08507868A (en) Separation of signal path and bias path in IC I Bottom DDQ test
Mallarapu et al. Iddq testing on a custom automotive IC
US8648617B2 (en) Semiconductor device and method of testing semiconductor device
JPH05114636A (en) Semiconductor device
US5412337A (en) Semiconductor device providing reliable conduction test of all terminals
JPH0354841A (en) Bicmos semiconductor device
JP2968642B2 (en) Integrated circuit device
JP2014163851A (en) Semiconductor integrated circuit with open detection terminal
Peters et al. Realistic defect coverages of voltage and current tests
JP2963234B2 (en) High-speed device test method
JPH05273298A (en) Semiconductor integrated circuit device and its test method
Muhtaroglu et al. I/O self-leakage test
TAKAGI et al. Lead open detection based on supply current of CMOS LSIs
JP3194740B2 (en) Semiconductor integrated circuit capable of measuring leak current
Miura et al. A low-loss built-in current sensor
JPS6337268A (en) Tester of semiconductor device
JPS63223577A (en) Semiconductor integrated circuit
JPS58111533A (en) Input circuit
JP3132635B2 (en) Test method for semiconductor integrated circuit
JPH0560841A (en) Semiconductor device
KR19990048279A (en) Leakage current inspection method and device by voltage measurement