JPH0254546A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPH0254546A
JPH0254546A JP63205836A JP20583688A JPH0254546A JP H0254546 A JPH0254546 A JP H0254546A JP 63205836 A JP63205836 A JP 63205836A JP 20583688 A JP20583688 A JP 20583688A JP H0254546 A JPH0254546 A JP H0254546A
Authority
JP
Japan
Prior art keywords
terminal
output
channel transistor
gate
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63205836A
Other languages
Japanese (ja)
Inventor
Taketoshi Hayakawa
早川 武利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63205836A priority Critical patent/JPH0254546A/en
Publication of JPH0254546A publication Critical patent/JPH0254546A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable measurement of a threshold voltage Vr from an IC terminal by providing a connection switching means of an output terminal which outputs an output of an output buffer connected with a P-channel and N-channel MOS transistor in series to the outside of an IC. CONSTITUTION:A terminal 1 is connected to GND, and a gate of an N-channel transistor 12 attains Low level and an output of the N-channel transistor 12 is in the high impedance state. A variable power source 17 is operated and an electric potential is provided to a gate of a P-channel transistor 11 by providing an electric potential to a terminal 2. In this state, Vr value of the P-channel transistor 11 is measured by measuring a value of an ammeter 16.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路(以後ICと呼ぶ)に関し、
スレッシュホールド電圧(以後V↑と呼ぶ)を測定でき
る出力バッファを有するICに関する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit (hereinafter referred to as an IC).
The present invention relates to an IC having an output buffer capable of measuring a threshold voltage (hereinafter referred to as V↑).

〔従来の技術〕[Conventional technology]

従来のICは、ICチップ上に空領域を設け、この領域
にICの内部回路には寄与しない単体のトランジスタ(
以後チエツク・トランジスタと呼ぶ)を作り、そのチエ
ツク・トランジスタに専用の測定装置を直接接続するこ
とによりVT値を測定していた。
Conventional ICs have an empty area on the IC chip, and in this area, a single transistor (
The VT value was measured by creating a check transistor (hereinafter referred to as a check transistor) and directly connecting a dedicated measuring device to the check transistor.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

前述した従来のICは、VT値の測定に専用の測定装置
を必要とし、又、ICチップに直接測定装置を接続しな
ければならず、ICチップを組立て封入してしまった後
では、測定装置が接続できず、VT値の測定が出来ない
という欠点がある。
The conventional IC described above requires a dedicated measuring device to measure the VT value, and the measuring device must be connected directly to the IC chip. It has the disadvantage that it cannot be connected and the VT value cannot be measured.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体集積回路は、PチャネルMOSトランジ
スタ及びNチャネルMOSトランジスタを直列に接続し
てなる出力バッファと、前記出力バッファの出力をIC
外部へ出力する出力端子と、前記出力端子及び電源端子
以外の別端子と前記出カバッファのゲートに半導体集積
回路の内部信号線を接続するかあるいは前記別端子を接
続するかの切換え手段とを含んで構成される。
The semiconductor integrated circuit of the present invention includes an output buffer formed by connecting a P-channel MOS transistor and an N-channel MOS transistor in series, and an output buffer that connects the output of the output buffer to an IC.
It includes an output terminal for outputting to the outside, a separate terminal other than the output terminal and the power supply terminal, and means for switching whether to connect an internal signal line of the semiconductor integrated circuit to the gate of the output buffer or to connect the separate terminal. Consists of.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は、本発明の一実施例の回路図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

切り換え回路aは、ICの通常動作時は、LOWレベル
となり、V子側定時は、Highレベルとなる信号であ
る。
The switching circuit a is a signal that is at a LOW level during normal operation of the IC, and is at a HIGH level when the V side is in regular operation.

ICの通常動作時、切換え信号aは、Lowレベルであ
ることにより、トランスファーゲート4〜7はON状態
となり、トランスファーゲート9゜10はOFF状態と
なる。端子1,2からの入力信号は、トランスファーゲ
ート4,5を通じて、IC内部へ伝わり、IC内部から
の出力信号は、トランスファーゲート4,5を通じて端
子1.2へ出力される。出力バッファトランジスタ11
゜12のゲートは、トランスファーゲート9,10によ
り端子1.2から絶縁され、ICの内部回路の出力がト
ランスファーゲート6.7を通じて出力バッファトラン
ジスタ11.12のゲートへ伝えられる。前述の状態に
よりICは通常動作が可能となる。
During normal operation of the IC, the switching signal a is at a low level, so that transfer gates 4 to 7 are in an ON state, and transfer gates 9 and 10 are in an OFF state. Input signals from terminals 1 and 2 are transmitted inside the IC through transfer gates 4 and 5, and output signals from inside the IC are output through transfer gates 4 and 5 to terminal 1.2. Output buffer transistor 11
12 is isolated from terminal 1.2 by transfer gates 9, 10, and the output of the internal circuit of the IC is transmitted through transfer gate 6.7 to the gate of output buffer transistor 11.12. The above state allows the IC to operate normally.

V、値測定時、切換え信号aは、Highレベルである
ことより、トランスファーゲート4〜7はOFF状態と
なり、トランスファーゲート9゜10はON状態となる
。端子1,2及び出力バッファ13を構成するPチャネ
ルトランジスタ11及びNチャネルトランジスタ12の
ゲートは、トランスファーゲート4〜7により、IC内
部より絶縁される。Pチャネルトランジスタ11のゲー
トは、トランスファーゲート10により端子2と接続さ
れ、Nチャネルトランジスタ12のゲートはトランスフ
ァーゲート9により端子1と接続され、端子1,2に電
位を与える事により両トランジスタを直接動作させるこ
とが可能となる。
Since the switching signal a is at a high level when measuring V, the transfer gates 4 to 7 are in the OFF state, and the transfer gates 9 and 10 are in the ON state. The gates of the P-channel transistor 11 and the N-channel transistor 12 constituting the terminals 1 and 2 and the output buffer 13 are insulated from the inside of the IC by transfer gates 4 to 7. The gate of P-channel transistor 11 is connected to terminal 2 by transfer gate 10, and the gate of N-channel transistor 12 is connected to terminal 1 by transfer gate 9. Both transistors can be operated directly by applying a potential to terminals 1 and 2. It becomes possible to do so.

第2図は前記状態におけるPチャネルトランジスタ1の
VT値測測定行う場合の測定回路図である。
FIG. 2 is a measurement circuit diagram when measuring the VT value of the P-channel transistor 1 in the above state.

端子1はGND (接地端子でLowレベル)と接続さ
れていることより、Nチャネルトランジスタ12のゲー
トはLowレベルとなり、Nチャネルトランジスタ12
の出力はハイインピーダンス状態となる。可変電源17
を操作し、端子2に電位を与える事によりPチャネルト
ランジスタ11のゲートに電位が与えられる。
Since terminal 1 is connected to GND (ground terminal and low level), the gate of N-channel transistor 12 becomes low level, and N-channel transistor 12
The output becomes a high impedance state. Variable power supply 17
By operating the terminal 2 and applying a potential to the terminal 2, a potential is applied to the gate of the P-channel transistor 11.

前記状態において、電流計16の値を測定することによ
り、Pチャネルトランジスタ11のVT値を測定する。
In the above state, the VT value of the P-channel transistor 11 is measured by measuring the value of the ammeter 16.

なお15は半導体集積回路14全体に供給する固定電源
である6 第3図はNチャネルトランジスタ12のvT値測測定行
う場合の測定回路図である。
Note that 15 is a fixed power supply that is supplied to the entire semiconductor integrated circuit 14. FIG. 3 is a measurement circuit diagram when measuring the vT value of the N-channel transistor 12.

Nチャネルトランジスタ12のVT値測測定方法は、前
述のPチャネルトランジスタ11のVt値測測定行う場
合と同様である。但し端子2はVDDに接続し、可変電
源17の出力は端子1に接、続する。
The method for measuring the VT value of the N-channel transistor 12 is the same as the method for measuring the Vt value of the P-channel transistor 11 described above. However, terminal 2 is connected to VDD, and the output of variable power supply 17 is connected to terminal 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、ICの端子よりVT値
の測定が可能な事により、専用の測定装置を必要とせず
、ウェハー状態では、プローブカードを用いて、組立て
後であれば、ICソケットを用いてのVT値測測定でき
る効果がある。又、ICの端子によるVT値の測定が可
能であるため、ICチップを封入されているICにおい
てもVTの測定ができる効果がある。
As explained above, the present invention makes it possible to measure the VT value from the terminals of the IC, so there is no need for a dedicated measuring device. This has the effect of making it possible to measure the VT value using a socket. Furthermore, since the VT value can be measured using the terminals of the IC, there is an effect that the VT can be measured even in an IC in which an IC chip is encapsulated.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例、の回路図、第2図はPチャ
ネルトランジスタのVT値測定回路図、第3図はNチャ
ネルトランジスタのVT値測定回路図である。 1.2.3・・・ICの端子、4,5.6,7,9゜1
0・・・トランスファーゲート、8・・・インバータ、
11・・・Pチャネルトランジスタ、12・・・Nチャ
ネルトランジスタ、13・・・出力バッファ、14・・
・半導体集積回路、15・・・固定電源、16・・・電
流計、17・・・可変電源。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a VT value measurement circuit diagram of a P-channel transistor, and FIG. 3 is a VT value measurement circuit diagram of an N-channel transistor. 1.2.3...IC terminal, 4, 5.6, 7, 9゜1
0...Transfer gate, 8...Inverter,
11...P channel transistor, 12...N channel transistor, 13...output buffer, 14...
- Semiconductor integrated circuit, 15... Fixed power supply, 16... Ammeter, 17... Variable power supply.

Claims (1)

【特許請求の範囲】[Claims] PチャネルMOSトランジスタ及びNチャネルMOSト
ランジスタを直列に接続してなる出力バッファと、前記
出力バッファの出力をIC外部へ出力する出力端子と、
前記出力端子及び電源端子以外の別端子と前記出力バッ
ファのゲートに半導体集積回路の内部信号線を接続する
かあるいは前記別端子を接続するかの切換え手段を含む
ことを特徴とする半導体集積回路。
an output buffer formed by connecting a P-channel MOS transistor and an N-channel MOS transistor in series; an output terminal for outputting the output of the output buffer to the outside of the IC;
A semiconductor integrated circuit comprising: switching means for connecting an internal signal line of the semiconductor integrated circuit to another terminal other than the output terminal and the power supply terminal and the gate of the output buffer, or connecting the other terminal to the gate of the output buffer.
JP63205836A 1988-08-18 1988-08-18 Semiconductor integrated circuit Pending JPH0254546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63205836A JPH0254546A (en) 1988-08-18 1988-08-18 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63205836A JPH0254546A (en) 1988-08-18 1988-08-18 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH0254546A true JPH0254546A (en) 1990-02-23

Family

ID=16513517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63205836A Pending JPH0254546A (en) 1988-08-18 1988-08-18 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH0254546A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258862A (en) * 1988-08-24 1990-02-28 Nec Corp Semiconductor integrated circuit
JP2002125215A (en) * 2000-10-12 2002-04-26 Nippon Telegr & Teleph Corp <Ntt> Method for providing advertisement in video on demand system, its system and recording medium for recording its program

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258862A (en) * 1988-08-24 1990-02-28 Nec Corp Semiconductor integrated circuit
JP2002125215A (en) * 2000-10-12 2002-04-26 Nippon Telegr & Teleph Corp <Ntt> Method for providing advertisement in video on demand system, its system and recording medium for recording its program

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