JPS58123474A - Circuit for measuring threshold voltage of transistor - Google Patents

Circuit for measuring threshold voltage of transistor

Info

Publication number
JPS58123474A
JPS58123474A JP57006980A JP698082A JPS58123474A JP S58123474 A JPS58123474 A JP S58123474A JP 57006980 A JP57006980 A JP 57006980A JP 698082 A JP698082 A JP 698082A JP S58123474 A JPS58123474 A JP S58123474A
Authority
JP
Japan
Prior art keywords
vdd
threshold voltage
terminals
transistor
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57006980A
Other languages
Japanese (ja)
Inventor
Shinji Terawaki
寺脇 真司
Masahiro Kamiizumi
上泉 眞裕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC Corp
Nippon Electric Co Ltd
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd, NEC IC Microcomputer Systems Co Ltd filed Critical NEC Corp
Priority to JP57006980A priority Critical patent/JPS58123474A/en
Publication of JPS58123474A publication Critical patent/JPS58123474A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2608Circuits therefor for testing bipolar transistors

Abstract

PURPOSE:To enable easy measurement of threshold voltage of a transistor in a semiconductor integrated circuit, even in a finished product, after it is sealed into a container by providing a plurality of inverter circuits into which partial voltages are inputted from a plurality of varied intermediate points of a resistance between two power sources different in the potential. CONSTITUTION:When the resistance value of a resistance 2 is set at R, intermediate terminals 3, 4 and 5 are so positioned that a resistance value between terminals 1-3, 3-4, 4-5 and 5-GND becomes R/4. When a power source +VDD is applied thereto, the output of an inverter 15, namely, an external terminal 18 moves to L if a potential 3/4 VDD at the input 3 of an enhancement transistor 12 of an inverter circuit 15 exceeds the threshold voltage thereof while it reaches H if it does not. When all outputs are L, the threshold voltage is between GND and 1/4 VDD while it is between 3/4 VDD and VDD when all outputs are H. In addition, when a terminal 18 is H and terminals 19-20 are L, the threshold voltage ranges 2/4 VDD-3/4VDD. When terminals 18 and 19 are H and a terminal 20 is L, it ranges 1/4 VDD-2/4 VDD. Thus, the threshold voltage can be measured easily even in a finished product contained in a container.

Description

【発明の詳細な説明】 本発明は半導体集積回路のトランジスタのしきい電圧測
定に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to threshold voltage measurement of transistors in semiconductor integrated circuits.

、同一ウニバー上に同一の条件で作られる半導体集積回
路のトランジスタのしきい電圧は略均−となる。そこで
従来は、トランジスタのソース、ドレイン、ゲートがど
こにも接続されないしきい電圧測定用のトランジスタを
ウェノ1−上あるいは半導体集積回路のチップ上に設け
、このトランジスタのソース、ドレイン、ゲートには外
部との接続を取易くするだめのパッドを備え、これらに
先端が微小な針状の導体などを用いて測定器を接続し、
半導体集積回路のトランジスタのしきい電圧を測定して
いた。そのためにしきい電圧の測定には多くの工数を喪
し容易に(I++ ’itすることができなかった。ま
た、外部との接続が可能な状態、例えばウェハーやチッ
プの様な状態でないと測定できなかった。
, the threshold voltages of transistors of semiconductor integrated circuits manufactured on the same univer under the same conditions are approximately equal. Therefore, conventionally, a transistor for threshold voltage measurement, whose source, drain, and gate are not connected anywhere, was provided on the semiconductor integrated circuit chip or on the chip of the semiconductor integrated circuit, and the source, drain, and gate of this transistor were connected to the outside. It is equipped with pads to make it easier to connect the measuring device, and a measuring device is connected to these using a needle-like conductor with a minute tip.
I was measuring the threshold voltage of transistors in semiconductor integrated circuits. For this reason, measuring the threshold voltage required a lot of man-hours and could not be done easily (I++'it).Also, it could not be measured unless it was in a state where it could be connected to the outside, such as a wafer or chip. There wasn't.

本発明は半導体集積回路のトランジスタのしきい電圧を
容易にしかも容器に封入後の完成品でも測定できるしき
い電圧測定回路を提供することを目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a threshold voltage measuring circuit that can easily measure the threshold voltage of a transistor in a semiconductor integrated circuit even in a finished product sealed in a container.

本発明では電位の異なる2つの電源間にある抵抗の任意
の相異なる中途点を入力をする複数のインバータ回路を
設け、その出力部を外部端子に接続する。そこで、電源
を印加すると、各インバー夕回路の入力には抵抗に依シ
分割された電圧が入力され、この時の各インバータ回路
の出方電位を外部端子から測定することに依シ、しきい
電圧を知ることができる。ゆえに、容易にしかも容器に
入った完成品でもトランジスタのしきい電圧を測定する
ことができる様になる。
In the present invention, a plurality of inverter circuits are provided to input arbitrarily different intermediate points of a resistor between two power sources having different potentials, and the output portions thereof are connected to an external terminal. Therefore, when power is applied, the voltage divided by the resistors is input to the input of each inverter circuit, and the threshold value is determined by measuring the output potential of each inverter circuit at this time from the external terminal. You can know the voltage. Therefore, it becomes possible to easily measure the threshold voltage of a transistor even when the finished product is housed in a container.

次に本発明の一実施例について図面を用いて説明する。Next, one embodiment of the present invention will be described using the drawings.

第1図において、端子1,6,7.8は正電源(VDD
 )用であシ、抵抗2は拡散層あるいは多結晶シリコン
等に依シ作られる。トランジスタ9゜10.11は負荷
となるデプレッショントランジスタであり、)2ンジス
タ12,13.14はエンハンスメントトランジスタで
ある。インバータ回路15゜16、17は各々トランジ
スタ6と12.7と13゜8と14に依シ構成される。
In Figure 1, terminals 1, 6, 7.8 are the positive power supply (VDD
), the resistor 2 is made of a diffusion layer or polycrystalline silicon. Transistors 9, 10, and 11 are depletion transistors serving as loads, and transistors 12, 13, and 14 are enhancement transistors. The inverter circuits 15.16, 17 are constructed based on transistors 6, 12.7, 13.8 and 14, respectively.

抵抗2の中間端子3゜4.5は各々インバータ回路。1
5,16.17の入力である。
Intermediate terminals 3°4.5 of resistor 2 are inverter circuits. 1
5, 16, and 17 inputs.

ここで、抵抗2の抵抗値をRとした時、端子1−3 、
3−4 、4−5 、5− GND間の抵抗値がR/4
となる様に中間端子3,4.5の位置を取る。そこで電
源+VDDを印加すると、インバータ回路150入力3
の電位は3/4vDD、インバータ回路160入力4の
電位は2/4vDD、インバータ回路17の入力5の電
位は1/4 VDDとなシ、インバータ回路15のエン
ハンスメントトランジスタ12のしきい電圧に対してそ
の人力3の電位3/4 VDDがそれを越えていればイ
ンバータ回路15の出力即ち外部端子18は低(@1”
)となシ、越えていなければ(”H”)となる。
Here, when the resistance value of resistor 2 is R, terminals 1-3,
The resistance value between 3-4, 4-5, 5-GND is R/4
Position intermediate terminals 3, 4.5 so that Then, when the power supply +VDD is applied, the inverter circuit 150 input 3
The potential of the input 4 of the inverter circuit 160 is 2/4 vDD, the potential of the input 5 of the inverter circuit 17 is 1/4 VDD, with respect to the threshold voltage of the enhancement transistor 12 of the inverter circuit 15. If the potential 3/4 VDD of the human power 3 exceeds it, the output of the inverter circuit 15, that is, the external terminal 18 is low (@1"
) and if it is not exceeded, it will be (“H”).

同様にして、インバータ回路16の出力は外部端子19
、インバータ回路17の出力は外部端子20へと出力さ
れる。この時、各インバータ回路15゜16.17の出
力は各々外部端子18.19.20に出力され、その結
果全ての出力が@L@ならば令インバータ回路15,1
6.17を構成するエンI・ンスメントトランジスタ1
2’、13.14は導通状態にあるわけで、その入力3
,4.Sの電位はトランジスタ12.13.14のしき
い電圧を越えているわけであシ、この場合の敷居電圧は
GND −、−”/4 VDDの間ということになる。
Similarly, the output of the inverter circuit 16 is connected to the external terminal 19.
, the output of the inverter circuit 17 is output to the external terminal 20. At this time, the outputs of the inverter circuits 15, 16, and 17 are output to the external terminals 18, 19, and 20, respectively, and as a result, if all outputs are @L@, then the inverter circuits 15, 1
6.17 Enforcement transistor 1
2', 13.14 are in a conductive state, so their input 3
,4. The potential of S exceeds the threshold voltage of transistors 12, 13, and 14, and the threshold voltage in this case is between GND - and -''/4 VDD.

また、全ての出力が1H1の場合は、インバータ回路の
各入力3.4.5の電位はトランジスター2,13.1
4のしきい電圧を越えていないわけであり、しきい電圧
は3/4 ’/DD〜VDDの間ということになる。
In addition, when all outputs are 1H1, the potential of each input 3.4.5 of the inverter circuit is the transistor 2, 13.1.
This means that the threshold voltage of 4 is not exceeded, and the threshold voltage is between 3/4'/DD and VDD.

さらに端子18が1H”、端子19〜20が智り曽の時
(D Ll イX圧ti 2/4 VDD −3/4 
VDD1m子18 。
Furthermore, when terminal 18 is 1H" and terminals 19 to 20 are at Chiriso (D Ll IX pressure ti 2/4 VDD -3/4
VDD1m child 18.

19が@ H雫、端子2oが@I、wの時のしきい電圧
Fi/4 VDD 〜”/4 VDD トナh。
The threshold voltage when 19 is @H drop and terminal 2o is @I, w is the threshold voltage Fi/4 VDD ~”/4 VDD Tona h.

以上FiNチャンネルMO8についての説明をしたもの
であるが、同様にPチャンネルMO8についても可能で
ある。
Although the FiN channel MO8 has been described above, the P channel MO8 can be similarly described.

したがって、以上の様にして半導体集積回路のトランジ
スタのしきい電圧を容易にしかも容器に入った完成品で
も測定することができる。
Therefore, as described above, the threshold voltage of a transistor in a semiconductor integrated circuit can be easily measured even in a finished product placed in a container.

分w4能をよくするためには、インバータ回路をpBや
せばよく、十VDDの値を変化させて測定するかあるい
は第1図における抵抗2の電源lを他とは別電僚にして
、それを変化させて測定してもよい。
In order to improve the inverter circuit's pB, it is possible to improve the inverter circuit by changing the value of 10 VDD, or by making the power supply l of resistor 2 in Fig. 1 a separate power supply. The measurement may be performed by changing the .

また、第1図における抵抗2による消費電力が無視でき
なければ抵抗2と直列にテスト信号で制御するトランス
ファーゲートを電源1あるいはGND間に挿入すること
に依シ、テスト時以外は通電しないようにすればよい。
Also, if the power consumption by resistor 2 in Figure 1 cannot be ignored, it is recommended to insert a transfer gate controlled by a test signal in series with resistor 2 between power supply 1 or GND, so that it is not energized except during testing. do it.

さらに、外部端子を通常の入出力端子と兼用する場合に
は、外部端子とインバータ回路の出力の間にテスト信号
で制御するマルチプレクサ回路を挿入することに依シ。
Furthermore, when the external terminal is used also as a normal input/output terminal, it is necessary to insert a multiplexer circuit controlled by a test signal between the external terminal and the output of the inverter circuit.

兼用することが可能である。Can be used for both purposes.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図である。 1.6,7.8・・・・・・+VDDIIIC1!li
、2・・・・・・抵抗、3゜4.5・・・・・・抵抗2
の任意の中途点でsb、インバータ回路15,16.1
7の入力、9.10,11・・・・・・負荷としてのデ
プレッシ冒ントランジスタ、12゜13.14・・・・
・・エンハンスメントトランジスタ、15・・・・・・
9と12のトランジスタから構成されるインバータ回路
。 代理人 弁理士  内 原   晋  二)  −
FIG. 1 is a circuit diagram showing an embodiment of the present invention. 1.6, 7.8...+VDDIIIC1! li
, 2...Resistance, 3゜4.5...Resistance 2
sb, inverter circuits 15, 16.1 at any intermediate point of
7 input, 9.10, 11... Depressive transistor as load, 12゜13.14...
...Enhancement transistor, 15...
An inverter circuit consisting of 9 and 12 transistors. Agent: Patent Attorney Shinji Uchihara) −

Claims (1)

【特許請求の範囲】[Claims] 電位の異なる2つの電源間に接続された抵抗の、相異な
る複数の中間点からの各分圧電圧を入力とする複数のイ
ンバータ回路を設け、該インバータ回路の出力を外部端
子に接続し、該外部端子の出力電圧を測定することに依
シ、該インバータのしきい電圧を測定しうるようにした
ことを特徴としたトランジスタしきい電圧測定回路。
A plurality of inverter circuits each receiving divided voltages from a plurality of different midpoints of resistors connected between two power supplies with different potentials are provided, and the outputs of the inverter circuits are connected to external terminals. A transistor threshold voltage measuring circuit characterized in that the threshold voltage of the inverter can be measured by measuring the output voltage of an external terminal.
JP57006980A 1982-01-20 1982-01-20 Circuit for measuring threshold voltage of transistor Pending JPS58123474A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57006980A JPS58123474A (en) 1982-01-20 1982-01-20 Circuit for measuring threshold voltage of transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57006980A JPS58123474A (en) 1982-01-20 1982-01-20 Circuit for measuring threshold voltage of transistor

Publications (1)

Publication Number Publication Date
JPS58123474A true JPS58123474A (en) 1983-07-22

Family

ID=11653330

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57006980A Pending JPS58123474A (en) 1982-01-20 1982-01-20 Circuit for measuring threshold voltage of transistor

Country Status (1)

Country Link
JP (1) JPS58123474A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59182535A (en) * 1983-03-29 1984-10-17 モトロ−ラ・インコ−ポレ−テツド On-chip voltage monitor and method of using same
JP2008139095A (en) * 2006-11-30 2008-06-19 Toshiba Microelectronics Corp Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59182535A (en) * 1983-03-29 1984-10-17 モトロ−ラ・インコ−ポレ−テツド On-chip voltage monitor and method of using same
JP2008139095A (en) * 2006-11-30 2008-06-19 Toshiba Microelectronics Corp Semiconductor device

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