JP2858390B2 - Method for measuring characteristics of vertical semiconductor device - Google Patents
Method for measuring characteristics of vertical semiconductor deviceInfo
- Publication number
- JP2858390B2 JP2858390B2 JP6058204A JP5820494A JP2858390B2 JP 2858390 B2 JP2858390 B2 JP 2858390B2 JP 6058204 A JP6058204 A JP 6058204A JP 5820494 A JP5820494 A JP 5820494A JP 2858390 B2 JP2858390 B2 JP 2858390B2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- source
- drain
- chip
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims description 12
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000001514 detection method Methods 0.000 claims description 18
- 238000005259 measurement Methods 0.000 description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000000758 substrate Substances 0.000 description 4
- 239000000523 sample Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000008186 active pharmaceutical agent Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000691 measurement method Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7815—Vertical DMOS transistors, i.e. VDMOS transistors with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は、ソース電極とゲート電
極が表面にあり、ドレイン電極が裏面にあるような縦型
トランジスタの特性を測定する方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for measuring characteristics of a vertical transistor having a source electrode and a gate electrode on the front surface and a drain electrode on the back surface.
【０００２】[0002]
【従来の技術】従来、縦型パワーＭＯＳＦＥＴでは、表
面にボンディングの可能なゲート電極、ソース電極が設
けられ、裏面にドレイン電極が形成されている。そのド
レイン電極は、電気的接合と放熱特性を考慮して、チッ
プ裏面の全体に接合用金属皮膜を形成することで形成さ
れている。2. Description of the Related Art Conventionally, in a vertical power MOSFET, a bondable gate electrode and a source electrode are provided on the front surface, and a drain electrode is formed on the back surface. The drain electrode is formed by forming a bonding metal film on the entire back surface of the chip in consideration of electrical bonding and heat radiation characteristics.
【０００３】縦型パワーＭＯＳＦＥＴはこのような構造
をとるため、ウエハ上では全チップに対して共通にドレ
イン電極が形成されている。この結果、ウエハの状態で
各チップ毎に縦型パワーＭＯＳＦＥＴの動作特性を測定
すると、全面のドレイン電極の電圧降下、ドレインフォ
ーシング平板の電圧降下のために、各チップ毎の特性を
正確に測定することが困難である。Since the vertical power MOSFET has such a structure, a drain electrode is commonly formed on all chips on a wafer. As a result, when the operating characteristics of the vertical power MOSFET are measured for each chip in the wafer state, the characteristics of each chip are accurately measured due to the voltage drop of the drain electrode on the entire surface and the voltage drop of the drain forcing plate. Is difficult to do.
【０００４】[0004]
【発明が解決しようとする課題】従って、従来の測定方
法では、ウエハの状態で各チップ毎に動作特性を正確に
測定することが困難であるために、各チップ毎にダイシ
ングし、モールドした後に、各トランジスタ毎に動作特
性を測定していた。このため、素子の検査効率や素子の
製造効率が悪いという問題がある。Therefore, in the conventional measuring method, it is difficult to accurately measure the operating characteristics of each chip in a wafer state. Therefore, after dicing and molding each chip, The operating characteristics of each transistor were measured. For this reason, there is a problem that the inspection efficiency of the element and the manufacturing efficiency of the element are poor.
【０００５】又、ウエハの状態であえて測定するとする
と、大電流を流して測定するような場合には、上記の電
圧降下が大きく、各素子の動作特性が正確に測定でき
ず、結局、各素子の設計上のマージンを大きくとる必要
があり、チップ肥大化によるコスト上昇を招いていた。If the measurement is made in the state of a wafer, when a large current is applied, the above-mentioned voltage drop is large and the operating characteristics of each element cannot be measured accurately. In this case, it is necessary to increase a design margin, which leads to an increase in cost due to an enlarged chip.
【０００６】本発明は上記の課題を解決するために成さ
れたものであり、その目的は縦型トランジスタの動作特
性をウエハの状態で正確に測定できるようにすることで
ある。SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to enable the operating characteristics of a vertical transistor to be accurately measured in a wafer state.
【０００７】[0007]
【課題を解決するための手段】上記課題を解決するため
の発明の構成は、表面にゲート電極及びソース電極、裏
面にドレイン電極を有する縦型トランジスタの特性を測
定する方法において、縦型トランジスタのパターンが各
チップに形成され、各チップ共通にドレイン電極が形成
されたウエハにおいて、ウエハ表面の各チップに、ドレ
インに接続される検出電極を形成し、チップのゲート電
極とソース電極間に所定の制御電圧を印加し、ソース電
極とドレイン電極間に定電流を流し、チップのソース電
極と検出電極間のソース検出電極間電圧を測定し、定電
流とソース検出電極間電圧とから各チップの縦型トラン
ジスタの特性をウエハの状態で測定することを特徴とす
る。又、請求項２に記載の発明は、定電流は、ソース電
極とドレイン電極とに端子を接続して電流を流す定電流
源により供給され、ソース検出電極間電圧は、ソース電
極と検出電極とに端子を接続して端子間の電圧を検出す
るセンシング回路により検出されることを特徴とする。SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for measuring the characteristics of a vertical transistor having a gate electrode and a source electrode on the front surface and a drain electrode on the back surface. On a wafer in which a pattern is formed on each chip and a drain electrode is commonly formed on each chip, a detection electrode connected to the drain is formed on each chip on the wafer surface, and a predetermined electrode is provided between the gate electrode and the source electrode of the chip. A control voltage is applied, a constant current flows between the source electrode and the drain electrode, and a voltage between the source and detection electrodes between the source electrode and the detection electrode of the chip is measured. The characteristics of the type transistor are measured in a state of a wafer. According to the second aspect of the present invention, the constant current is a constant current in which a terminal is connected to a source electrode and a drain electrode to flow a current.
The voltage supplied between the source and the source detection electrode is detected by a sensing circuit that connects terminals to the source electrode and the detection electrode and detects a voltage between the terminals.
【０００８】[0008]
【作用及び発明の効果】上記の検出電極は各チップ毎に
分離しており、各チップのドレインに接続されているの
で、ドレインの電位を精度良く検出できる。又、ソース
電極とゲート電極間に制御電圧を印加して、ソース電極
とドレイン電極間に定電流を流して、その時のソース、
ドレイン間のソースドレイン間電圧を、ソース電極と検
出電極間のソース検出電極間電圧で検出している。よっ
て、検出電極により各チップ個別にドレインの電位を検
出できるためウエハの状態で各チップの動作特性を個別
に測定することができる。又、定電流の流入及び流出の
給電リードとは別に電圧検出リードを設けて電圧を検出
していることから、トランジスタの動作特性が正確に検
出できる。The detection electrode is separated for each chip and connected to the drain of each chip, so that the potential of the drain can be detected with high accuracy. In addition, a control voltage is applied between the source electrode and the gate electrode, and a constant current flows between the source electrode and the drain electrode.
The source-drain voltage between the drains is detected by the source-detection electrode voltage between the source electrode and the detection electrode. Therefore, the potential of the drain can be individually detected by the detection electrode, so that the operating characteristics of each chip can be individually measured in the state of the wafer. Further, since the voltage is detected by providing the voltage detection lead separately from the power supply lead for inflow and outflow of the constant current, the operating characteristics of the transistor can be accurately detected.
【０００９】このように、各トランジスタの動作特性が
ウエハの状態で測定できることから、検査効率が高く、
トランジスタの製造効率も高くなる。As described above, since the operating characteristics of each transistor can be measured in the state of the wafer, the inspection efficiency is high,
The manufacturing efficiency of the transistor is also increased.
【００１０】[0010]
【実施例】図２は、本発明の一実施例である半導体装置
が形成されたウエハ２の平面図、図３は、図２中の半導
体装置１チップの部分斜視図である。図３に示すように
本発明の一実施例である縦型ＤＭＯＳトランジスタ（Ｖ
ＤＭＯＳ）１は、シリコンウエハ２上に形成される。そ
のＶＤＭＯＳは、図３に示すように外部接続用としてド
レイン電極３、ソースボンディングパッド（ソース電
極）４、ゲートボンディングパッド（ゲート電極）５を
備えており、ドレイン電極３と等電位の出力がドレイン
センシング配線７を介してドレインセンシングパッド
（検出電極）６から電気的に取り出されるようになって
いる。FIG. 2 is a plan view of a wafer 2 on which a semiconductor device according to an embodiment of the present invention is formed, and FIG. 3 is a partial perspective view of one chip of the semiconductor device in FIG. As shown in FIG. 3, a vertical DMOS transistor (V
The DMOS 1 is formed on a silicon wafer 2. The VDMOS includes a drain electrode 3, a source bonding pad (source electrode) 4, and a gate bonding pad (gate electrode) 5 for external connection as shown in FIG. It is electrically extracted from the drain sensing pad (detection electrode) 6 through the sensing wiring 7.
【００１１】次に、図３のＶＤＭＯＳの断面構造図を図
１に示す。図１に示すように本発明に係る半導体装置
は、Ｎ- エピタキシャル層８が形成されたＮ型シリコン
基板９を用いシリコン酸化膜10a を介してＰ- チャネル
領域11及びＮ+ ソース領域12を２重拡散形成したＶＤＭ
ＯＳトランジスタ部Ａ、エピタキシャル層８上のシリコ
ン酸化膜10a にリンドープポリシリコン膜１３を堆積し
アルミニウム金属皮膜14を形成したゲート電極部Ｂ、シ
リコン基板９に外部接続用金属皮膜17を形成したドレイ
ン電極部Ｃ１、及びＶＤＭＯＳトランジスタのＮ+ ソー
ス領域11を形成時に選択的にシリコン基板エピタキシャ
ル層８にＮ+ 拡散領域15を形成しドレイン電位と等電位
としたドレインセンシング部Ｃ２から構成される。ま
た、ドレインセンシング部Ｃ２は、外部からプローブピ
ン等を接触させドレイン電位が測定出来るように絶縁保
護膜16を除去したプロービングパッド構造となる。Next, FIG. 1 shows a sectional structural view of the VDMOS of FIG. The semiconductor device according to the present invention as shown in FIG. 1, N - P through the silicon oxide film 10a using N-type silicon substrate 9 on which the epitaxial layer 8 is formed - a channel region 11 and the N + source region 12 2 VDM formed with double diffusion
OS transistor section A, gate electrode section B in which phosphorus-doped polysilicon film 13 is deposited on silicon oxide film 10a on epitaxial layer 8 to form aluminum metal film 14, and drain in which metal film 17 for external connection is formed on silicon substrate 9 It comprises an electrode portion C1 and a drain sensing portion C2 in which an N + diffusion region 15 is selectively formed in the silicon substrate epitaxial layer 8 when the N + source region 11 of the VDMOS transistor is formed to make the drain potential equal to the drain potential. Further, the drain sensing part C2 has a probing pad structure in which the insulating protective film 16 is removed so that a probe pin or the like can be contacted from the outside to measure the drain potential.
【００１２】次に、前記構成に係るＶＤＭＯＳをウエハ
状態で１チップのオン抵抗を測定する際の測定方法を示
した構造図を図４に示し、オン抵抗測定の等価回路図を
図５に示し、測定方法について説明する。Next, FIG. 4 is a structural diagram showing a measuring method for measuring the on-resistance of one chip in the VDMOS according to the above configuration in a wafer state, and FIG. 5 is an equivalent circuit diagram of the on-resistance measurement. The measurement method will be described.
【００１３】この測定方法に使用される測定装置18は定
電流源としてのフォーシング用定電流源19、ゲート信号
用定電圧源20および電圧計21を備えており、定電流源19
にはＶＤＭＯＳウエハ２のドレイン電極３と面接触させ
るためのフォーシングステージ22Ａ及びソース電極４と
プロービングするためのソースフォーシングピン22Ｂ
が、電圧計21にはドレインセンシングピン23Ａ及びソー
スセンシングピン23Ｂがそれぞれ電気的に接続されてい
る。The measuring device 18 used in this measuring method is fixed.
Forcing constant current source 19 as a current source includes a constant voltage source 20 and a voltmeter 21 for the gate signal, the constant current source 19
Forcing stage 22A for making surface contact with drain electrode 3 of VDMOS wafer 2 and source forcing pin 22B for probing with source electrode 4
However, the voltmeter 21 is electrically connected to a drain sensing pin 23A and a source sensing pin 23B.
【００１４】一方、ゲート信号用定電圧源20には、ソー
ス基準電位としてゲートに定電圧信号を印加するため、
電源20の負極は、ソースのフォーシング線３１及びセン
シング線３２に、正極はゲート電極５をプロービングす
るため、ゲートフォーシングピン24及びセンシングピン
25に電気的に接続される。On the other hand, a constant voltage signal is applied to the gate as a source reference potential to the gate signal constant voltage source 20.
The negative electrode of the power source 20 is connected to the source forcing line 31 and the sensing line 32, and the positive electrode is used to probe the gate electrode 5, so that the gate forcing pin 24 and the sensing pin
It is electrically connected to 25.
【００１５】測定に際して、ＶＤＭＯＳウエハ２がドレ
インフォーシングステージ22Ａの上にセットされると、
ソース電極４にソースフォーシングピン22Ｂ及びソース
センシングピン23Ｂが、ゲート電極５にゲートフォーシ
ングピン24及びゲートセンシングピン25が、ドレインセ
ンシング電極６にドレインセンシングピン23Ａがそれぞ
れ接触される。これにより、各測定用ピンとＶＤＭＯＳ
１の電極が電気的に接続されることになる。In the measurement, when the VDMOS wafer 2 is set on the drain forcing stage 22A,
The source electrode 4 is in contact with the source forcing pin 22B and the source sensing pin 23B, the gate electrode 5 is in contact with the gate forcing pin 24 and the gate sensing pin 25, and the drain sensing electrode 6 is in contact with the drain sensing pin 23A. This allows each measurement pin and VDMOS
One electrode will be electrically connected.
【００１６】続いて、測定装置18のゲート信号用電源20
よりＶＤＭＯＳ１（図５ではｎチャネルＤＭＯＳ）のチ
ャネルをオンさせるために十分な電圧をゲートフォーシ
ングピン24及びセンシングピン25を通じて供給し、フォ
ーシング用定電流源19により大電流をＶＤＭＯＳ１のド
レイン電極３〜ソース電極４間にドレインフォーシング
ステージ22Ａ及びソースフォーシングピン22Ｂを通じて
供給する。同時に、測定装置18の電圧計21によりＶＤＭ
ＯＳ１のオン電圧が次式(1) により測定される。Subsequently, the power source 20 for the gate signal of the measuring device 18
A voltage sufficient to turn on the channel of the VDMOS 1 (n-channel DMOS in FIG. 5) is supplied through the gate forcing pin 24 and the sensing pin 25, and a large current is supplied by the forcing constant current source 19 to the drain electrode 3 of the VDMOS 1. To source electrode 4 through drain forcing stage 22A and source forcing pin 22B. At the same time, the voltmeter 21 of the measuring device 18
The ON voltage of OS1 is measured by the following equation (1).
【００１７】[0017]
【数１】 ＶON＝ＩDS×（ＲON＋ＲD ＋ＲS ）・・・・(1)## EQU1 ## V ON = I DS × (R ON + R D + R S ) (1)
【００１８】(1) 式中、ＶONはドレイン電極３〜ソース
電極４間の電圧降下、ＩDSはドレイン電極３〜ソース電
極４間電流、ＲONはＶＤＭＯＳ１のオン抵抗、ＲD はド
レイン電極３とドレインフォーシングステージ22Ａとの
間の接触抵抗、ＲS はソース電極４とソースフォーシン
グピン22Ｂとの間の接触抵抗である。In the equation (1), V ON is a voltage drop between the drain electrode 3 and the source electrode 4, I DS is a current between the drain electrode 3 and the source electrode 4, R ON is the ON resistance of the VDMOS 1, and RD is a drain electrode. 3 and the contact resistance between the drain forcing stage 22A, R S is the contact resistance between the source electrode 4 and the source forcing pin 22B.
【００１９】このとき、大電流が通電されるフォーシン
グ用測定子22Ａ、22Ｂとドレイン電極３、ソース電極４
の接触面間には、接触抵抗26Ａ、26Ｂがそれぞれ作用す
るが、ドレインセンシングピン23Ａとドレインセンシン
グ電極６との接触部分、及び、ソースセンシングピン23
Ｂとソース電極４との接触部分には大電流が通電される
わけではないため、接触抵抗の影響は作用しない。その
結果、ドレイン電極３〜ソース電極４間の電圧降下が、
式(1) において、接触抵抗ＲD 、ＲS に影響されないで
測定出来るため、ドレイン電極３〜ソース電極４間のオ
ン抵抗ＲONは正確に測定されることになる。At this time, the forcing tracing styluses 22A and 22B to which a large current is applied, the drain electrode 3, and the source electrode 4
Contact resistances 26A and 26B respectively act between the contact surfaces of the drain sensing pin 23A and the drain sensing electrode 6, and the source sensing pin 23A.
Since a large current does not flow through the contact portion between B and the source electrode 4, the influence of the contact resistance does not act. As a result, the voltage drop between the drain electrode 3 and the source electrode 4 becomes
In the equation (1), since the measurement can be performed without being affected by the contact resistances R D and R S , the on-resistance R ON between the drain electrode 3 and the source electrode 4 can be accurately measured.
【００２０】ＶＤＭＯＳの各チップにドレインセンシン
グ電極を設けることにより、オン抵抗等の測定時におい
て、ドレイン、ソース両電極について、フォーシング電
極にフォーシング用測定ピンを、センシング電極にセン
シング用測定ピンをそれぞれ接触されることができるた
め、フォーシング電極部に大電流を通電させながら、セ
ンシング用測定ピンにより大電流印加部から独立して電
気的測定を実行することができる。その結果、大電流通
電による接触抵抗の測定値中への影響を抑制することが
出来るため、ウエハ状態でＶＤＭＯＳの電気的特性を正
確に測定することが出来る。By providing a drain sensing electrode on each VDMOS chip, when measuring on-resistance, etc., for both the drain and source electrodes, a forcing measurement pin is used as a forcing electrode and a sensing measurement pin is used as a sensing electrode. Since they can be contacted with each other, electrical measurement can be performed independently of the large current application unit by the sensing measurement pin while applying a large current to the forcing electrode unit. As a result, it is possible to suppress the influence of a large current flow on the measured contact resistance, so that the electrical characteristics of the VDMOS can be accurately measured in a wafer state.
【００２１】又、ドレインセンシング電極６の大きさ
は、大電流を流さないので電極６に先端径φ50μｍ程度
のプローブピンが電気的に接続できる広さであれば十分
であり、φ100 μｍ程度しか必要ない。このため、デバ
イスサイズの拡大によるコスト高騰を招くことなく、高
価な特殊測定装置を使用しなくても現有測定設備を流用
可能である。The size of the drain sensing electrode 6 is sufficient if a probe pin having a tip diameter of about 50 μm can be electrically connected to the electrode 6 because a large current does not flow, and only about 100 μm is required. Absent. For this reason, the existing measuring equipment can be diverted without using an expensive special measuring device without increasing the cost due to an increase in the device size.
【００２２】又、本発明の測定方法によれば、パワーＭ
ＯＳＦＥＴ（ＶＤＭＯＳ）のオン抵抗のような電気的特
性を正確に測定することができる。このため、余分な電
気的特性マージンの増大を防止することが可能であるの
でＶＤＭＯＳのチップサイズを設計仕様内の最小サイズ
にできる。さらに、ウエハ状態でＶＤＭＯＳの電気特性
を完全に測定可能であるため、そのＶＤＭＯＳ素子を使
用する製品への不良持ち込みを無くすることが出来る。According to the measuring method of the present invention, the power M
Electrical characteristics such as the on-resistance of the OSFET (VDMOS) can be accurately measured. For this reason, it is possible to prevent an extra increase in the margin of the electrical characteristics, so that the chip size of the VDMOS can be made the minimum size within the design specifications. Further, since the electrical characteristics of the VDMOS can be completely measured in the wafer state, it is possible to eliminate the failure to bring the VDMOS element into a product using the VDMOS element.
【００２３】上記の実測例は、図５の等価回路に示すよ
うに、ｎチャネルＶＤＭＯＳについて具体的に説明した
が、ウエハ内のＶＤＭＯＳの各チップにおいて、ドレイ
ンセンシング電極６を備えていれば、ｐチャネルのＶＤ
ＭＯＳについてもゲートに印加する信号レベルを変更す
るだけで、同様にオン抵抗等電気特性を正確に測定可能
である。又、測定する電気特性は、ＶＤＭＯＳのオン抵
抗に限定されない。In the above-described actual measurement example, the n-channel VDMOS is specifically described as shown in the equivalent circuit of FIG. 5, but if each VDMOS chip in the wafer has the drain sensing electrode 6, p-channel VDMOS can be used. VD of channel
Similarly, the electrical characteristics such as the on-resistance can be accurately measured only by changing the signal level applied to the gate of the MOS. Further, the electrical characteristics to be measured are not limited to the ON resistance of the VDMOS.
【図１】本発明の具体的な実施例方法で用いられるウエ
ハに形成された測定対象の縦型トランジスタの構成図。FIG. 1 is a configuration diagram of a vertical transistor to be measured formed on a wafer used in a specific embodiment method of the present invention.
【図２】同実施例のウエハの平面図。FIG. 2 is a plan view of the wafer of the embodiment.
【図３】同実施例のウエハの１つのチップの構成を示し
た構成図。FIG. 3 is a configuration diagram showing a configuration of one chip of the wafer of the embodiment.
【図４】同実施例の測定方法を実現するための装置構成
を示した構成図。FIG. 4 is a configuration diagram showing an apparatus configuration for realizing the measurement method of the embodiment.
【図５】同実施例の測定方法を実現するための回路構成
を示した回路図。FIG. 5 is a circuit diagram showing a circuit configuration for realizing the measuring method of the embodiment.
１…縦型ＤＭＯＳトランジスタ ２…シリコンウエハ ３…ドレイン電極 ４…ソースボンディングパッド（ソース電極） ５…ゲートボンディングパッド（ゲート電極） ６…ドレインセンシングパッド（検出電極） ８…Ｎ- エピタキシャル層 ９…シリコン基板DESCRIPTION OF SYMBOLS 1 ... Vertical DMOS transistor 2 ... Silicon wafer 3 ... Drain electrode 4 ... Source bonding pad (source electrode) 5 ... Gate bonding pad (gate electrode) 6 ... Drain sensing pad (detection electrode) 8 ... N - epitaxial layer 9 ... Silicon substrate
Claims (2)
にドレイン電極を有する縦型トランジスタの特性を測定
する方法において、 前記縦型トランジスタのパターンが各チップに形成さ
れ、各チップ共通にドレイン電極が形成されたウエハに
おいて、ウエハ表面の各チップに、ドレインに接続され
る検出電極を形成し、 前記チップの前記ゲート電極と前記ソース電極間に所定
の制御電圧を印加し、前記ソース電極と前記ドレイン電
極間に定電流を流し、 前記チップの前記ソース電極と前記検出電極間のソース
検出電極間電圧を測定し、 前記定電流と前記ソース検出電極間電圧とから前記各チ
ップの前記縦型トランジスタの特性をウエハの状態で測
定することを特徴とする縦型トランジスタの特性測定方
法。1. A method for measuring characteristics of a vertical transistor having a gate electrode and a source electrode on a front surface and a drain electrode on a back surface, wherein a pattern of the vertical transistor is formed on each chip, and a drain electrode is commonly used on each chip. In the formed wafer, a detection electrode connected to a drain is formed on each chip on the wafer surface, a predetermined control voltage is applied between the gate electrode and the source electrode of the chip, and the source electrode and the drain Flowing a constant current between the electrodes, measuring a voltage between the source detection electrodes between the source electrode and the detection electrode of the chip, and measuring the voltage of the vertical transistor of each chip from the constant current and the voltage between the source detection electrodes. A method for measuring characteristics of a vertical transistor, wherein characteristics are measured in a state of a wafer.
レイン電極とに端子を接続して電流を流す定電流源によ
り供給され、前記ソース検出電極間電圧は、前記ソース
電極と前記検出電極とに端子を接続して端子間の電圧を
検出するセンシング回路により検出されることを特徴と
する請求項１に記載の縦型半導体装置の特性測定方法。2. The constant current source is supplied by a constant current source that supplies a current by connecting a terminal to the source electrode and the drain electrode, and the voltage between the source detection electrodes is the source current. The method for measuring characteristics of a vertical semiconductor device according to claim 1, wherein the sensing is performed by a sensing circuit that connects a terminal to the electrode and the detection electrode and detects a voltage between the terminals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6058204A JP2858390B2 (en) | 1994-03-02 | 1994-03-02 | Method for measuring characteristics of vertical semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6058204A JP2858390B2 (en) | 1994-03-02 | 1994-03-02 | Method for measuring characteristics of vertical semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH07245401A JPH07245401A (en) | 1995-09-19 |
| JP2858390B2 true JP2858390B2 (en) | 1999-02-17 |
Family
ID=13077513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6058204A Expired - Fee Related JP2858390B2 (en) | 1994-03-02 | 1994-03-02 | Method for measuring characteristics of vertical semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2858390B2 (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006184136A (en) * | 2004-12-28 | 2006-07-13 | Aitesu:Kk | Semiconductor analyzer and its method |
| JP2009164288A (en) * | 2007-12-28 | 2009-07-23 | Sanken Electric Co Ltd | Semiconductor element and semiconductor device |
| JP5656422B2 (en) * | 2010-03-11 | 2015-01-21 | 三菱電機株式会社 | Measuring method |
| CN103187398B (en) * | 2011-12-30 | 2015-12-16 | 中芯国际集成电路制造(上海)有限公司 | Silicon through hole detection architecture and detection method |
| US11041900B2 (en) | 2014-03-26 | 2021-06-22 | Teradyne, Inc. | Equi-resistant probe distribution for high-accuracy voltage measurements at the wafer level |
| US10698020B2 (en) | 2014-03-26 | 2020-06-30 | Teradyne, Inc. | Current regulation for accurate and low-cost voltage measurements at the wafer level |
| US9768085B1 (en) | 2016-07-25 | 2017-09-19 | International Business Machines Corporation | Top contact resistance measurement in vertical FETs |
| WO2018150555A1 (en) | 2017-02-20 | 2018-08-23 | 新電元工業株式会社 | Electronic device and connector |
| US11024738B2 (en) | 2019-03-13 | 2021-06-01 | International Business Machines Corporation | Measurement of top contact resistance in vertical field-effect transistor devices |
| DE102022210851A1 (en) | 2022-10-14 | 2024-04-25 | Robert Bosch Gesellschaft mit beschränkter Haftung | Vertical semiconductor device based on gallium nitride with front-side measuring electrode |
-
1994
- 1994-03-02 JP JP6058204A patent/JP2858390B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07245401A (en) | 1995-09-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100940415B1 (en) | On resistance test method for back-side-drain wafer | |
| JP2858390B2 (en) | Method for measuring characteristics of vertical semiconductor device | |
| US5034796A (en) | Simplified current sensing structure for MOS power devices | |
| US5760600A (en) | Test device for insulated-gate field effect transistor and testing circuit and testing method using the same | |
| US8108175B2 (en) | Method for determining self-heating free I-V characterstics of a transistor | |
| JP3277914B2 (en) | Integrated circuit device having a process parameter measuring circuit | |
| US7263759B2 (en) | Methods of manufacturing and testing bonding wires | |
| JPS5952860A (en) | Semiconductor integrated circuit device | |
| JPH08153763A (en) | Method for measuring semiconductor device | |
| KR100396344B1 (en) | Monitoring resistor element and measuring method of relative preciseness of resistor elements | |
| JPH11297782A (en) | Testing circuit | |
| JP3093216B2 (en) | Semiconductor device and inspection method thereof | |
| JPH04188643A (en) | Semiconductor integrated circuit | |
| US20240302427A1 (en) | Test system and test device | |
| JPH04217341A (en) | Semiconductor integrated circuit device | |
| US9410921B2 (en) | Method for testing a CMOS transistor | |
| JPH0883830A (en) | Inspecting method of insulated-separated type semiconductor device, and insulated-separated type semiconductor device | |
| JP3425330B2 (en) | Semiconductor device | |
| JP2548160B2 (en) | Semiconductor device | |
| JP2968642B2 (en) | Integrated circuit device | |
| JPH02166748A (en) | Inspection circuit for temperature | |
| JPH0582652A (en) | Semiconductor integrated circuit device | |
| JPH0614539B2 (en) | Method for manufacturing semiconductor integrated circuit device | |
| JP3250215B2 (en) | Method and apparatus for evaluating plasma non-uniformity | |
| JPH09326473A (en) | Voltage monitor circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20071204 Year of fee payment: 9 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101204 Year of fee payment: 12 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111204 Year of fee payment: 13 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121204 Year of fee payment: 14 |
|
| LAPS | Cancellation because of no payment of annual fees |