JP5656422B2 - Measuring method - Google Patents

Description

  The present invention relates to a semiconductor device and a measurement method, and more particularly to a semiconductor device including a channel stopper region outside an element formation region and a method for measuring characteristics of the semiconductor device.

  Conventionally, as a kind of semiconductor device, a high-breakdown-voltage type semiconductor element such as an insulated gate bipolar transistor (IGBT) is known (for example, Japanese Patent Laid-Open No. 2000-269520 (hereinafter referred to as “Patent Document 1”). And Japanese Patent Laid-Open No. 2000-208768 (hereinafter referred to as “Patent Document 2”). Patent Documents 1 and 2 disclose a high voltage semiconductor device having a channel stopper region, and Patent Document 2 discloses an auxiliary electrode connected to the channel stopper region.

JP 2000-269520 A JP 2000-208768 A

  However, a passivation film is usually formed on these channel stopper regions, and the auxiliary electrode of Patent Document 2 is also covered with the passivation film. Further, conventionally, an equipotential conductor (equipotential ring) connected to the channel stopper region may be formed. However, the width of such an equipotential conductor is relatively narrow, and even when a passivation film is not formed, the measuring needle or the measuring pin is brought into contact with the surface of such an equipotential conductor. It was often difficult. For this reason, in order to confirm the electrical characteristics of the diode (the back side PN junction) included in the IGBT, which is an example of a high voltage semiconductor device, conventionally, processing such as cutting an element such as an IGBT is performed. In addition, it was necessary to bring the measuring needle into contact with a predetermined position. In other words, it is difficult for conventional elements such as IGBTs to confirm the electrical characteristics of only the diode part directly and simply without destroying the element.

  For this reason, for example, when applying a new substrate or applying a new process apparatus, there is a problem that it takes time to adjust characteristics of a device to be formed.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a semiconductor device capable of directly and simply measuring the electrical characteristics of the included diode and the semiconductor. It is to provide a measurement method for the device.

A semiconductor device according to the present invention includes a semiconductor substrate, a guard ring, a channel stopper region, an equipotential conductor, and a back electrode. The semiconductor substrate has a main surface and an element formation region on the main surface. The guard ring is formed on the main surface of the semiconductor substrate so as to surround the element formation region in plan view. The channel stopper region is formed on the main surface of the semiconductor substrate so as to be positioned on the outer peripheral side of the guard ring. The equipotential conductor is formed on the main surface of the semiconductor substrate and is electrically connected to the channel stopper region. The back electrode is formed on the back surface opposite to the main surface in the semiconductor substrate. The semiconductor substrate has a first conductivity type region and a second conductivity type.
And a conductive type region. The first conductivity type region is electrically connected to the back electrode, and the conductivity type is the first conductivity type. The second conductivity type region is in direct contact with the first conductivity type region, the second conductivity type is different from the first conductivity type, and is in direct contact with the channel stopper region. The equipotential conductor includes a measurement electrode portion. Furthermore, the semiconductor device includes a coating film that covers at least the equipotential conductor. An opening that exposes a part of the surface of the equipotential conductor is formed in the coating film. The equipotential conductor includes an extending portion that extends to the surface of the coating film through the opening. The measurement electrode part includes an extension part. The extending portion extends to a region located above the guard ring on the surface of the coating film.
A method for measuring a semiconductor device according to the present invention is a method for measuring characteristics of a semiconductor device that is an insulated gate bipolar transistor, and the semiconductor device has the above-described configuration. The measurement method includes a step of electrically connecting a collector electrode of a measurement insulated gate bipolar transistor to a back electrode of a semiconductor device, and connecting an inductive load between the back electrode and the measurement electrode unit. Current flowing through the first conductivity type region and the second conductivity type region of the semiconductor device when a plurality of pulse voltages are input between the gate electrode and the emitter electrode of the measurement insulated gate bipolar transistor Measuring the electrical characteristics of the PN junction formed at the contact portion between the first conductivity type region and the second conductivity type region by measuring the value.

  According to the present invention, the electrical characteristics of the PN junction (PN diode) formed at the contact portion between the first conductivity type region and the second conductivity type region are directly and directly measured using the back electrode and the measurement electrode portion. It can be easily measured.

1 is a schematic cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. FIG. 2 is a schematic plan view of the semiconductor device shown in FIG. 1. FIG. 3 is an equivalent circuit diagram of the semiconductor device shown in FIGS. 1 and 2. FIG. 7 is a schematic plan view illustrating a first modification of the semiconductor device illustrated in FIGS. 1 to 3. FIG. 10 is a schematic plan view illustrating a second modification of the semiconductor device illustrated in FIGS. 1 to 3. FIG. 10 is a schematic plan view illustrating a third modification of the semiconductor device illustrated in FIGS. 1 to 3. It is a circuit diagram for demonstrating the measuring method by this invention. It is a cross-sectional schematic diagram which shows Embodiment 2 of the semiconductor device by this invention. FIG. 9 is a schematic plan view of the semiconductor device shown in FIG. 8. FIG. 10 is a schematic plan view illustrating a modification of the semiconductor device illustrated in FIGS. 8 and 9.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
A first embodiment of a semiconductor device according to the present invention will be described with reference to FIGS.

  Referring to FIGS. 1 and 2, the semiconductor device according to the present invention is an insulated gate bipolar transistor (IGBT) having a substantially square shape as shown in FIG. An element formation region 1 in which is formed is disposed. A chip termination region 2 is arranged so as to surround the element formation region 1. In the chip termination region 2, a guard ring 12 and an equipotential aluminum 13 electrically connected to the guard ring 12 and positioned on the guard ring 12 are disposed so as to surround the element formation region 1. A channel stopper region 14 is formed on the outer peripheral side of the guard ring 12 so as to surround the guard ring 12. An equipotential aluminum 15 connected to the channel stopper region 14 and disposed on the channel stopper region 14 is also formed so as to surround the guard ring 12.

The above-described guard ring 12, channel stopper region 14, and conductive regions of functional elements in the element formation region 1 are formed on the main surface of the semiconductor substrate. Here, as shown in FIG. 1, the semiconductor substrate includes a p ⁺ layer 7 having a p-type conductivity and an n ⁻ layer 6 having an n-type conductivity formed on the p ⁺ layer 7. Is done. That is, in the chip termination region 2, the guard ring 12 and the channel stopper region 14 are formed on the surface of the n ⁻ layer 6.

In the semiconductor device shown in FIGS. 1 and 2, an insulated gate bipolar transistor (IGBT) as a functional element is formed in the element formation region. Specifically, a p ⁺ layer 5 that is a channel dope layer is formed in the element formation region 1 on the surface of the n ⁻ layer 6. The surface layer of the p ⁺ layer 5, n ⁺ layer 4 spaced apart from the outer end of the p ⁺ layer 5 is formed. A gate electrode 9 is formed on the region between the n ⁺ layer 4 and the outer peripheral edge of the p ⁺ layer 5 via an oxide film 10 which is an insulating film. As shown in FIG. 1, the side surface and the upper surface of the gate electrode 9 are also covered with the oxide film 10. Emitter electrode 3 is formed so as to be in contact with the surface of n ⁺ layer 4. A collector electrode 8 is formed on the back side of the semiconductor substrate (the back side of the p ⁺ layer 7).

In the chip termination region 2, an oxide film 10 that is an insulating film is formed on the surface of the n ⁻ layer 6 so as to cover the guard ring 12. In the oxide film 10, an opening is formed in a region located on the guard ring 12. Equipotential aluminum 13 that is electrically connected to the guard ring 12 is formed so as to fill the inside of the opening and extend to the top of the oxide film 10. The equipotential aluminum 13 is formed along the guard ring 12 so as to go around the outer periphery of the element forming region 1 as shown in FIG. Further, the equipotential aluminum 15 is formed on the channel stopper region 14 located on the outer peripheral side of the guard ring 12 in a state of being electrically connected to the channel stopper region 14 as described above. The equipotential aluminum 15 is also formed so as to surround the outer periphery of the element formation region 1 along the channel stopper region 14 as shown in FIG.

  Then, a passivation film 11 as a coating film is formed so as to cover the oxide film 10 and the equipotential aluminums 13 and 15. In the passivation film 11, an opening 17 is formed so as to expose a part of the surface of the equipotential aluminum 15 located on the channel stopper region 14. A portion of the surface of the equipotential aluminum 15 exposed in the opening 17 is a channel stopper electrode 16. As shown in FIG. 2, the channel stopper electrode 16 is formed in the vicinity of the corner of the semiconductor device when the semiconductor device is viewed in plan. In this way, since the channel stopper electrode 16 can be disposed at the bent portion of the equipotential aluminum 15, the area of the channel stopper electrode 16 (that is, the opening area of the opening 17) can be easily increased.

Referring to the equivalent circuit diagram shown in FIG. 3, the junction between p ⁺ layer 7 and n ⁻ layer 6 on the back side of the semiconductor substrate functions as a so-called PN diode. The channel stopper electrode 16 is electrically connected to the n ⁻ layer 6 side of the PN diode. The collector electrode 8 is connected to the p ⁺ layer 7 side of the PN diode. Therefore, the characteristics of the PN diode can be directly confirmed using the collector electrode 8 and the channel stopper electrode 16 as will be described later.

  Note that the preparation of the semiconductor substrate, the formation of the IGBT, and the formation of the passivation film 11 can be performed using a conventionally known method for manufacturing a semiconductor device. For example, the following method can be used as a method of forming the opening 17 in the passivation film 11. That is, first, a resist pattern having an opening pattern corresponding to the opening 17 is formed on the passivation film 11 using photolithography. Then, the passivation film 11 is partially removed by etching using the resist pattern as a mask.

  Next, a first modification of the first embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 4 corresponds to FIG.

  The semiconductor device shown in FIG. 4 basically has the same structure as the semiconductor device shown in FIGS. 1 to 3, but the planar shapes of the opening 17 and the channel stopper electrode 16 are different. Specifically, in the semiconductor device shown in FIG. 4, the planar shapes of the channel stopper electrode 16 and the opening 17 are triangular. Even in such a case, the same effect as the semiconductor device shown in FIGS. 1 to 3 can be obtained. In addition, by making the planar shape of the channel stopper electrode 16 and the opening 17 into such a triangular shape, the outer periphery of the channel stopper electrode 16 can be formed along the outer periphery of the planar shape of the semiconductor device. The surface area of can be increased.

  With reference to FIG. 5, a second modification of the first embodiment of the semiconductor device according to the present invention will be described. FIG. 5 corresponds to FIG.

  The semiconductor device shown in FIG. 5 basically has the same structure as the semiconductor device shown in FIGS. 1 to 3, but the number of channel stopper electrodes 16 and openings 17 are different. That is, in the semiconductor device shown in FIG. 5, two channel stopper electrodes 16 and two openings 17 are formed. In this way, one of the channel stopper electrodes 16 can be used as a force electrode for contacting the measuring needle or the measuring fin. The other channel stopper electrode 16 can be used as a sense pad electrode.

  The number of channel stopper electrodes 16 is not limited to two as shown in FIG. 5, but may be three or a plurality of four or more. In FIG. 5, two channel stopper electrodes 16 are arranged at point-symmetrical positions with the central portion of the semiconductor device in plan view as a center. However, the two channel stopper electrodes 16 are offset toward one end portion of the semiconductor device. A plurality of channel stopper electrodes 16 may be arranged.

  With reference to FIG. 6, a third modification of the first embodiment of the semiconductor device according to the present invention will be described. FIG. 6 corresponds to FIG.

  The semiconductor device shown in FIG. 6 is basically the same as the semiconductor device shown in FIG. 5, but the planar shape of the channel stopper electrode 16 is different. Specifically, in the semiconductor device shown in FIG. 6, the planar shape of the channel stopper electrode 16 is triangular. Further, two adjacent sides in the planar shape of the channel stopper electrode 16 are arranged so as to be substantially along the outer peripheral side of the semiconductor device as in the case of the semiconductor device shown in FIG. As a result, similarly to the semiconductor device shown in FIG. 4, the surface area of the channel stopper electrode 16 can be increased. Further, the same effect as the semiconductor device shown in FIG. 5 can be obtained.

  Next, a measurement method for measuring the characteristics of the semiconductor device according to the present invention will be described with reference to FIG.

  The measuring method according to the present invention is a method for measuring the characteristics of the semiconductor device according to the present invention shown in any of FIGS. Specifically, an inductive load 20 is connected between the collector electrode 8 and the channel stopper electrode 16 of the semiconductor device according to the present invention. Further, a collector electrode 22 of a measurement insulated gate bipolar transistor (IGBT) is connected to the collector electrode 8 of the semiconductor device according to the present invention. Then, the emitter electrode 23 of the measurement IGBT is grounded.

In this state, when a plurality of pulse voltages are input between the gate electrode and the emitter electrode 23 of the IGBT 21 for measurement, the current value flowing through the PN junction composed of the p ⁺ layer 7 and the n ⁻ layer 6 is measured. . As a result, the hole injection amount and the quality of the p ⁺ layer 7 in the semiconductor device according to the present invention can be determined.

Further, by measuring the forward voltage and breakdown voltage of the channel stopper electrode 16 and the collector electrode 8, the impurity concentration and thickness of the p ⁺ layer 7 can be confirmed.

(Embodiment 2)
A second embodiment of the semiconductor device according to the present invention will be described with reference to FIGS.

  The semiconductor device shown in FIGS. 8 and 9 basically has the same structure as the semiconductor device shown in FIGS. 1 to 3, but the structure of the channel stopper electrode 16 is different. Specifically, in the semiconductor device shown in FIGS. 8 and 9, the channel stopper electrode 16 is a conductor electrically connected to the equipotential aluminum 15 through the opening 17 formed in the passivation film 11. It is. The channel stopper electrode 16 is formed so as to protrude from the inside of the opening 17 toward the upper surface of the passivation film 11. From a different point of view, the channel stopper electrode 16 in the semiconductor device shown in FIGS. 8 and 9 is connected to the equipotential aluminum 15 and extends on the passivation film 11 so as to extend on the upper surface of the passivation film 11. The existing extension part 31 is included.

  Even with such a structure, the same effect as that of the semiconductor device shown in FIGS. 1 to 3 can be obtained. Further, in the semiconductor device shown in FIGS. 8 and 9, the planar shape and planar size of the channel stopper electrode 16 can be determined independently of the size of the opening 17. Therefore, for example, the channel stopper electrode 16 can be formed so as to extend to a region located above the guard ring 12 on the upper surface of the passivation film 11. As a result, the planar size of the channel stopper electrode 16 can be made sufficiently large. For this reason, workability | operativity when making a measurement terminal etc. contact the channel stopper electrode 16 can be improved.

  A modification of the second embodiment of the semiconductor device according to the present invention will be described with reference to FIG. FIG. 10 corresponds to FIG.

  Referring to FIG. 10, the semiconductor device basically has the same structure as the semiconductor device shown in FIGS. 8 and 9, except that two channel stopper electrodes 16 are formed. Specifically, in the semiconductor device shown in FIG. 10, two channel stopper electrodes 16 are formed at point-symmetrical positions around the central portion of the semiconductor device in plan view. The configuration of the two channel stopper electrodes 16 is basically the same. In this way, the same effect as that of the semiconductor device shown in FIG. 5 described above can be obtained.

  The planar shape of the channel stopper electrode 16 in the semiconductor device shown in FIGS. 8 to 10 is not limited to the quadrangular shape as illustrated, but may be any polygonal shape such as a triangular shape, a pentagon, or a hexagon. . Moreover, the measuring method as shown in FIG. 7 can also be implemented using the semiconductor device shown in FIGS.

  Here, although there is a part which overlaps with embodiment mentioned above, the characteristic structure of this invention is enumerated.

The semiconductor device according to the present invention includes a semiconductor substrate (n ⁻ layer 6 and p ⁻ layer 7), a guard ring 12, a channel stopper region 14, an equipotential conductor (equipotential aluminum 15), a back electrode ( Collector electrode 8). The semiconductor substrate has a main surface and has an element formation region 1 on the main surface. Guard ring 12 is formed on the main surface of the semiconductor substrate so as to surround element formation region 1 in plan view. The channel stopper region 14 is formed on the main surface of the semiconductor substrate so as to be positioned on the outer peripheral side of the guard ring 12. The equipotential aluminum 15 is formed on the main surface of the semiconductor substrate and is electrically connected to the channel stopper region 14. Collector electrode 8 is formed on the back surface of the semiconductor substrate opposite to the main surface. The semiconductor substrate includes a first conductivity type region (p ⁻ layer 7) and a second conductivity type region (n ⁻ layer 6). The first conductivity type region (p ⁻ layer 7) is electrically connected to the collector electrode 8, and the conductivity type is the first conductivity type (p type). The second conductivity type region (n ⁻ layer 6) is in direct contact with the first conductivity type region (p ⁻ layer 7) and is a second conductivity type (n type) different from the first conductivity type. Direct contact with the channel stopper region 14. The equipotential aluminum 15 includes a measurement electrode portion (channel stopper electrode 16).

In this way, the first conductivity type region (p) can be obtained without causing special processing or the like to the semiconductor device by causing the current to flow by bringing the measurement terminals into contact with the collector electrode 8 and the channel stopper electrode 16, respectively. The electrical characteristics of the PN junction (PN diode) formed at the contact portion between the ⁻ layer 7) and the second conductivity type region (n ⁻ layer 6) can be measured directly and simply. As a result, when the electrical characteristics of the semiconductor device need to be adjusted, the characteristics related to the PN diode of the semiconductor device can be directly measured, so that the adjustment operation can be performed easily and quickly.

  The semiconductor device may include a coating film (passivation film 11) that covers at least the equipotential aluminum 15, as shown in FIGS. An opening 17 that exposes a part of the surface of the equipotential aluminum 15 may be formed in the passivation film 11. The channel stopper electrode 16 may be a portion of the equipotential aluminum 15 exposed from the opening 17.

  In this case, by forming the opening 17 in the passivation film 11 positioned on the equipotential aluminum 15, the channel stopper electrode 16 can be easily formed by exposing a part of the surface of the equipotential aluminum 15. .

  As shown in FIGS. 8 to 10, the semiconductor device may include a coating film (passivation film 11) that covers at least the equipotential aluminum 15. An opening 17 that exposes a part of the surface of the equipotential aluminum 15 may be formed in the passivation film 11. The equipotential aluminum 15 may include an extending portion 31 that extends toward the surface of the passivation film 11 through the opening 17. The channel stopper electrode 16 may include an extending portion 31.

  In this case, since the extending portion 31 that functions as the channel stopper electrode 16 extends on the opening 17 of the passivation film 11, its planar shape is formed on the upper portion of the passivation film 11 independently of the size of the opening 17. Can be determined. Therefore, the extended portion 31 having a planar shape larger than the size of the opening 17 can be formed as the channel stopper electrode 16. As a result, the operation of bringing the measurement terminal into contact with the channel stopper electrode 16 can be easily performed.

  In the semiconductor device, the extending portion 31 covers a part of the surface of the passivation film 11 from the opening 17 toward the outside on the surface of the passivation film 11 as shown in FIGS. It may be formed. In this case, the channel stopper electrode 16 can be reliably made larger than the size of the opening 17.

  In the semiconductor device, the planar shape of the channel stopper electrode 16 may be an arbitrary polygonal shape such as a triangle, a quadrangle, or a pentagon in plan view. In this case, the planar shape of the channel stopper electrode 16 is adjusted so as to conform to the shape and size of the measurement terminal that contacts the channel stopper electrode 16 in measurement and the layout of other components (electrodes, etc.) of the semiconductor device. The degree of freedom can be increased.

  In the semiconductor device, the channel stopper electrode 16 may have a rectangular shape in plan view, and the vertical length and the horizontal length of the square shape may be 100 μm or more, respectively. In this case, the measurement terminal can be easily brought into contact with the channel stopper electrode 16.

  In the semiconductor device, the channel stopper electrode 16 may be formed at a plurality of locations in the equipotential aluminum 15 as shown in FIGS. In this case, measurement terminals can be connected to a plurality of locations of the equipotential aluminum 15 at the time of measurement, and the degree of freedom in selecting the measurement method can be increased.

The measurement method according to the present invention is a method for measuring the characteristics of the semiconductor device described above. As shown in FIG. 7, the collector electrode 22 of the measurement insulated gate bipolar transistor (IGBT) is replaced by the back electrode (collector) Electrically connecting to the electrode 8) and connecting the inductive load 20 so as to connect the collector electrode 8 and the measurement electrode portion (channel stopper electrode 16) (preparation step); When a plurality of pulse voltages are input between the gate electrode and the emitter electrode 23 of the insulated gate bipolar transistor (IGBT), the first conductivity type region (p ⁻ layer 7) and the second conductivity type region (n ^- layer 6) and flowing through the (ie PN diode) and a step (measuring step) to measure the current value.

In this way, the amount of holes injected into the junction (PN diode) between the first conductive region (p ⁻ layer 7) and the second conductive region (n ⁻ layer 6), and the conductive region constituting the PN diode Information about the state can be easily obtained.

  In another measurement method according to the present invention, a recovery surge breakdown test of the PN junction at the junction between the first conductivity type region and the second conductivity type region is performed using the above measurement method, thereby Measure the thickness of the region.

  In the above-described embodiment, an IGBT is used as an example of a semiconductor device. However, in the present invention, a PN junction is formed in a semiconductor substrate and is electrically connected to any conductive region of the PN junction. Any semiconductor device in which the channel stopper region 14 and the equipotential conductor (equipotential aluminum 15) are formed can be applied to a semiconductor device having an arbitrary functional element.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention is particularly advantageously applied to IGBTs.

1 element formation region, 2 chip termination region, 3,23 emitter electrode, 4 n ⁺ layer, 5 p ⁺ layer, 6 n ⁻ layer, 7 p ⁺ layer, 8, 22 collector electrode, 9 gate electrode, 10 oxide film, 11 Passivation film, 12 Guard ring, 13, 15 Equipotential aluminum, 14 channel stopper region, 16 channel stopper electrode, 17 opening, 20 inductive load, 31 extension.

Claims (1)

A method for measuring characteristics of a semiconductor device which is an insulated gate bipolar transistor ,
The semiconductor device includes:
A semiconductor substrate having a main surface and having an element formation region on the main surface;
A guard ring formed on the main surface of the semiconductor substrate so as to surround the element formation region in plan view;
A channel stopper region formed on the main surface of the semiconductor substrate so as to be positioned on the outer peripheral side of the guard ring;
An equipotential conductor formed on the main surface of the semiconductor substrate and electrically connected to the channel stopper region;
In the semiconductor substrate, comprising a back electrode formed on the back surface opposite to the main surface,
The semiconductor substrate is
A first conductivity type region electrically connected to the back electrode and having a conductivity type of the first conductivity type;
A second conductivity type region that is in direct contact with the first conductivity type region, the second conductivity type being different from the first conductivity type and in direct contact with the channel stopper region;
The equipotential conductor includes a measurement electrode part, and
The semiconductor device includes a coating film covering at least the equipotential conductor,
In the coating film, an opening that exposes a part of the surface of the equipotential conductor is formed,
The equipotential conductor includes an extending portion that extends to the surface of the coating film through the opening,
The measurement electrode part includes the extension part,
The extending portion extends to a region located above the guard ring on the surface of the coating film,
Electrically connecting a collector electrode of an insulated gate bipolar transistor for measurement to the back electrode of the semiconductor device, and connecting an inductive load so as to connect the back electrode and the measurement electrode part; ,
A current value flowing through the first conductivity type region and the second conductivity type region of the semiconductor device when a plurality of pulse voltages are input between the gate electrode and the emitter electrode of the insulated gate bipolar transistor for measurement. And measuring the electrical characteristics of the PN junction formed at the contact portion between the first conductivity type region and the second conductivity type region by measuring.

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