JPH07128396A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To make it possible to easily measure gate leak current without requiring any test jig by providing a plurality of input buffer circuits each having a MOS transistor, a plurality of switch circuits, and a control circuit therefor. CONSTITUTION:At the time of gate leak current test, a test mode switching signal is set at H level with a power supply voltage VDD and a ground potential GND being applied to circuits in an LSI and each CMOS transfer gate circuit 14 is turned on based on an output level H from a buffer circuit 161 and an output level L from an inverter circuit 162. Since each node of each input buffer circuit 121-12n is short-circuited, DC input can be applied simultaneously to all input pins 111 to 11n of the LSI when the terminal of an external LSI tester is connected with any one of the input pins 111 and thereby, the gate leak current can be measured simultaneously.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a test circuit for performing a gate leak test function of an input buffer circuit in a large scale integrated circuit (LSI).

[0002]

2. Description of the Related Art LSI is one of the DC tests for LSI.
The amount of gate leakage current of the MOS transistor of the input buffer circuit is measured. As one of the methods for performing this gate leak test, an LSI is provided for each input pin of the LSI.
The gate leak current for each input buffer circuit in this state is measured by setting it to "H" level or "L" level by the tester.

However, according to this method, the measurement condition is set for each input pin and the measurement is performed. Therefore, the measurement time increases as the number of pins of the LSI increases. Further, due to the recent progress in the miniaturization processing technology of LSI, the high integration has been advanced, and the input / output of the bidirectional buffer circuit connected to the input / output pin of the LSI has been advanced.
A huge number of test patterns are required to control the output, which also causes an increase in measurement time.

As another example of the method for performing the gate leak test, a gate leak test jig capable of setting each input pin of the LSI to a short-circuited state outside the LSI is used, and all pins of the LSI are short-circuited. A giant leak test is performed in which "H" level or "L" level is applied to the input pins from the LSI tester and the gate leak currents of all the input buffer circuits are measured at one time.

However, in this method, it is necessary to prepare a jig for a gate leak test for each type of LSI, which causes an increase in inspection cost of the LSI and an increase in development period. Further, when the input pins of the LSI include those to which the input load resistance is connected and those not to be connected, it is necessary to correct the gate leak test jig as described above.
Since it is not possible to measure all the input pins at once, it is necessary to measure in multiple times, which also leads to an increase in development period.

On the other hand, in LSI such as DRAM,
There is known a technique for simplifying an LSI tester by incorporating a test circuit for performing a functional test in the LSI, and a test circuit for performing a gate leak test of the LSI is incorporated in the LSI according to this. However, it is necessary to solve various problems peculiar to the input circuit section of the LSI and devise an appropriate circuit configuration.

[0007]

As described above, in the conventional semiconductor integrated circuit, when the gate leakage currents of a plurality of LSI input buffer circuits are simultaneously measured, a gate leakage test jig is provided for each LSI type. Need to prepare,
There is a problem in that the inspection cost of the LSI and the development period increase.

The present invention has been made to solve the above-mentioned problems, and it is possible to obtain an L
An object of the present invention is to provide a semiconductor integrated circuit capable of easily measuring the gate leak current of an SI input buffer circuit in a short time.

[0009]

In a semiconductor integrated circuit of the present invention, a plurality of signal input terminals are connected to respective input nodes corresponding to the plurality of signal input terminals, and gates are connected to the respective input nodes. A plurality of input buffer circuits having connected MOS transistors, a plurality of switch circuits inserted so as to short-circuit between the input nodes of the plurality of input buffer circuits, and a plurality of switch circuits are provided. A test mode switching signal for switch control is provided, and a control circuit for controlling each of the plurality of switch circuits into an off state or an on state based on the test mode switching signal is provided.

[0010]

In normal operation, each input buffer circuit can be operated by controlling each switch circuit to the off state based on the test mode switching signal. During the gate leak current test, the respective input nodes of the plurality of input buffer circuits are short-circuited by controlling each switch circuit to the ON state based on the test mode switching signal. It becomes possible to measure the leak current in a short time.

[0011]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a first embodiment of the input circuit section in the LSI of the present invention. In this LSI, 1
11 to 11n are a plurality of signal input pins, 121 to 12n
Is a plurality of input buffer circuits connected corresponding to the plurality of signal input pins, each of which is, for example, a CM.
The OS inverter circuit 13 is connected in two stages, and its output node is connected to the LSI internal circuit.

Reference numeral 14 denotes the plurality of input buffer circuits 1
It is a plurality of switch circuits inserted so that each input node of 21 to 12n can be short-circuited. In this example, one CM is provided between the input node of any one input buffer circuit and the input node of another one input buffer circuit, for example, CM.
An OS transfer gate circuit is connected, and the input nodes of the input buffer circuits 121 to 12n are sequentially connected (they are connected in a ring shape as a whole).

Numeral 15 is one control pin to which a test mode switching signal is inputted from the outside, and a test mode switching signal is given from this control pin 15, and the plurality of CMOS transfer gates are supplied based on this test mode switching signal. A control circuit is provided to control 14 ...

This control circuit receives a test mode switching signal input from the control pin 15 and supplies the output signal to the gates of the NMOS transistors TN of the CMOS transfer gate circuits 14 ...
, Corresponding to the CMOS transfer gate circuits 14 ..., Receiving and inverting the output signals of the buffer circuits 161 respectively, and corresponding PMOs of the CMOS transfer gate circuits 14 ...
A plurality of inverter circuits 162 supplied to the gate of the S transistor TP, the control pin 15 and the ground potential (G
ND) node and a resistance element R for pull-down connected to the node.

The control pin 15, the control circuit and the plurality of CMOS transfer gate circuits 14 ... Form a gate leak current test circuit 17. In the LSI of the above embodiment, during normal operation, the test mode switching signal is set to the "L" level with the power supply voltage VDD and the ground potential GND being applied to the circuit in the LSI.
Based on the output level "L" of the buffer circuit 161 and the output level "H" of the inverter circuits 162 ...
Each of the S transfer gate circuits 14 ... Is controlled to an off state. As a result, each input buffer circuit 121 to
12n becomes operable.

On the other hand, during the gate leak current test, the power supply voltage VDD and the ground potential GN are applied to the circuits in the LSI.
The test mode switching signal is set to the “H” level in the state where D is applied, and each CMOS transfer gate circuit 1 is set based on the output level “H” of the buffer circuit 161 and the output level “L” of the inverter circuit 162.
4 ... are controlled to be in the ON state.

As a result, each input buffer circuit 121-
Since the 12n input nodes are short-circuited to each other, LS
External L to any one of I input pins 111 to 11n
By connecting the terminals of the SI tester, it becomes possible to simultaneously apply the DC input to all the input pins 111 to 11n of the LSI and measure the gate leak current at one time.

In this case, in a normal LSI (non-defective product), each gate leak current of each input buffer circuit 121 to 12n is 0 A, and if the gate leak current flows, an LSI.
If there is, it is defective.

Therefore, it is not necessary to set the measurement condition for each input pin as in the case of measuring the gate leak current for each input buffer circuit for each input pin of the LSI, and L
Even if the number of SI pins increases, the measurement time for one pin is sufficient.

By the way, at least one of the signal input terminals of the LSI or at least one of the input nodes of the input buffer circuits may interfere with the gate leak current test. The circuit may be connected. In this case as well, it is necessary to prevent other circuits from interfering with the gate leak current test when performing the gate leak current test so that the present invention can be applied.

[0021] Conventionally, as an example in which another circuit that is a hindrance when performing a gate leak current test is connected, typically, a resistance element for pulling up or pulling down is connected to a signal input pin. , The case where the output node of the output buffer circuit of the bidirectional buffer circuit is connected to the signal input pin.

Further, the input node of the input buffer circuit
Even if a feedback circuit is connected between the output nodes, these circuits may interfere with the gate leak current test.

FIG. 2 shows a second embodiment of the input circuit section in the LSI of the present invention. In this LSI,
Compared with the LSI shown in FIG. 1, a load resistance element composed of a PMOS transistor 21 is connected between an input node of a part of the input buffer circuit 121 and a power supply potential (VDD) node, and another part of the input is connected. The NMOS transistor 22 is provided between the input node of the buffer circuit 122 and the GND node.
Is connected to the gate of the PMOS transistor 21, and the output signal of the buffer circuit 161 of the gate leakage current test circuit 17 is supplied to the gate of the PMOS transistor 21.
The output signal of the buffer circuit 161 is converted into the inverter circuit 2
The signal inverted by 3 is applied to the NMOS transistor 2
Since they are supplied to the second gate and are otherwise the same, the same reference numerals as in FIG. 1 are given.

The operation of this LSI is basically the same as that of the LSI shown in FIG. 1, but the PMOS for the load resistance element connected to the input node of the input buffer circuit is used.
The operating states of the transistor 21 and the NMOS transistor 22 are controlled in synchronization with the ON / OFF states of the CMOS transfer gate circuits 14 ... In the gate leak current test circuit.

That is, during the normal operation (the test mode switching signal is at "L" level), the PMOS transistor 21 is controlled to be in the ON state based on the output level "L" of the buffer circuit 161, and the output level of the inverter circuit 23. The NMOS transistor 22 is controlled to be in the ON state based on "H", and the operation of each input buffer circuit becomes possible.

During the gate leak current test (the test mode switching signal is at "H" level), the buffer circuit 16
The PMOS transistor 21 is controlled to the off state based on the output level "H" of 1 and the NMOS transistor 22 is controlled to the off state based on the output level "L" of the inverter circuit 23, enabling the gate leak current test. .

Therefore, in the LSI shown in FIG.
Even if some of the input pins of the LSI are connected to input load resistors and some are not,
It becomes possible to measure the gate leak current for all the input pins 111 to 11n of the LSI at one time.

Conventionally, each input pin of the LSI is connected to the LSI.
Compared with the need to prepare a gate leak test jig for each type of LSI when using a gate leak test jig that can be set to a short-circuit state externally, this is no longer necessary, and the LSI inspection cost And the development period of the LSI can be shortened.

FIG. 3 shows, as a modification of the input buffer circuit of the LSI shown in FIG. 2, a feedback circuit of an oscillation circuit using a CMOS inverter circuit connected to an input pin 113 to which a crystal oscillator is externally attached. The example which controls is shown.

In this case, the PMOS transistor 32 and the NMOS transistor 33 for the feedback circuit are provided between the input node and the output node of the first stage CMOS inverter circuit 31.
Are inserted in parallel, and during normal operation (the test mode switching signal is at “L” level), the PMOS transistor 32 based on the output level “L” of the buffer circuit 161.
Are turned on, and the NMOS transistor 33 is turned on based on the output level “H” of the inverter circuit 34. During the gate leak current test, the PMOS transistor 32 is controlled to be off based on the output level “H” of the buffer circuit 161, and the NMOS transistor 33 is controlled to be off based on the output level “L” of the inverter circuit 34. As a result, the CMOS inverter circuit 31 at the first stage of the oscillation circuit
The gate leakage current test for

FIG. 4 shows a third embodiment of the input circuit section in the LSI of the present invention. In this LSI,
Compared with the LSI shown in FIG. 1, the input buffer circuit 12
Output buffer circuits 421 and 422 corresponding to
Is used, and the bidirectional buffer circuit is connected to the signal input / output pins 411 and 412, and for controlling the PMOS transistor of the CMOS transfer gate circuit 14 in the gate leakage current test circuit. The output signal of the inverter circuit 162 is output buffer circuits 421 and 422 of the bidirectional buffer circuit.
1 is the same as that in FIG. 1, and is the same as that in FIG.

The operation of this LSI is basically the same as that of the LSI shown in FIG. 1, but the active / inactive state of the output buffer circuits 421 and 422 of the bidirectional buffer circuit is the same as that of the gate leak current test circuit. The CMOS transfer gate circuits 14 ... Are synchronously controlled corresponding to the off / on state.

That is, during the normal operation (the test mode switching signal is at "L" level), the output buffer circuits 421, 42 are based on the output level "H" of the inverter circuit 162.
2 is controlled to the active state, and the bidirectional operation of each bidirectional buffer circuit becomes possible.

During the gate leak current test (the test mode switching signal is at "H" level), the inverter circuit 1
The output buffer circuit 4 based on the output level "L" of 62.
Since 21, 422 are controlled to be inactive, each bidirectional buffer circuit is forced to input buffer circuits 121, 12.
Only 2 can be operated, and a gate leak current test can be performed.

Therefore, in the LSI shown in FIG.
To reduce the measurement time, reduce the LSI inspection cost, and shorten the LSI development period compared with the conventional method that required enormous test patterns to control the input / output of the bidirectional buffer circuit. Will be possible.

In each of the above embodiments, the test mode switching signal for controlling the switching of the plurality of switch circuits is input from the outside through the control pin, but the present invention is not limited to this.
LSI based on input from at least one external pin
It may be modified to internally generate the test mode switching signal.

The specific configuration of the gate leakage current test circuit according to the present invention is not limited to the above-mentioned embodiments, and various modifications can be made. Further, the present invention may be implemented by arbitrarily combining the above-described embodiments, or the signal input terminal group may be divided into a plurality of blocks and each block may be implemented as in the above-described embodiments.

In each of the above embodiments, the MOS type LSI is used.
However, the present invention is not limited to the analog / digital mixed type LS.
It is also applicable to the case of performing the gate leak current test of the MOS type input buffer circuit section in I.

Further, in each of the above-mentioned embodiments, the external pins are shown as the external terminals assuming the LSI after packaging is completed, but the present invention is not limited to this, and conductive bumps are used as the external terminals. LSIs and LSIs after the wafer process, which corresponds to signal input pads as external terminals
It is also applicable when performing a gate leak current test on a chip region.

When performing a gate leak current test in the LSI chip area in a wafer state, as shown in FIG. 5, the input gate connected to the input side of each input buffer circuit is protected (static from the input pin). The gate for leaking the input current to the power supply potential or the ground potential to prevent the input gate from being damaged by electrostatic discharge may also be used in the gate leak current test. It becomes possible to omit the addition of the switch circuit and the control circuit for the current test.

That is, a PMOS in which the drain / gate / substrate are connected to each other for input gate protection between the first pad 51 and the input node of each input buffer circuit.
The transistor 53 is connected, and the drain, gate, and substrate are connected to each other for input gate protection between the input node of the input buffer circuit and the second pad 52.
The MOS transistor 54 is connected. In this case, P
The drain / substrate region of the MOS transistor 53 is formed to be electrically separated from the substrate regions of other internal circuits.
It is assumed that the drain / substrate region of the NMOS transistor 54 is electrically separated from the substrate regions of other internal circuits.

When the gate leak current test is performed in the wafer state, the first pad 51 is opened (floating) and a required DC voltage is applied to the second pad 52, whereby each input buffer is To the input node of each input buffer circuit via the PN junction of the input gate protection NMOS transistor 54 connected to the input side of the circuit and the input protection resistor (not shown) inserted in series in the input path. It becomes possible to apply DC inputs all at once.

At times other than the above gate leak current test,
By applying the power supply potential VDD to the first pad 51 and the ground potential GND to the second pad 52, the gate protection operation by the PMOS transistor 53 and the NMOS transistor 54 becomes possible.

As a method of applying a required electric potential to each of the pads 51 and 52, in the wafer state, the electric potential is applied from the probe card of the prober of the LSI tester,
At the time of assembly, the above pads may be connected to external terminals for power supply or ground by bonding wires, for example.

[0045]

As described above, according to the present invention, it is possible to realize a semiconductor integrated circuit capable of easily measuring the gate leak current of an input buffer circuit of an LSI in a short time without the need for a jig for a gate leak test. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an input circuit unit of an LSI according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing an input circuit unit of an LSI according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a modification of the input circuit unit of the LSI shown in FIG.

FIG. 4 is a circuit diagram showing an input circuit section of an LSI according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing an input circuit section of an LSI according to a fourth embodiment of the present invention.

FIG. 6 is a circuit diagram showing an input circuit section of a conventional LSI.

[Explanation of symbols]

111-11n ... Signal input pins, 121-12n ... Input buffer circuits, 13, 23, 31, 34 ... CMOS inverter circuits, 14 ... Switch circuits (CMOS transfer gate circuits), 15 ... Control pins, 161 ... Control circuit buffers Circuit, 162 ... Inverter circuit for control circuit, 1
7 ... Gate leak current test circuit, 411, 412 ... Signal input / output pin, 421, 422 ... Output buffer circuit, 2
1, 32, TP ... PMOS transistors, 22, 33,
TN ... NMOS transistor, R ... Resistance element.

Claims (2)

[Claims] 1. A MOS having a plurality of signal input terminals, each input node connected to the plurality of signal input terminals, and a gate connected to each input node.
A plurality of input buffer circuits having transistors, a plurality of switch circuits inserted so that each input node of the plurality of input buffer circuits can be short-circuited, and a switch control circuit for the plurality of switch circuits. And a control circuit for controlling each of the plurality of switch circuits into an off state or an on state based on the test mode switching signal. 2. The semiconductor integrated circuit according to claim 1, further connected to at least one of the plurality of signal input terminals or at least one of input nodes of the plurality of input buffer circuits. When performing a gate leak current test of the input buffer circuit, the control circuit controls each of the plurality of switch circuits to be in an ON state based on the test mode switching signal, and A semiconductor integrated circuit, characterized in that a predetermined circuit is controlled so as not to interfere with the gate leakage current test.