JP2848441B2 - CMOS semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a CMOS semiconductor device having a test circuit.

[0002]

2. Description of the Related Art Conventionally, in a CMOS semiconductor device having a CMOS circuit, various test circuits and test methods have been considered in order to obtain a high fault detection rate. The failure detection rate refers to a ratio of a detectable failure among all possible failures such as elements and wiring of a CMOS semiconductor device in a test. Therefore, a test with a high failure detection rate can select defective products with a high probability.

As a general test method, there is a method in which a test pattern is input to an input terminal, and it is determined whether an output terminal outputs a correct value according to the logic of the circuit. Therefore, in this test, if there is a failure in the circuit, the output terminal outputs a value different from the expected value.

However, in recent years, as the semiconductor process becomes finer and the circuit size of the CMOS semiconductor device increases, the length of the test pattern tends to increase in order to obtain a high failure detection rate in the above-described test. With the increase of the test pattern length, there has been a problem that an enormous amount of time is required for creating the test pattern.

In order to solve such a problem, Idd
A q test was considered. Hereinafter, the Iddq test will be briefly described.

In a CMOS circuit, a current flows when a signal changes, but normally, when the signal does not change, that is, in a steady state, there is no path from the power supply to the ground (GND). , Several μA to several tens μ
Only the current of A flows. The Iddq test is a method of finding a fault by measuring the current in a steady state by using the characteristics of such a CMOS circuit.

Recently, due to the use of a composite logic block or the like, even if a current flows, the voltage drop is settled to the extent that it does not exceed the threshold voltage, and the operation of the function test becomes normal. In this case, the operation is normal, but the Iddq test fails. In such a case, there is a case where there is no problem because the operation is normal, but the feature of the low power consumption of the CMOS circuit disappears.

As described above, the Iddq test has a feature that a defect that cannot be detected by the function test can be detected.

Further, even if there is a defect that can be found in the function test, in order to detect the defect as a fault, in addition to activating the input of the defective transistor, the effect is propagated to the output terminal. There is a need. On the other hand, in the Iddq test, by activating the input, the detection result can be observed through the power supply line, and the value need not be propagated to the output. Therefore, it can also be used as a complement to a function test.

In the Iddq test, if a steady state current of a CMOS circuit is measured with one test pattern, more than half of all the fault definitions of the CMOS semiconductor device can be detected. Furthermore, CMOS
If a steady state current is measured with a plurality of test patterns in which the inside of the circuit changes, a high fault detection rate can be effectively obtained with a small test pattern.

Here, a point to be noted in the Iddq test is that the CMOS semiconductor device includes a CMOS circuit,
There is a case in which the combination with a PULL-UP buffer or a PULL-DOWN buffer is used. PU
The LL-UP buffer and the PULL-DOWN buffer are buffers having a resistance connected to a power supply and a ground in addition to a transistor path.
When the output value becomes 0 in the buffer, PULL-
When the output value becomes 1 in the DOWN buffer, a current path is formed between the power supply and the ground. Therefore, when selecting a test pattern, it is necessary to avoid such a test pattern that causes a current path as described above.

However, when these buffers have the current cut mode, the power supply current flowing from the power supply to the ground (GND) in the steady state can be reduced to 0 by cutting the current path.
The reliability of the ddq test can be improved. Therefore, the circuit of the CMOS semiconductor device performing the Iddq test sets the power supply current from the power supply to GND in the steady state to 0.
With this function, highly accurate tests can be performed.

An example of such a CMOS semiconductor device is a CMOS differential circuit as shown in FIG. This CMOS differential circuit has a data input terminal 1
, Data inverting input terminal 2 and test signal input terminal 3
, And an output terminal 4, and includes a differential amplifier unit 5, a test circuit unit 6b, and a first inverter 7.

The test circuit section 6b comprises an nMOS transistor 15b connected to the test signal input terminal 3 and driven by the test signal.
The input to the first inverter 7 during the test is controlled.

When an Iddq test is performed using a differential circuit having such a test circuit, "H" is input to the test signal input terminal 3 and the power supply current of the differential amplifier unit 5 is set to zero. At this time, the nMOS transistor 15b of the test circuit unit 6b is turned on, so that the differential amplifier unit output 11
Is fixed to the pseudo output “L”. Further, since the power supply current of the first inverter 7 also becomes 0, the power supply current of the entire differential circuit becomes 0, thereby enabling the Iddq test. At this time, the potential of the output terminal 4 is fixed at "H".

When "L" is input to the test signal input terminal 3, the nMOS transistor 15b of the test circuit section 6b is turned off, and the CMOS differential circuit operates normally.

[0017]

However, in the above-described conventional CMOS differential circuit, when the Iddq test is performed, that is, when "H" is input to the test signal input terminal 3, the pseudo-amp of the differential amplifier unit 5 is generated. Output is fixed to "L", thereby the first inverter 7
Will always output "H". Therefore, the first
However, there is a problem that the failure when the output of the inverter 7 is "L" cannot be detected, and the failure detection rate hardly increases.

An object of the present invention is to solve the above-mentioned problems,
Another object of the present invention is to provide a differential circuit that outputs the same logical value as in a normal operation even when performing a ddq test.

[0019]

According to the present invention, a power supply line, a data input terminal, a buffer circuit connected to the data input terminal and the power supply line, and a buffer circuit connected to the buffer circuit and the power supply line are provided. A CMOS circuit, a data output terminal connected to the CMOS circuit, a test circuit, a test signal input terminal for inputting a test signal for performing a test, and a test circuit connected to the test signal input terminal. A switch circuit for interrupting connection between the buffer circuit and the power supply line when a signal is input,
At the time of non-test, while outputting data of a predetermined logical value from the data output terminal according to the input data from the data input terminal, at the time of test, the test signal input is performed while the input to the data input terminal is fixed. In a CMOS semiconductor device configured to perform a test by inputting the test signal to a terminal, the test circuit is connected in parallel with the buffer circuit between the data input terminal and the CMOS circuit, The test circuit is further connected to the test signal input terminal and the power supply line, and has a function of outputting a high-level or low-level signal according to the input data input from the input terminal during a test. CMOS semiconductor device is obtained.

Further, according to the present invention, in the CMOS semiconductor device, the data input terminal includes first and second data input terminals.
The data input to the second data input terminal is data having a value obtained by inverting the data input to the first data input terminal, and the buffer circuit includes the data input terminal A CMOS semiconductor device is obtained, which is a differential amplifier connected to the first and second data input terminals, and wherein the CMOS circuit is a first inverter.

According to the invention, in particular, in the CMOS semiconductor device, the test circuit is connected to the first data input terminal and inverts data input to the first data input terminal. An inverter, a two-input NAND circuit connected to the output terminal of the second inverter and the test signal input terminal, and a pMOS connected to the output terminal of the two-input NAND circuit and driven by the output of the two-input NAND circuit A transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nM connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit
An OS transistor; the pMOS transistor and the nMOS transistor are connected in series between the power supply line and ground;
A CMOS semiconductor device is obtained in which the potential of the common connection between the S transistor and the nMOS transistor is input to the first inverter.

Further, according to the present invention, in the CMOS semiconductor device, the test circuit includes a two-input NAND circuit connected to the second data input terminal and the test signal input terminal; And is driven by the output of the two-input NAND circuit
A MOS transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nMOS connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit Transistors, the pMOS transistor and the nMOS transistor are connected in series between the power supply line and the ground, and the potential of a common connection portion between the pMOS transistor and the nMOS transistor is set to the first inverter. Is obtained as a CMOS semiconductor device.

[0023]

Next, a CM according to an embodiment of the present invention will be described.
The OS differential circuit will be described with reference to the drawings.

(First Embodiment) A CMOS differential circuit according to a first embodiment of the present invention has a circuit configuration as shown in FIG. That is, the CM according to the first embodiment of the present invention
The OS differential circuit has a data input terminal 1, a data inversion input terminal 2, and a test signal input terminal 3, and includes a differential amplifier unit 5, a test circuit unit 6a, and a first inverter 7.

The test circuit section 6a includes a second inverter 16 connected to the data input terminal 1 for inverting data input to the data input terminal 1, and a second inverter 1
6, a two-input NAND circuit 17 connected to the output terminal 6 and the test signal input terminal 3, a pMOS transistor 14 connected to the output terminal of the two-input NAND circuit 17 and driven by the output of the two-input NAND circuit 17, A two-input AND circuit 18 connected to the terminal 1 and the test signal input terminal 3 and an n connected to the output terminal of the two-input AND circuit 18 and driven by the output of the two-input AND circuit 18
And a MOS transistor 15a. Here, the pMOS transistor 14 and the nMOS transistor 15a are connected in series between the power supply 12 and the ground 13. Further, the pMOS transistor 14 and n
The common connection with the MOS transistor 15a is connected to the first inverter 7, and during the Iddq test,
pMOS transistor 14 and nMOS transistor 15
The potential of the common connection portion with the signal a becomes the input signal to the first inverter 7, that is, the pseudo output of the differential amplifier unit output 11.

The circuit operation of the CMOS differential circuit according to the first embodiment of the present invention having such a circuit configuration will be described with reference to a timing chart as shown in FIG.

FIGS. 2A to 2H show timing charts of respective nodes in the CMOS differential circuit of the first embodiment shown in FIG. Here, (a) is a timing chart of the input signal to the data input terminal 1, (b) is a timing chart of the input signal to the data inversion input terminal 2, and (c) is the test signal input terminal 3. 4 (d) is a timing chart of an output signal from the output terminal 4. FIG. (E) is a timing chart of the differential amplifier section output 11, and (f) is a pMOS of the test circuit section 6a.
6 is a timing chart of a transistor gate 9;
(G) is a timing chart of the nMOS transistor gate 10 of the test circuit section 6a. (H) shows a timing chart of the current of the power supply 12.

First, at time t ₀ , the data input terminal 1 is “L” (see (a)), the data inversion input terminal 2 is “H” (see (b)), and the test signal input terminal 3 is “L” (see (b)).
When ((c)) is input, the output 11 of the differential amplifier section becomes “H ′” (H> H ′) (see (e)), and the “H ′” signal is input to the first inverter 7. And the output from the output terminal 4 becomes "L" (see (d)). At this time, a power supply current is generated in the differential amplifier unit 5 and the first inverter 7 (see (h)).

Next, at time t ₁ , the input to the data input terminal 1 changes from “L” to “H” (see (a)), and the input to the data inversion input terminal 2 changes from “H” to “L”. (See (b)), the output 11 of the differential amplifier section changes from “H ′” to “L” (see (e)), and the output from the output terminal 4 changes from “L” to “H” (see (e)). (See (d)). At this time, the power supply current is generated in the differential amplifier unit 5 and the first inverter 7 as in the case of the time t ₀ (see (h)).

Next, at time t _2, (see (c)) When the input to the test signal input terminal 3 changes from "L""H", pMOS transistor 8 of the differential amplifier unit 5 is turned off , The test circuit unit 6a operates, and the nMOS transistor gate 10 of the test circuit unit 6a is set to “L”.
To “H” (see (g)), and the test circuit section 6a
The nMOS transistor 15a is turned on, and the differential amplifier output 11 changes from “L ′” to a pseudo output “L” (see (e)). However, the output from the output terminal 4 is
It remains at "H" (see (d)). Here, the power supply current changes to “0” because the pMOS transistor 8 of the differential amplifier unit 5 is turned off and the differential amplifier unit 5 is disconnected (see (h)). At this time, the output logic value at the output terminal 4 of the CMOS differential circuit remains the output logic value in the normal operation, the power supply current becomes 0, and the Iddq test becomes possible.

Next, at time t ₃ , when the input to the test signal input terminal 3 changes from “H” to “L” (see (c)), the nMOS transistor gate 15 a of the test circuit section 6 a becomes “H”. From "L" to "L" (see (g)), and the differential amplifier output 11 changes from the pseudo output "L" to the actual output "L '" ((e)).
reference). However, the output from the output terminal 4 remains at "H" (see (d)). Also, the pM of the differential amplifier unit 5
The OS transistor 8 is turned on, a power supply current is generated in the differential amplifier unit 5 (see (h)), and the CMOS differential circuit returns to the normal operation.

Next, at time t ₄ , the input to the data input terminal 1 changes from “H” to “L” (see (a)), and the input to the data inversion input terminal 2 changes from “L” to “H”. (See (b)), the output 11 of the differential amplifier section changes from “L” to “H” (see (e)), and the output from the output terminal 4 changes from “H” to “L” ((d See)) change. At this time, similarly to the time t _1, the supply current is generated in the differential amplifier section 5 and the first inverter 7 ((h) see).

Next, at time t _5, (see (c)) When the input to the test signal input terminal 3 changes from "H" to "L", pMOS transistor 8 of the differential amplifier section 5 from on The test circuit 6a is turned off, and the pMOS transistor gate 9 of the test circuit 6a is turned off.
Changes from "H" to "L" (see (f)), and the pMOS transistor 14 of the test circuit section 6a changes from off to on. As a result, the differential amplifier output 11 becomes “H”.
”Changes to a pseudo output“ H ”(see (e)), so that the output from the output terminal 4 remains at“ L ”(see (d)). It becomes "0" in the same manner as _2. At this time, the output logic value at the output terminal 4 of the CMOS differential circuit remains the output logic value in the normal operation, the power supply current becomes 0, and the Iddq test can be performed. Become.

Next, at time t ₆ , when the input to the test signal input terminal 3 changes from “H” to “L” (see (c)), the pMOS transistor gate 9 of the test circuit section 6 a becomes “ From "L" to "H" ((f)
), And the differential amplifier section output 11 is a pseudo output “H”.
To the actual output “H ′” (see (e)).
At this time, the output from the output terminal 4 remains at "L" (see (d)). Further, the pMOS transistor 8 of the differential amplifier unit 5 is turned on from off, and a power supply current is generated in the differential amplifier unit 5 (see (h)), and the CMOS differential circuit returns to the normal operation.

As described above, the CM of the first embodiment
The OS differential circuit shuts off the power supply between the differential amplifier unit 5 and the power supply, sets the power supply current to 0, performs an Iddq test on the CMOS differential circuit, simulates the output of the differential amplifier unit, and performs normal operation. It is possible to output the same logical value as.

Second Embodiment A CMOS differential circuit according to a second embodiment of the present invention will be described with reference to the drawings.

The CMOS differential circuit according to the second embodiment has
The circuit configuration is as shown in FIG. Referring to FIG. 3, it can be seen that the circuit configuration is almost the same as that of the CMOS differential circuit of the first embodiment, but the test circuit section 6a is different.

The test circuit section 6a in the CMOS differential circuit according to the second embodiment includes a two-input NAND circuit 17 connected to the data inversion input terminal 2 and the test signal input terminal 3.
A pMOS transistor 14 connected to the output terminal of the two-input NAND circuit 17 and driven by the output of the two-input NAND circuit 17, a two-input AND circuit 18 connected to the data input terminal 1 and the test signal input terminal 3, An nMOS transistor 15a is connected to the output terminal of the two-input AND circuit 18 and is driven by the output of the two-input AND circuit 18. Here, the pMOS transistor 14 and the nMOS transistor 15a are connected to the power supply 1
2 and a ground 13 are connected in series. Further, the common connection between the pMOS transistor 14 and the nMOS transistor 15a is connected to the first inverter 7, and during the Iddq test, the potential at the common connection between the pMOS transistor 14 and the nMOS transistor 15a is changed to the first inverter 7 , Ie, a pseudo output of the differential amplifier section output 11.

In the CMOS differential circuit according to the second embodiment, at the input of the two-input NAND circuit 17 serving as the signal of the gate 9 of the pMOS transistor, like the CMOS differential circuit according to the first embodiment, Instead of passing the input from the data input terminal 1 through the second inverter 16 and then inputting it to the two-input NAND circuit 17, the input from the data inverting input terminal 2 is directly input to the two-input NAND circuit 17. . As a result, compared with the CMOS differential circuit according to the first embodiment, there is an advantage that the circuit area is reduced because one second inverter 16 is reduced.

The timing chart at each node of the circuit is the same as that of the CMOS differential circuit of the first embodiment.

[0041]

As described above, according to the present invention, it is possible to obtain a CMOS semiconductor device which can easily perform a high-precision test without lowering a failure detection rate when performing an Iddq test. Was done.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a CMOS differential circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a timing chart at each node of the CMOS differential circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a CMOS differential circuit according to a second embodiment of the present invention.

FIG. 4 is a circuit diagram showing a conventional CMOS differential circuit.

[Explanation of symbols]

 Reference Signs List 1 data input terminal 2 data inversion input terminal 3 test signal input terminal 4 output terminal 5 differential amplifier section 6a test circuit section (present invention) 6b test circuit section (conventional) 7 first inverter 8 pMOS transistor of differential amplifier section Reference Signs List 9 pMOS transistor gate of test circuit section 10 nMOS transistor gate of test circuit section 11 differential amplifier section output 12 power supply 13 ground (GND) 14 pMOS transistor of test circuit section 15a nMOS transistor of test circuit section 15b nMOS transistor of test circuit section 16 Second inverter 17 Two-input NAND circuit 18 Two-input AND circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G01R 31/28-31/3193 G01R 31/26 H01L 21/8238 H01L 27/04 H03K 19/00

Claims (4)

(57) [Claims] 1. A power supply line, a data input terminal, a buffer circuit connected to the data input terminal and the power supply line, a CMOS circuit connected to the buffer circuit and the power supply line, and a connection to the CMOS circuit A data output terminal, a test circuit, a test signal input terminal for inputting a test signal for performing a test, a buffer circuit and the power supply line connected to the test signal input terminal when a test signal is input. And a switch circuit for interrupting connection with the data input terminal, and outputs data of a predetermined logical value from the data output terminal in accordance with input data from the data input terminal during a non-test, and to the data input terminal during a test. CMOS in which the test signal is input to the test signal input terminal while the input of the In the semiconductor device, the test circuit includes the data input terminal and the CMOS.
Between the test signal input terminal and the power supply line, and the input data input from the input terminal during a test. A CMOS semiconductor device having a function of outputting a high-level or low-level signal according to the following. 2. The CMOS semiconductor device according to claim 1, wherein said data input terminal includes first and second data input terminals, and data input to said second data input terminal is said first data input terminal. The buffer circuit is a differential amplifier connected to the first and second data input terminals; and the CMOS circuit is a first amplifier connected to the first and second data input terminals. CMOS semiconductor device, characterized in that it is an inverter of (1). 3. The CMOS semiconductor device according to claim 2, wherein said test circuit is connected to said first data input terminal and inverts data input to said first data input terminal. A two-input NAND circuit connected to the output terminal of the second inverter and the test signal input terminal; and a pMOS connected to the output terminal of the two-input NAND circuit and driven by the output of the two-input NAND circuit
A transistor, a two-input AND circuit connected to the first data input terminal and the test signal input terminal, and an nMOS transistor connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit The pMOS transistor and the nMOS transistor are connected in series between the power supply line and the ground, and further, the pMOS transistor and the nMOS transistor
A CMOS semiconductor device, wherein a potential of a common connection portion with a transistor is an input of the first inverter. 4. The CMOS semiconductor device according to claim 2, wherein the test circuit includes a two-input NAND circuit connected to the second data input terminal and the test signal input terminal;
A pMOS transistor connected to an output terminal of the two-input NAND circuit and driven by an output of the two-input NAND circuit; a two-input AND circuit connected to the first data input terminal and the test signal input terminal; An nMOS transistor connected to the output terminal of the two-input AND circuit and driven by the output of the two-input AND circuit, wherein the pMOS transistor and the nMOS transistor are connected in series between the power supply line and ground; Further, the pMOS transistor and the nMOS
A CMOS semiconductor device, wherein a potential of a common connection portion with a transistor is an input of the first inverter.