JP3076267B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for initializing the same, and more particularly, to a semiconductor integrated circuit having an SRAM and capable of easily measuring a quiescent power supply current between a power supply and a ground, and an initializing method thereof. It is related to the conversion method.

[0002]

2. Description of the Related Art As semiconductor integrated circuits have become larger in scale, it has become difficult to realize test vectors for achieving a high fault detection rate. Therefore, in order to facilitate the test, recently, a built-in self-test B including a test data generation circuit and a test result determination circuit in a semiconductor integrated circuit has been previously prepared.
How to incorporate IST (Built-in Self Test), SC
Design for facilitating test using an AN or the like has been performed. On the other hand, a method of detecting a failure by measuring a quiescent power supply current between the power supply VDD and GND in each node of the circuit in an “L” or “H” state has also become important.

Here, a method of measuring the power supply current and how to increase the failure detection rate will be described with reference to FIG.
FIG. 5A shows a measurement circuit diagram for measuring a power supply current as an example. In the figure, 12 is a voltage source,
11 is an ammeter. The semiconductor integrated circuit 10 has memory circuits 13, 14, 15, 16 and a logic circuit 17 mounted thereon. Here, the defects 18 and 19 are manufacturing defects on the logic circuit 17 and the memory circuit 16 of the semiconductor integrated circuit 10, respectively, and usually, an operation function test (function test)
Thus, a failure can be detected.

However, if the manufacturing defect is a high-resistance short-circuit defect, the function test is passed and no failure can be detected. However, it is possible to detect a fault location by measuring the quiescent power supply current between the power supply VDD and GND. FIG. 5B is a circuit diagram assuming that there is a short failure of the high resistance 23 caused by the defect 18 at the output stage of the two-input NAND circuit 22 of the logic circuit 17. If the power supply current is measured in a state where “H” is input and “L” is output to the terminal C, the failure can be detected because the measured current becomes larger than usual. As described above, by activating the fault location, the fault detection rate can be increased. The same applies to the defect 19 on the memory circuit 13.

However, with the recent increase in the scale of semiconductor integrated circuits, especially with the increase in memory capacity, a huge number of test vectors are required for initial setting, and this reduction is urgently required. An example of a circuit that efficiently sets a memory cell of a memory circuit to “L” or “H” to meet this need is:
It is described in JP-A-1-113995. FIG. 6 shows a circuit diagram described in the publication. As shown in the figure, this memory cell includes inverters INV1a, INV2a and a capacitor CV.
1 and C2 and N-type MOS transistors Q1 and Q2. Here, the gate dimensions of the inverters INV1a, 2a are made different from each other or the capacitances C1, C2 are changed.
Are different, there is a difference in the rise of the voltage at the connection points X and Y after the power is supplied, and it can be determined to be a predetermined “L” or “H”.

Further, another conventional example of a circuit for efficiently setting a memory cell of a memory circuit to "L" or "H" is described in JP-A-8-221985. FIG. 7 shows a circuit diagram of a memory circuit described in the publication. As shown in the figure, this memory cell is configured such that the sources of the inverters INV1a and INV2a and the sources of the inverters INV1a and INV2a are connected to a terminal 1
a, 1b, 2a and 2b. Here, only the terminal 1a is made independent of the normal VDD, a voltage is normally applied as the VDD terminal, and a GND level potential is applied only when it is desired to set the value of the memory cell. When the GND level is applied, the output of the inverter INV1a becomes "L" state, whereby the output of the inverter INV2a becomes "H".
State.

Another conventional example of a circuit for efficiently setting a memory cell of a memory circuit to "L" or "H" is described in Japanese Patent Application Laid-Open No. 6-84368. FIG. 8 shows a circuit diagram of a memory circuit described in the publication. As shown, the memory cell includes inverters INV1a, INV2a and N
It consists of type MOS transistors Q1 and Q2, P-type MOS transistors P1 and P2, and a gate input terminal I of P-type MOS transistors P1 and P2. Here, when the terminal I is set to the GND level with the N-type MOS transistors Q1 and Q2 turned off, the P-type MOS transistors P1 and P2 are turned on.
As a result, the output of the inverter INV1a becomes "H" state, and the output of the inverter INV1b becomes "L" state.

[0008]

As described above, as the memory circuit scale increases, it takes time to set L or H because it is necessary to run test vectors for the memory capacity in the method of selecting and writing addresses. Will be. In the memory cell shown in FIG. 7, since the source of one inverter of the memory cell is separated from the normal power supply and treated as a signal, the memory cell is provided with a source power supply for one inverter and a normal power supply for the other. Required and the memory cell size increases. The use of multi-layer wiring may not increase the memory cell size, but is limited by the need for multi-layers.

FIG. 8 requires a control signal terminal for controlling ON / OFF of the transistor for initial setting of the prior art shown in FIG. 7, and transmits a control signal to a memory cell. The wiring increases the memory cell size.

An object of the present invention is to provide a semiconductor integrated circuit which does not increase the memory size and does not need to run a test vector corresponding to the memory capacity at the time of fault detection, and an initialization method thereof.

[0011]

In order to solve the above-mentioned problems, the present invention employs the following means. In the semiconductor integrated circuit according to the present invention, the output of the first inverter circuit formed by complementarily connecting the first conductivity type MOSFET and the second conductivity type MOSFET is used to complement the first conductivity type MOSFET and the second conductivity type MOSFET. A memory circuit in which a memory cell configured as an input of a second inverter circuit formed by connection and an output of the second inverter circuit as an input of the first inverter circuit is arranged in a row and column direction. In the semiconductor integrated circuit having the first resistance element,
The output of the first inverter circuit and the first conductivity type MO
And a second resistance element connected in series between the SFET and the SFET.
The output of the second inverter circuit and the second conductivity type MO
It is characterized in that it is connected in series with the SFET.
You .

With the above configuration, if the power supply voltage is changed beyond the operating power supply voltage range by using the method for initializing a semiconductor integrated circuit according to the present invention, the memory circuit is set to "L" or "H". Since the state can be set and the test vectors for the memory capacity do not need to be run, no time is required for the setting.

[0013]

[0014]

[0015] More preferably, the resistance element has a resistance value which is higher by one to two digits than the on-resistance value of each transistor constituting the inverter circuit.

According to the above configuration, it is easy to set the memory circuit to the "L" or "H" state by changing the power supply voltage applied to the semiconductor integrated circuit beyond the operating power supply voltage range. .

[0017]

[0018]

[0019]

Embodiments of the present invention will be described with reference to the drawings.

The memory cell of the present invention has a configuration in which a resistance element is inserted into a normal memory cell. The connection position of the resistance element is provided between the connection of the N-type MOS transistor and the P-type transistor so that the output of the inverter is easily determined to be "L", and the output is taken out from between the N-type MOS transistor and the resistance element. On the other hand, the output is taken out from between the resistance element and the P-type MOS transistor so that the other inverter can be easily determined to be “H”. Next, an example of the resistance value of the resistance element will be described. FIG. 4 shows numerical values obtained by the circuit simulation SPICE. 3K-20
The operation of the invention was confirmed within the range of K ohms. The power supply voltage at that time fluctuated from 1.5 V to 6.5 V, and a potential difference of about 5.0 V was required. Note that the variation range of the resistance value and the power supply voltage can be changed according to the gate length size and the gate width size of the inverter of the memory cell, or manufacturing conditions.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a first embodiment showing a semiconductor integrated circuit having a memory circuit according to the present invention. As shown in FIG. 1, this memory circuit comprises N-type MOS transistors (first conductivity type MOSFETs) N1, N2 and P
MOS transistor (second conductivity type MOSFET) P
1 and P2 to form an inverter circuit INV1a and a second inverter circuit INV2a, and an N-type MO having terminals IN_1 and IN_2 as inputs.
In this configuration, S transistors N3 and N4 are arranged, and a resistance element R is connected between an N-type MOS transistor and a P-type MOS transistor constituting the inverter.

Next, the operation of the memory circuit of FIG. 1 will be described with reference to the drawings. FIG. 2 is a timing chart for explaining the circuit operation of FIG. 0V power supply voltage VDD
To a voltage within the operation guarantee range. For example, this voltage value is 3.3V. Here, the output of the inverter of the memory cell changes from OUT_1 to “L” level and OUT_2 to “H” level due to the influence of the resistance element R. Here, a normal memory cell writing procedure is performed, and IN_1 is input at “H” level so that OUT_1 is at “H” level and OUT_2 is at “L” level.
"H" level is also input. At this time, the “L” level is input to IN_2. After the writing time of the value of the memory cell has elapsed, IN_2 is set to the “L” level at timing t3, and IN_3 is set to the “L” level at t4, thereby completing the memory cell writing T2.

Thereafter, a reset T3 of the memory cell is performed due to the fluctuation of the power supply voltage. Timing t5, t6, t
It is an example that the voltage is increased from the side where the voltage is increased at timings of changing the number of times t7 and t8, and the timing t5. Therefore, another combination may be used as long as the following conditions are satisfied for the fluctuation of the power supply voltage.

One of the necessary conditions for the fluctuation of the power supply voltage is that the upper and lower limits of the power supply voltage do not exceed the absolute maximum rated power supply voltage of the semiconductor integrated circuit, and the other is the operation of the logic circuit of the present invention. This is to fluctuate beyond the power supply voltage range. As long as these two conditions are satisfied, the range of fluctuation of the power supply voltage may be any voltage.

When the power supply is changed from the high potential to the low potential at the timing t6, the potential of OUT_1 in the "H" state drops to near 0V, and the difference from the potential of OUT_2 in the "L" state decreases. . When the power supply voltage is changed from the low potential to the high potential at the state timing t7, OUT_2
Rises to the “H” side under the influence of the power supply voltage change,
Further, the potential difference between OUT_1 and OUT_2 becomes smaller.
Here, the rise of the voltage of OUT_1 is slowed by the resistor attached to the P-type MOS side, and the voltage drop of OUT_2 is slowed by the resistor attached to the N-type MOS side. Rises to a potential that goes to “H” level, and OUT_1 falls to a potential that goes to “L” level.

Next, a second embodiment of the present invention is shown in FIG. In the first embodiment, the first inverter circuit INV1
a and the second inverter circuit INV2a, the N-type MOS transistor and the P-type MO
Although the resistance element R is connected between the S transistors, in this embodiment, the second inverter INV2a
Is formed by connecting a resistance element R only between the N-type MOS transistor and the P-type MOS transistor.

According to this configuration, the power supply voltage VDD is set to 0.
When the voltage is changed from V to a voltage within the operation guarantee range, the output of the inverter of the memory cell becomes OUT_
1 goes to the “L” level, and accordingly OUT_2 changes to the “H” level.

[0028]

As described above, according to the present invention,
By changing the power supply voltage beyond the power supply voltage range in which the operation of the semiconductor integrated circuit is guaranteed, “L” or “H” of the memory circuit is changed.
Since the state can be set and the logic of the logic circuit can be maintained as it is when the power supply voltage fluctuates, it is not necessary to run the test vectors corresponding to the memory capacity, and the setting does not take much time. In addition, it can be realized without the necessity of separating the power supply from a normal power supply, and the ON / OFF of the transistor can be realized.
Therefore, there is no need for a control signal terminal for performing the above operation, so that it is not necessary to increase the memory cell size and to use a multilayer wiring.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit shown in FIG. 1;

FIG. 3 is an example of a simulation result of obtaining a resistance value and a power supply voltage range of a resistance element realizing the present invention.

FIG. 4 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 5A is a diagram illustrating a method of measuring a static power supply current, and FIG. 5B is a diagram illustrating a method of measuring a manufacturing defect in a process.

FIG. 6 is a diagram showing a conventional memory circuit.

FIG. 7 is a diagram showing a conventional memory circuit.

FIG. 8 is a diagram showing a conventional memory circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor integrated circuit 11 Ammeter 12 Voltage source 13, 14, 15, 16 Memory circuit 17 Logic circuit 18 Manufacturing defect 19 Manufacturing defect 20 Power supply voltage wiring 21 GND wiring 22 2-input NAND circuit 23 High resistance manufacturing defect N1, N2 N3 N-type MOS transistors P1, P2, P3 P-type MOS transistor VDD Power supply voltage terminal R Resistance INV1a First inverter circuit INV2a Second inverter circuit Q1, Q2 N-type MOS transistors P1, P2 P-type MOS transistors I P1, P2 Line signal terminal for controlling the initial setting W for controlling Q1 and Q2

Claims (2)

(57) [Claims] 1. A first conductivity type MOSFET and a second conductivity type M
An output of a first inverter circuit formed by complementarily connecting an OSFET and a first conductivity type MOSFET and a second conductivity type M
A memory cell configured as an input of a second inverter circuit formed by complementarily connecting an OSFET and an output of the second inverter circuit as an input of the first inverter circuit is arranged in the row and column directions. In a semiconductor integrated circuit having a memory circuit, a first resistance element is connected in series between an output of the first inverter circuit and the first conductivity type MOSFET, and a second resistance element is 2. A semiconductor integrated circuit, which is connected in series between the output of the second inverter circuit and the second conductivity type MOSFET. 2. The method according to claim 1, wherein the resistance element is one digit to two digits smaller than an on-resistance value of each transistor constituting the inverter circuit.
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit has an order of magnitude higher resistance.