JPH0697389A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit having sense amps in which erroneous function due to fluctuation of device characteristics is prevented within an operation guaranteed power supply voltage range. CONSTITUTION:An L level signal is inputted to a control signal input terminal CNT at the time of data read out. If an L(H) level signal is inputted to a data input terminal DIN at that time, potential at node N1 goes L(H). Potential at the output terminal DOUT of a sense amp is determined by the ratio of transconductance between a p-channel transistor Qp3 having gate connected with the node N1 and a transistor selected from n-channel transistors Qn21, Qn22, Qn23 having different sizes. A voltage reference is applied on each transistor from a test circuit 10 and a transistor producing optimal results is selected while drain wirings (11a, 11b, 11c) are disconnected for other transistors.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit having a sense amplifier, and more particularly to a mutual inductance ratio between a transistor to which a voltage corresponding to stored data is applied and a transistor to which a reference voltage is applied. The present invention relates to a semiconductor integrated circuit having one or more sense amplifiers of a type determined by.

[0002]

2. Description of the Related Art In a conventional sense amplifier of this type, as shown in FIG. 3, a control signal input terminal CNT is connected to an inverter IV1 having an input terminal connected thereto, and a first input terminal is connected to a control signal input terminal CNT. , A two-input NOR gate NR having a second input terminal connected to the data input terminal D _IN , a gate at the output terminal of the inverter IV1, and a source at the power supply V
_A first p-channel transistor Qp1 having a drain connected to the node N1 and a gate and a drain connected to the node N1
A second p-channel transistor Qp2 whose source is connected to the power supply V _DD , and a third p-channel transistor Qp2 whose gate is connected to the node N1, whose source is connected to the power supply V _DD and whose drain is connected to the output terminal D _OUT .
P-channel transistor Qp3 and the gate has 2 inputs N
The output terminal of the OR gate NR, the source is the data input terminal D _IN , the drain is the first n-channel transistor Qn1 connected to the node N1, the gate is the reference voltage input terminal REF, and the drain is the output terminal D _OUT . A second n-channel transistor Qn2 connected to the source and grounded
It consists of and.

Next, the operation of this conventional example will be described with reference to the timing chart of FIG. When reading the data stored in the memory, first, the control signal input terminal CNT is set to the high level (time t ₁ ). As a result, the node N2 connected to the output terminal of the 2-input NOR gate and the node N3 connected to the output terminal of the inverter IV1 become low level, turning off the transistor Qn1 and turning on the transistor Qp1.

Next, a low level signal is input to the control signal input terminal CNT (time t ₂ ). At this time, if the signal applied to the data input terminal D _IN connected to the memory cell is low level, the node N2 becomes high level and the transistor Qn1 is turned on. Further, since the node N3 becomes high level, the transistor Qp1 is turned off, and the node N1 has a potential sufficiently lower than the power supply potential V _DD . Here, if the potential of the reference voltage input terminal REF is set high enough to turn on the n-channel transistor Qn2, the transistors Qp3 and Qn2 turn on. Therefore, the potential of the output terminal D _OUT is determined by the mutual conductance of both transistors. When a low level signal is input to the data input terminal D _IN , the node N
Since the potential of 1 becomes a low potential that strongly turns on the transistor Qp3, the potential of the output terminal D _OUT becomes high level.

At time t ₃ , the control signal input terminal CN
The signal applied to T becomes high level again, and the state of the sense amplifier becomes similar to that at time t ₁ .

Then, at time t ₄ , when the signal applied to the control signal input terminal CNT becomes low level, the node N3
Becomes high level and the transistor Qp1 is turned off. Here, _assuming that the signal at the data input terminal D _IN is at high level, the potential at the node N2 becomes low level and the transistor Qn1 is turned off. As a result, the potential of the node N1 becomes V _T , where V _T is the threshold voltage of the transistor Qp2.
_DD − | V _T |. This voltage weakly turns on the transistor Qp3. On the other hand, the transistor Qn2 whose gate is supplied with the reference voltage has a relatively low resistance and is turned on. Therefore, the transistor Qp3 and the transistor Qn2
Output terminal D _OUT determined by the ratio of the mutual conductance of
Potential becomes low level.

As described above, the output terminal D of the sense amplifier
The potential of _OUT is determined by the ratio of the mutual conductances of the p-channel transistor Qp3 and the n-channel transistor Qn2, so that the gate length and gate width of these transistors become high and low level output values to predetermined values. Set to size. The manufacturer must guarantee the normal operation of the sense amplifier over the guaranteed operating power supply voltage.

[0008]

In the conventional semiconductor integrated circuit described above, the transconductance of the transistor deviates from the set value due to variations in ion implantation and heat treatment in the diffusion process, so that the power supply voltage range in which the sense amplifier normally operates is limited. Change. As a result, there arises a problem that the normal operation of the sense amplifier cannot be ensured within the guaranteed power supply voltage range.

[0009]

In a semiconductor integrated circuit of the present invention, a first transistor (Qp ₃ ) to which a voltage corresponding to stored data of a memory cell to be read is applied, and the first transistor are connected in series. One or a plurality of sense amplifiers each having a second transistor connected to the gate to which a reference voltage is applied, the first amplifier comprising:
Alternatively, the second transistor is selected from a plurality of transistors (Qn ₂₁ , Qn ₂₂ , Qn ₂₃ ) having different sizes.

[0010]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1A is a circuit diagram showing a first embodiment of the present invention, and FIG. 1B is a partial layout diagram on the chip. In FIG. 1 (a), the same parts as those of the conventional example of FIG. 4 are designated by the same reference numerals, and a duplicate description will be omitted.

In this embodiment, the n-channel transistor Q
Instead of n2, three n-channel transistors Qn ₂₁ , Qn
n ₂₂ and Qn ₂₃ are connected in parallel between the output terminal D _OUT and the ground. A reference voltage is applied from the test circuit 10 to the gates of these transistors.

FIG. 1B shows transistors Qn _{21 to} Qn.
It is a layout diagram of a portion of n ₂₃ . In the figure, 11
Is an output wiring having drain wirings 11a to 11c, 12
Is a ground wiring, 13a to 13c are gate electrodes, and 14a to 1
Reference numeral 4c is a diffusion layer forming a source / drain.

In this embodiment, three transistors Q are used.
Any one of n ₂₁ , Qn ₂₂ , and Qn ₂₃ is selected and used. As shown in FIG. 1B, the transistor Qn ₂₁ has the shortest gate width and the transistor Qn ₂₃ has the longest gate width. Therefore, the on-resistances of these transistors are maximum in the transistor Qn ₂₁ and minimum in the transistor Qn ₂₃ . Therefore, the potential of the output terminal D _OUT of the sense amplifier becomes the highest when the transistor Qn ₂₁ is selected, and becomes the lowest when the transistor Qn ₂₃ is selected.

At the time of product inspection on a wafer, the test circuit 10 switches so that the reference voltage is supplied to one of the n-channel transistors Qn ₂₁ , Qn ₂₂ , and Qn ₂₃ , and the reference voltage is supplied to each transistor. Measure the range of operable power supply voltage for the case. Measurement results, for example, a range of acceptable power supply voltage when using a transistor Qn ₂₁ is 3 to 7 V, the range of acceptable supply voltage when using a transistor Qn ₂₂ is 4.5 to 8.5
V, when the allowable power supply voltage range when using the transistor Qn _{23 is 5} to 9 V, and if the product operation guaranteed power supply voltage range is 4 to 6 V, in order to guarantee the operation of the sense amplifier, n-channel It is best to choose the transistor Qn ₂₁ .

When it is judged that the selection of the transistor Qn ₂₁ is optimum, the drain wiring 1 in FIG.
1b and 11c are cut by a laser trimmer. Similarly, when the transistor Qn ₂₂ or Qn ₂₃ is determined to be optimal, the drain wirings 11a, 11c or 11a, 1
Cut 1b. As a result, even if the transistor characteristics deviate from the designed values due to variations in the manufacturing process, the sense amplifier can always operate normally within the operation-guaranteed power supply voltage range.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. In this embodiment, the n-channel transistor Qn
Nodes N ₄₁ , N ₄₂ , and N ₄₃ to which the respective gates of ₂₁ , Qn ₂₂ , and Qn ₂₃ are connected are transfer gates T ₁₁ ,
It is connected to the reference voltage output terminal of the test circuit 10 via T ₁₂ and T ₁₃ , and also n-channel transistors Qn ₃₁ and Qn are connected.
It is grounded via n ₃₂ and Qn ₃₃ . The control gates of the transfer gates T ₁₁ , T ₁₂ , T ₁₃ are connected to the output terminals 15a, 15b, 15c of the non-volatile memory circuit 15, and these output terminals 15a, 15b, 15c are also connected.
Is connected to the gates of the transistors Qn ₃₁ , Qn ₃₂ , Qn ₃₃ via the inverters IV ₂₁ , IV ₂₂ , IV ₂₃ .

In product inspection on a wafer,
Channel transistor Qn_{twenty one}Is determined to be the best choice
In case of the non-volatile memory circuit 15, the output terminal 15a is
I level, low level output to output terminals 15b and 15c
Write the data as described. This makes the transformer
Fagate T₁₁Is on, transfer gate T₁₂, T ₁₃
Turn off. Inverter IV_{twenty one}Output of Lorebe
LE, inverter IV_{twenty two}, IV_{twenty three}Output is high level
N-channel transistor Qn₃₁Off, n channel
Transistor Qn₃₂, Qn₃₃Turns on. Therefore, the section
Point N₄₁Potential becomes the same as the reference voltage potential, and the node N
₄₂, N₄₃Potential becomes low level. Therefore, n channel
Lu transistor Qn_{twenty two}, Qn_{twenty three}Off and n channel
Langista Qn_{twenty one}Can be selected.

The preferred embodiment has been described above.
The present invention is not limited to these examples, and various modifications can be made. For example, instead of cutting the drain wiring by the laser trimmer in the embodiment of FIG. 1, it is possible to cut the drain wiring by a transfer gate to continue the connection. Also, instead of forming a plurality of n-channel transistors, a p-channel transistor Qp3 is formed.
It is also possible to prepare a plurality of transistors having different sizes in the place where is used and select one of them.

[0019]

As described above, according to the present invention, the first transistor to which the voltage corresponding to the stored data of the memory cell to be read is applied and the second transistor to which the reference voltage is applied are connected in series. In this case, the first or second transistor can be selected from a plurality of transistors having different sizes. Therefore, according to the present invention, the characteristics of the device can be changed due to variations in ion implantation and heat treatment during the manufacturing process. It is possible to select the transistor having the optimum characteristic even when the value fluctuates, and it is possible to operate the sense amplifier normally within the operation guaranteed power supply voltage range.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention and a partial layout diagram thereof on a chip.

FIG. 2 is a circuit diagram of a second embodiment of the present invention.

FIG. 3 is a sense amplifier circuit diagram of a conventional example.

FIG. 4 is a timing chart of a conventional sense amplifier.

[Explanation of symbols]

CNT control signal input terminal D _IN data input terminal D _OUT output terminal of sense amplifier Qn1, Qn2, Qn ₂₁ , Qn ₂₂ , Qn ₂₃ , Qn ₃₁ , Qn
n ₃₂ , Qn ₃₃ n-channel transistor Qp1, Qp2, Qp3 p-channel transistor REF reference voltage input terminal 10 test circuit 11 output wiring 11a, 11b, 11c drain wiring 12 ground wiring 13a, 13b, 13c gate electrode 14a, 14b, 14c diffusion Layer 15 Non-volatile memory circuit

Claims (1)

[Claims] 1. A first transistor (Qp ₃ ) to which a voltage according to stored data of a memory cell to be read is applied.
And a second transistor connected in series with the first transistor and having a gate to which a reference voltage is applied, the semiconductor integrated circuit having one to a plurality of sense amplifiers. Is a transistor selected from a plurality of transistors (Qn ₂₁ , Qn ₂₂ , Qn ₂₃ ) having different sizes from each other.