JP4992838B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier suitable for an IDDQ test.

  An IDDQ test is used as one of testing methods for a semiconductor integrated circuit (IC). In this IDDQ test, a test pattern is sequentially input to an input terminal of an IC to be tested, an IC input / output or an internal logic state is set to a steady state, and a power supply current (IDDQ current) in the steady state is measured. Is the method. When the IC has a CMOS configuration, the IDDQ current becomes extremely small (for example, several μA to several tens μA) if it is normal. On the other hand, if there is a defect or failure during manufacture, the IDDQ current becomes abnormally large (for example, several hundred μA to several tens mA). Since the IDDQ current can be easily observed as the power supply current, it is possible to determine and eliminate defective products.

  However, when an operational amplifier or a comparator is formed in the IC together with a logic circuit, it is necessary to pass a bias current in order to operate the differential amplifier circuit. Since this bias current is larger than the leak current of CMOS, the IDDQ test is hindered. To cope with this, it is conceivable to set the standard value exceeding the bias current and perform the IDDQ test, but it becomes impossible to detect a failure with a minute leak.

Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique for performing an IDDQ test by stopping the operation of a differential amplifier circuit to cut off a bias current. The input buffer circuit (actually a comparator) described in Patent Document 1 includes an input switching circuit that selects either an input signal or an output signal of a differential amplifier circuit and outputs the selected signal to an internal circuit. The IDDQ test At that time, the bias current of the differential amplifier circuit is stopped and the output node of the differential amplifier circuit is fixed to the ground potential. The input switching circuit selects an input signal that bypasses the differential amplifier circuit and outputs the selected signal to the next stage, thereby preventing the output logic of the input buffer circuit from being fixed and enabling the use of the conventional test pattern. .
Japanese Patent Laid-Open No. 11-202029

  As described above, Patent Document 1 describes a configuration in which the operation of a target circuit (comparator) is completely stopped during an IDDQ test, and an input signal is bypassed through the entire target circuit and given to the next stage. However, when an IC including an operational amplifier is subjected to an IDDQ test using this configuration, failure detection cannot be performed for the entire operational amplifier including a differential amplifier circuit, a buffer circuit, an output circuit, etc., and the failure detection rate is lowered. .

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an operational amplifier with an improved failure detection rate in an IDDQ test.

  According to the means described in claim 1, the operational amplifier is configured by sequentially connecting a differential amplifier circuit, an amplifier circuit, and a buffer circuit. Among these, the differential amplifier circuit includes a differential input transistor pair, an active load, and a first transistor that operates as a constant current circuit. The amplifier circuit includes a second transistor having a control terminal connected to the output node of the differential amplifier circuit and a third transistor operating as a constant current circuit between the first and second power supply lines across the intermediate output node. It is equipped with the structure connected to. The buffer circuit can have various circuit configurations including transistors, and receives the voltage of the intermediate output node.

  In the IDDQ test state, the test control circuit turns off the first, second, and third transistors, so that no bias current flows through the operational amplifier. Then, since a voltage corresponding to the inverted or non-inverted differential input voltage is applied to the intermediate output node of the amplifier circuit, the buffer circuit performs the buffer operation by inputting the voltage. That is, this means does not stop the operation of the entire operational amplifier during the IDDQ test, but maintains the buffer circuit in an operable state. Since a voltage corresponding to the differential input voltage is applied to the intermediate output node in the operational amplifier, the second and third transistors and the buffer circuit constituting the amplifier circuit are also defective based on the power supply current during the IDDQ test. And failure can be detected. Thereby, the failure detection rate in the IDDQ test can be increased.

  According to the means described in claim 2, the test control circuit includes a first transistor, a fourth transistor connected between the first power supply line and the control terminal of the second transistor, and an intermediate output node. Complementary logic circuits having fifth and sixth transistors connected between the second power supply lines, and seventh and eighth transistors connected in series with the fifth and sixth transistors, respectively.

  In the IDDQ test state, the first and third transistors are turned off, the fourth, seventh and eighth transistors are turned on, and the complementary logic circuit is operated according to the inverted or non-inverted differential input voltage. Let Thereby, the voltage of the intermediate output node can be changed according to the inverted or non-inverted differential input voltage, and the second and third transistors and the buffer circuit can be inspected by various test patterns. On the other hand, in the normal operation state, the first and third transistors are operated as a constant current circuit and the fourth, seventh, and eighth transistors are turned off, so that the normal operation of the operational amplifier is not hindered.

  According to the means described in claim 3, the test control circuit includes a fourth transistor connected between the first power supply line and the control terminal of the second transistor, and an inverting or non-inverting differential input. A switch circuit connected between the voltage input node and the intermediate output node is provided. In the IDDQ test state, the first and third transistors are turned off, and the fourth transistor and the switch circuit are turned on. Thereby, the voltage of the intermediate output node can be changed according to the inverted or non-inverted differential input voltage, and the second and third transistors and the buffer circuit can be inspected by various test patterns. On the other hand, in the normal operation state, the first and third transistors are operated as a constant current circuit and the fourth transistor and the switch circuit are turned off, so that the normal operation of the operational amplifier is not hindered.

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a configuration diagram of an operational amplifier formed in an IC having a CMOS structure. The operational amplifier 1 operates by receiving the supply voltage VDD from the power supply lines 2 and 3 (corresponding to the first and second power supply lines). The operational amplifier 1 includes a first-stage differential amplifier circuit 4, an intermediate-stage amplifier circuit 5 and An output stage buffer circuit 6 is connected in order. In addition to the operational amplifier 1, a logic circuit is formed in the IC.

  The differential amplifier circuit 4 includes N-channel FETs 7 and 8 (corresponding to a differential input transistor pair) to which inverted and non-inverted differential input voltages Vinm and Vinp are applied, and between the power supply line 2 and the FETs 7 and 8, respectively. It is composed of connected P-channel FETs 9 and 10 (corresponding to an active load), an N-channel FET 11 connected between a common source of the FETs 7 and 8 and the power supply line 3. The FET 11 operates as a constant current circuit with a bias voltage applied to the gate during normal operation, and is turned off by applying 0 V (L level) to the gate during the IDDQ test (stationary power supply current measurement test). It is supposed to be.

  The amplifier circuit 5 has a configuration in which a P-channel FET 12 and an N-channel FET 13 (corresponding to second and third transistors) are connected between power supply lines 2 and 3 with an intermediate output node Nc interposed therebetween. The gate (control terminal) of the FET 12 is connected to the output node of the differential amplifier circuit 4. Like the FET 11, the FET 13 operates as a constant current circuit during normal operation, and is turned off during the IDDQ test.

  The buffer circuit 6 is configured as a push-pull circuit (not shown) including, for example, a P-channel FET and an N-channel FET connected between the power supply lines 2 and 3, and receives the voltage of the intermediate output node Nc. And output the voltage Vo.

  Further, the operational amplifier 1 includes a test control circuit 14 for executing the IDDQ test. The test control circuit 14 has a signal CUTP that is H level during normal operation and L level during an IDDQ test, L level during normal operation, a signal CUTN that is H level during an IDDQ test, and gate voltages ( Bias voltage or 0V) is generated. The test control circuit 14 has the following circuit configuration.

  A P-channel FET 15 (corresponding to a fourth transistor) is connected between the power supply line 2 and the gate of the FET 12, and the signal CUTP is supplied to the gate. P-channel FETs 16 and 18 are connected in series between the power supply line 2 and the intermediate output node Nc, and N-channel FETs 19 and 17 are connected in series between the intermediate output node Nc and the power supply line 3. It is connected.

  Of these, FETs 16 and 17 (corresponding to fifth and sixth transistors) have their gates connected in common to form a complementary logic circuit 20. Signals CUTP and CUTN are applied to the gates of the FETs 18 and 19 (corresponding to seventh and eighth transistors), respectively. The NAND circuit 21 operating with the power supply voltage VDD receives the differential input voltage Vinp and the signal CUTN, and the output signal is given to the complementary logic circuit 20.

Next, the operation and effect of this embodiment will be described.
In the normal operation, the test control circuit 14 sets the signal CUTP to the H level (voltage VDD), the signal CUTN to the L level (0 V), and applies a bias voltage to the gates of the FETs 11 and 13. As a result, the FETs 15, 18, and 19 are turned off, and the output of the NAND circuit 21 becomes constant at the H level. In this state, the test control circuit 14 does not affect the basic operation of the operational amplifier 1, and the differential amplifier circuit 4, the amplifier circuit 5 and the buffer circuit 6 perform normal operations according to the differential input voltages Vinm and Vinp. .

  On the other hand, during the IDDQ test, the test control circuit 14 sets the signal CUTP to the L level and the signal CUTN to the H level, and applies 0 V to the gates of the FETs 11 and 13. In this state, the FETs 11, 12, and 13 are turned off, and the bias current flowing through the operational amplifier 1 is cut off. Since the FETs 18 and 19 are turned on, the complementary logic circuit 20 receives the inverted signal of the non-inverted differential input voltage Vinp, inverts the logic, and outputs it to the buffer circuit 6 through the intermediate output node Nc. That is, the non-inverted differential input voltage Vinp is binarized and applied to the intermediate output node Nc while maintaining the same phase logic.

  As a result, the IDDQ test can be performed while inputting a test pattern to the non-inverting input node and passing the test pattern from the intermediate output node Nc inside the operational amplifier 1 to the buffer circuit 6. During the IDDQ test, the FET 11 is turned off, and the drains of the FETs 8 and 10 are short-circuited to the power supply line 2 via the FET 15. There is. For example, a short circuit between each drain and source of the FETs 7 to 11 cannot be detected.

  On the other hand, for the amplifier circuit 5 and the buffer circuit 6, it is possible to detect short-circuit faults in most FETs. Specifically, a short circuit between the gates and the sources of the FETs 12 and 13 cannot be detected. Short-circuit faults between terminals can be detected. The power supply current (IDDQ current) of IC1 is monitored, and when the current value exceeds a specified value, it may be determined as abnormal. Here, the short-circuit fault includes a resistive leak fault. How much leak failure can be detected differs depending on the specified value of the IDDQ test.

  As described above, the operational amplifier 1 of the present embodiment cuts off the bias current during the IDDQ test, but maintains a part of the circuit in an operable state, unlike the prior art. That is, the buffer circuit 6 in the operational amplifier 1 is maintained in the operating state, and the non-inverted differential input voltage Vinp is applied to the intermediate output node Nc in the operational amplifier. The intermediate output node Nc is a node whose potential is fixed to the ground in the prior art. By driving the internal node of the operational amplifier 1 with the differential input voltage Vinp as described above, it becomes possible to detect a failure in the intermediate amplification stage and a part of the output stage of the operational amplifier 1 that have been excluded from the failure detection so far. The failure detection rate of the IDDQ test can be increased.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.
FIG. 2 is a configuration diagram of an operational amplifier formed in an IC having a CMOS structure. The same components as those in FIG. 1 are denoted by the same reference numerals, and different portions will be described below.

  The operational amplifier 31 includes a test control circuit 32 for executing the IDDQ test in addition to the differential amplifier circuit 4, the amplifier circuit 5, and the buffer circuit 6. The test control circuit 32 includes the FET 15 described above and the switch circuit 33 connected between the non-inverting input node and the intermediate output node Nc. The switch circuit 33 is a transmission gate formed by an analog switch composed of an N-channel FET and a P-channel FET. The switch circuit 33 is turned off during normal operation when the signal CUTP is H level and the signal CUTN is L level, and the signal CUTP is L level. It turns on at the time of the IDDQ test when the signal CUTN becomes H level.

  During normal operation, the FET 15 and the switch circuit 33 are turned off, and a bias voltage is applied to the gates of the FETs 11 and 13, so that the operational amplifier 31 performs a normal amplification operation. On the other hand, during the IDDQ test, the FET 15 and the switch circuit 33 are turned on. As a result, the FETs 11, 12, and 13 are turned off, and the bias current flowing through the operational amplifier 31 is cut off. Further, the non-inverted differential input voltage Vinp is applied to the intermediate output node Nc via the switch circuit 33. As a result, the test pattern can be input to the non-inverting input node, and the IDDQ test can be performed while passing the test pattern from the intermediate output node Nc inside the operational amplifier 31 through the buffer circuit 6.

  Also according to the present embodiment, most short-circuit faults related to the FETs constituting the amplifier circuit 5 and the buffer circuit 6 can be detected as in the first embodiment. Further, unlike the first embodiment, the non-inverted differential input voltage Vinp can be applied to the buffer circuit 6 as it is without being binarized, so that an IDDQ test is executed using an analog voltage as a test voltage. Can do.

(Other embodiments)
The present invention is not limited to the embodiments described above and shown in the drawings, and can be modified or expanded as follows, for example.
The FETs 16 and 18 may be interchanged and the FETs 19 and 17 may be interchanged.
In each embodiment, the power supply lines 2 and 3 may be the second and first power supply lines, respectively, and the conductivity type of each FET may be switched between the P channel and the N channel. In this case, the signal CUTP is L level and the signal CUTN is H level during normal operation, and the signal CUTP is H level and the signal CUTN is L level during the IDDQ test.

The test control circuit is not limited to the first and second embodiments. In the normal operation state, the FETs 11, 12, and 13 are turned on, and in the IDDQ test state, the FETs 11, 12, and 13 are turned off. Any configuration that provides a voltage corresponding to the differential input voltage to the intermediate output node Nc may be used.
A bipolar transistor may be used instead of the FET. In this case, the control terminal is a base.
The configuration of the buffer circuit 6 is not limited to the push-pull circuit.

Configuration diagram of operational amplifier showing the first embodiment of the present invention FIG. 1 equivalent diagram showing a second embodiment of the present invention

Explanation of symbols

  In the drawing, 1 and 31 are operational amplifiers, 2 and 3 are power supply lines (first and second power supply lines), 4 is a differential amplifier circuit, 5 is an amplifier circuit, 6 is a buffer circuit, and 7 and 8 are FETs (differences). Dynamic input transistor pair), 9, 10 FET (active load), 11 FET (first transistor, constant current circuit), 12 FET (second transistor), 13 FET (third transistor, constant current circuit) Current circuit), 14 and 32 are test control circuits, 15 is an FET (fourth transistor), 16 to 19 are FETs (fifth to eighth transistors), 20 is a complementary logic circuit, 33 is a switch circuit, and Nc Is an intermediate output node.

Claims (3)

A differential input transistor pair to which an inverting and non-inverting differential input voltage is applied, an active load connected between a first power supply line and the differential input transistor pair, and the differential input transistor pair and a second A differential amplifier circuit composed of a first transistor that operates as a constant current circuit with respect to the power supply line;
A second transistor having a control terminal connected to the output node of the differential amplifier circuit and a third transistor operating as a constant current circuit include the first power line and the second transistor across the intermediate output node. An amplifier circuit connected between the power line and
A buffer circuit having the voltage of the intermediate output node as an input;
A test control circuit that turns off the first, second, and third transistors in an IDDQ test state and that supplies a voltage corresponding to the inverted or non-inverted differential input voltage to the intermediate output node; An operational amplifier characterized by that. The test control circuit includes:
A fourth transistor connected between the first power supply line and a control terminal of the second transistor;
A complementary logic circuit having fifth and sixth transistors connected between the first power supply line and the second power supply line across the intermediate output node;
A seventh transistor connected in series with the fifth transistor between the first power supply line and the intermediate output node; and a sixth transistor connected between the intermediate output node and the second power supply line. An eighth transistor connected in series with the transistor;
In the IDDQ test state, the first and third transistors are turned off, the fourth, seventh and eighth transistors are turned on, and the complementary type is selected according to the inverted or non-inverted differential input voltage. The logic circuit is operated, and in the normal operation state, the first and third transistors are operated as a constant current circuit, and the fourth, seventh and eighth transistors are turned off. The operational amplifier according to claim 1. The test control circuit includes:
A fourth transistor connected between the first power supply line and a control terminal of the second transistor;
A switch circuit connected between an input node of the inverting or non-inverting differential input voltage and the intermediate output node;
In the IDDQ test state, the first and third transistors are turned off, and the fourth transistor and the switch circuit are turned on. In the normal operation state, the first and third transistors are used as constant current circuits. 2. The operational amplifier according to claim 1, wherein the operational amplifier is configured to operate and to turn off the fourth transistor and the switch circuit.

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