JP4814614B2 - Semiconductor integrated circuit and inspection method thereof - Google Patents

Description

  The present invention relates to a technique for inspecting connectivity of power supply terminals of a semiconductor integrated circuit.

  Generally, when inspecting a semiconductor integrated circuit, power and signals are supplied from the outside to the terminals of the semiconductor integrated circuit. Since a normal inspection cannot be performed without a connection, this connectivity must first be checked.

  Patent Document 1 discloses a method of measuring a forward current flowing by supplying a built-in voltage to a surge protection diode provided at a power supply terminal or a signal terminal in order to check connectivity.

  In addition, as an inspection method using the same principle, in a recent semiconductor inspection apparatus, a built-in voltage excited at a terminal by connecting a load resistor outside the terminal of the semiconductor integrated circuit and supplying a voltage through the load resistor. A voltage application voltage measurement method for measuring the voltage is known.

In the above method, when the absolute value of the built-in voltage is low, it is possible to determine a short circuit failure between the power source and the ground, and when it is high, an open failure (connection failure).
Japanese Patent No. 3454896 (page 3, FIG. 16)

  However, in the conventional voltage application voltage measurement method, when the connectivity of the power supply terminal of the semiconductor integrated circuit is inspected, not only the forward current of the surge protection diode but also the off-leakage current of the internal circuit flows out. There is a problem that the voltage value measured by the method is significantly lower than the built-in voltage.

  In particular, the problem becomes significant when the Vt of the internal circuit transistor is low as in a recent fine process. In such a case, it is difficult to determine a short circuit failure between the power source and the ground, and there is a problem that the reliability of inspection cannot be obtained.

  FIG. 10 is a diagram showing a configuration of a conventional semiconductor inspection system. In FIG. 10, 100 is a semiconductor inspection system, 101 is a semiconductor integrated circuit, 102 is a power supply terminal, 103 is a ground terminal, 104 is a surge protection diode, 105 is an internal circuit, 106 is an internal power supply line, 107 is an internal ground line, 111 is a semiconductor inspection device, 112 is a load resistance, 113 is a third voltage supply unit, and 114 is a voltmeter.

  Here, the transient response after the voltage is supplied is not considered, and the state when a sufficient time has passed after the voltage supply is considered.

When the potential Vin is applied to the load resistor 112 by the third voltage supply unit 113, the forward current I ₁ of the surge protection diode 104 flows out from the power supply terminal 102, and when the resistance value of the load resistor 112 is R, R × I ₁ occurs, the potential Vm measured by the voltmeter 114 becomes Vin + R × I ₁ . Here, when Vin = −1.5V, R = 1 kΩ, and I ₁ = 0.9 mA, Vm becomes −0.6V.

However, in reality, the potential Vm = Vin + R × (I ₁ + I ₂ ) due to the influence of the off-leakage current I ₂ flowing out from the internal circuit. Here, if I ₂ = 0.6 mA and other parameters are the same as those described above, Vm becomes 0 V, which is the same measured value as when the power source and the ground are short-circuited.

In this example, I ₂ = 0.6 mA is used as an example. However, in recent fine processes, the Vt of the transistor is decreasing more and more, but the circuit scale tends to increase due to the improvement in the degree of integration. It is not uncommon for the off-leakage current of the internal circuit to exceed 1 mA.

  The present invention has been made in view of the above points, and an object of the present invention is to influence the off-leakage current of an internal circuit when the connectivity of a power supply terminal of a semiconductor integrated circuit is tested by a voltage application voltage measurement method. Is to enable a stable inspection.

That is, the semiconductor integrated circuit of the present invention includes a power supply terminal for supplying power,
A ground terminal for supplying a ground potential;
An internal power line connected to the power terminal;
An internal ground wire connected to the ground terminal;
A surge protection circuit connected between the internal power line and the internal ground line;
An internal circuit composed of a group of CMOS transistors and connected between the internal power supply line and the internal ground line;
The internal power line includes a switch circuit that is connected between the surge protection circuit and the internal circuit and has a control terminal connected to the internal ground line or the internal power line. .

The semiconductor inspection system of the present invention includes the semiconductor integrated circuit,
A load resistance connected to the power supply terminal of the semiconductor integrated circuit; a voltmeter for measuring the potential of the power supply terminal; and a voltage supply means connected to the load resistance. And a semiconductor inspection apparatus for inspecting connectivity of power supply terminals of the integrated circuit.

As described above, according to the present invention, without controlling the switching from the external, it is possible to disconnect the power supply terminal or the ground terminal and an internal circuit electrically, the semiconductor integrated circuit with a voltage source voltage measurement method When inspecting the connectivity of the power supply terminals, the influence of the off-leak current of the internal circuit can be eliminated. Thereby, it is possible to prevent a decrease in the measured voltage value without increasing the number of external terminals, and to stabilize the inspection.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The following description of the preferred embodiments is merely exemplary in nature and is in no way intended to limit the invention, its application, or its application.

< Reference Example 1>
FIG. 1 is a diagram showing a configuration of a semiconductor inspection system according to Reference Example 1 of the present invention. In FIG. 1, 1 is a semiconductor inspection system, 11 is a semiconductor integrated circuit, 102 is a power supply terminal, 103 is a ground terminal, 104 is a surge protection diode, 15 is an internal circuit composed of CMOS, 106 is an internal power supply line, 107 Is an internal ground line, 18 is a first substrate potential supply terminal for supplying a PMOS substrate potential, 19 is a second substrate potential supply terminal for supplying an NMOS substrate potential, 21 is a semiconductor inspection device, and 112 is a load. A resistor, 113 is a third voltage supply unit, 114 is a voltmeter, 25 is a first voltage supply unit, and 26 is a second voltage supply unit.

I ₁ is a forward current of the surge protection diode 104, I ₂ is an off-leakage current from the internal circuit 15, Vdp is a potential applied to the first substrate potential supply terminal 18, and Vdn is a second substrate potential supply terminal 19. , Vin is a potential supplied from the third voltage supply unit 113, and Vm is a potential of the power supply terminal 102.

  The operation of the semiconductor inspection system 1 shown in FIG. 1 will be described below. First, the potential Vdp is applied from the first voltage supply unit 25 to the first substrate potential supply terminal 18, while the potential Vdn is applied from the second voltage supply unit 26 to the second substrate potential supply terminal 19.

  Further, the potential Vin is given from the third voltage supply unit 113 to the load resistor 112 with respect to the ground reference. At this time, the potential Vin is applied so that the surge protection diode 104 is forward biased. For example, when the ground reference is 0V, Vin = −1.5V.

  The potential Vdp is given so as to satisfy the relationship Vin <Vdp so that the PMOS transistor substrate is reverse-biased. For example, Vdp = 0V.

  The potential Vdn is applied so that the NMOS transistor substrate is reverse-biased with respect to the ground potential. For example, Vdn = −1.5V.

In such a state, the transistor substrate of the internal circuit 15 is reverse-biased, and the off-leakage current I ₂ is smaller than the forward current I ₁ of the surge protection diode 104.

Therefore, it flows current to the power supply terminal 102, becomes forward current _{I 1} is dominant, so that the potential Vm of the power supply terminal 102 satisfy the relation: Vm = Vin + R × _{I 1,} near the built-in voltage of the surge protection diode 104 Will stabilize. For example, when R = 1 kΩ and I ₁ = 0.7 mA, Vm = −0.8V.

As described above, according to the semiconductor inspection system according to the first reference example , the connectivity of the power supply terminal 102 can be inspected by measuring the potential Vm with the voltmeter 114, and the off-leak from the internal circuit 15 as in the prior art. avoiding Vm due to the influence of the current I ₂ is the problem decreases, inspection can be performed, such as performing the power-ground short circuit determination stably even.

In the first reference example , a semiconductor integrated circuit device in which a semiconductor integrated circuit is assembled into a package may be used instead of the semiconductor integrated circuit. This also applies to the following embodiments.

In the first reference example , the semiconductor inspection device includes a semiconductor integrated circuit or an inspection jig (for example, a probe card or a performance board) for connection to the semiconductor integrated circuit device. This also applies to the following embodiments.

< Reference Example 2>
FIG. 2 is a diagram showing a configuration of a semiconductor inspection system according to Reference Example 2 of the present invention. Since the difference from the reference example 1 is that a voltage control unit for controlling the voltage based on the control signal output from the voltmeter is provided, hereinafter, the same parts as those in the reference example 1 are denoted by the same reference numerals. Only the differences will be described. The same applies to the following embodiments.

  In FIG. 2, 2 is a semiconductor inspection system, 31 is a semiconductor inspection apparatus, 34 is a voltmeter that outputs a control signal, 35 is a first voltage supply unit, 36 is a second voltage supply unit, and 37 is a voltage control unit. is there.

  Vdp2 is a potential applied to the first substrate potential supply terminal 18, Vdn2 is a potential applied to the second substrate potential supply terminal 19, Vin is a potential applied from the third voltage supply unit 113, and Vm is a potential applied to the power supply terminal 102. Potential.

  The operation of the semiconductor inspection system 2 shown in FIG. 2 will be described below. First, the potential Vdp2 is applied from the first voltage supply unit 35 to the first substrate potential supply terminal 18, while the potential Vdn2 is applied from the second voltage supply unit 36 to the second substrate potential supply terminal 19.

  Further, the potential Vin is given from the third voltage supply unit 113 to the load resistor 112 with respect to the ground reference. Here, Vin = −1.5V.

  The potential Vdp2 is given so as to satisfy the relationship Vin <Vdp2 so that the PMOS transistor substrate is reverse-biased. For example, Vdp2 = −1.0V.

  The potential Vdn2 is applied so that the NMOS transistor substrate is reverse-biased with respect to the ground potential. For example, Vdn2 = −0.5V.

  Further, a desired voltage value Vmi to be measured as the potential Vm of the power supply terminal 102 is set in the voltmeter 34 in advance. For example, Vmi = −0.8V is set.

In this state, the transistor substrate of the internal circuit 15 has been reverse biased, to reduce the off-leakage current I ₂ by variation or the like of the device it may not be sufficient. For example, if R = 1 kΩ, I ₁ = 0.8 mA, and I ₂ = 0.6 mA, Vm measured by the voltmeter 34 is −0.1 V, which is lower than the built-in voltage of the surge protection diode 104. Become.

  The voltmeter 34 generates a control signal for the voltage control unit 37 when there is a difference between Vm and Vmi. For example, when Vm> Vmi, −1.0 V is set, and when Vm <Vmi, 1.0 V is set.

  The voltage control unit 37 generates and outputs a signal for adjusting the voltage value to the first voltage supply unit 35 and the second voltage supply unit 36 based on the control signal output from the voltmeter 34. To do.

For example, when the output signal from the voltmeter 44 is −1.0 V, since the relationship of Vm> Vmi is established, the voltage value is adjusted in the direction of decreasing the off-leakage current I ₂ in the above example. Vdp2 is changed from -1.0V to 0V, and Vdn2 is changed from -0.5V to -1.5V.

By performing such control, the off-leakage current I ₂ becomes sufficiently smaller than the forward current I ₁ and is stabilized at Vm = −0.8V.

As described above, according to the semiconductor inspection system according to the second reference example , the substrate potential can be automatically adjusted so that the measured voltage value becomes a desired value, without depending on the variation of the device, The power supply terminal connectivity inspection and the determination of a short circuit failure between the power supply and the ground can be performed stably.

In Reference Example 2, the initial values of the potential Vdp2 and the potential Vdn2 are set to Vdp2 = −1.0 V and Vdn2 = −0.5 V, respectively. However, the present invention is not limited to this mode. Some Vdp2 = −1.5V and Vdn2 = 0V may be applied.

< Reference Example 3>
FIG. 3 is a diagram showing a configuration of a semiconductor inspection system according to Reference Example 3 of the present invention. In FIG. 3, 3 is a semiconductor inspection system, 41 is a semiconductor integrated circuit, 48 is a first substrate potential supply unit for supplying a PMOS substrate potential, and 49 is a second substrate potential supply for supplying an NMOS substrate potential. Part.

  Vdp4 is a potential output from the first substrate potential supply unit 48, and Vdn4 is a potential output from the second substrate potential supply unit 49.

  The operation of the semiconductor inspection system 3 shown in FIG. 3 will be described below. First, the potential Vin is given from the third voltage supply unit 113 to the load resistor 112 with respect to the ground reference. At this time, the potential Vin is applied so that the surge protection diode 104 is forward biased. For example, when the ground reference is 0V, Vin = −1.5V.

  The potential Vdp4 is applied by the first substrate potential supply unit 48 so that the PMOS transistor substrate is reverse-biased, while the potential Vdn4 is the second substrate so that the NMOS transistor substrate is reverse-biased with respect to the ground potential. It is given by the potential supply unit 49.

  FIG. 4 is a diagram showing an internal configuration of the first substrate potential supply unit. In FIG. 4, 48a, 48b, and 48c are external terminals, p1 is a first transistor formed of PMOS, and p2 is a second transistor formed of PMOS.

  As shown in FIG. 4, the drain of the first transistor p1 and the drain of the second transistor p2 are connected to the external terminal 48a.

  The external terminal 48b is connected to the source of the first transistor p1, the substrate of the first transistor p1 and the second transistor p2, and the gate of the second transistor p2.

  The external terminal 48c is connected to the source of the second transistor p2 and the gate of the first transistor p1.

  In the semiconductor integrated circuit 41, the external terminal 48a is connected to the PMOS substrate of the internal circuit 15, the external terminal 48b is connected to the internal power line 106, and the external terminal 48c is connected to the internal ground line 107.

  Here, when the semiconductor integrated circuit 41 is normally operated, a potential is applied to the power supply terminal 102 and the ground terminal 103 is grounded. Here, it is assumed that the potential of the power supply terminal 102 is 1.2V and the ground potential is 0V. At this time, since the source potential of the first transistor p1 is 1.2V and the gate potential is 0V, the first transistor p1 is in the ON state, the source potential of the second transistor p2 is 0V, and the gate potential is 1.2V. Therefore, the second transistor p2 is turned off. As a result, 1.2V is supplied to the external terminal 48a.

  Therefore, the PMOS substrate potential of the semiconductor integrated circuit 41 is 1.2 V, and an operation equivalent to the conventional example is possible.

  Next, consider the power connection inspection of the semiconductor integrated circuit 41. If a potential is applied from the outside by an inspection method equivalent to that of the conventional example, the potential of the power supply terminal 102 is -0.8V and the ground terminal potential is 0V. At this time, since the source potential of the first transistor p1 is −0.8V and the gate potential is 0V, the first transistor p1 is in the OFF state, the source potential of the second transistor p2 is 0V, and the gate potential is −0. Therefore, the second transistor p2 is turned on. As a result, 0V is supplied to the external terminal 48a.

  Accordingly, the PMOS substrate potential of the semiconductor integrated circuit 41 is 0V, and the PMOS substrate potential is in the reverse bias direction during the power connection inspection.

  FIG. 5 is a diagram illustrating an internal configuration of the second substrate potential supply unit. In FIG. 5, 49d, 49e, and 49f are external terminals, n3 is a third transistor formed of NMOS, and n4 is a fourth transistor formed of NMOS.

  As shown in FIG. 5, the drain of the third transistor n3 and the drain of the fourth transistor n4 are connected to the external terminal 49d.

  The external terminal 49e is connected to the source of the third transistor n3 and the gate of the fourth transistor n4.

  The external terminal 49f is connected to the source of the fourth transistor n4, the gate of the third transistor n3, and the substrate of the third transistor n3 and the fourth transistor n4.

  In the semiconductor integrated circuit 41, 49 d is connected to the NMOS substrate of the internal circuit 15, 49 e is connected to the internal power supply line 106, and 49 f is connected to the internal ground line 107.

  Here, consider the case where the semiconductor integrated circuit 41 is normally operated. Here, the potential of the power supply terminal 102 is 1.2V, and the ground potential is 0V. At this time, since the source potential of the third transistor n3 is 1.2V and the gate potential is 0V, the third transistor n3 is in the OFF state, the source potential of the fourth transistor n4 is 0V, and the gate potential is 1.2V. Therefore, the fourth transistor n4 is turned on. As a result, 0V is supplied to the external terminal 49d.

  Therefore, the NMOS substrate potential of the semiconductor integrated circuit 41 is 0 V, and the same operation as in the conventional example is possible.

  Next, consider the power connection inspection of the semiconductor integrated circuit 41. If a potential is applied from the outside by an inspection method equivalent to that of the conventional example, the potential of the power supply terminal 102 is -0.8V and the ground terminal potential is 0V. At this time, since the source potential of the third transistor n3 is −0.8 V and the gate potential is 0 V, the third transistor n3 is in the ON state, the source potential of the fourth transistor n4 is 0 V, and the gate potential is −0. Since the voltage is .8V, the fourth transistor n4 is turned off. As a result, -0.8V is supplied to the external terminal 49d.

  Therefore, the NMOS substrate potential of the semiconductor integrated circuit 41 is −0.8 V, and the NMOS substrate potential is in the reverse bias direction at the time of power connection inspection.

In such a state, the transistor substrate of the internal circuit 15 is reverse-biased, and the off-leakage current I ₂ is smaller than the forward current I ₁ of the surge protection diode 104.

Therefore, the forward current I ₁ is dominant in the current flowing into the power supply terminal 102, and the potential Vm of the power supply terminal 102 is stabilized near the built-in voltage of the surge protection diode 104.

As described above, according to the semiconductor inspection system according to the third reference example , an operation equivalent to the conventional operation is possible during normal operation without increasing the number of external terminals, and the connectivity of the power supply terminal 102 during power connection inspection. In this way, it is possible to avoid the problem that the Vm decreases due to the influence of the off-leakage current I ₂ from the internal circuit 15 as in the prior art, and to perform a stable determination of a short circuit failure between the power source and the ground. It becomes possible.

< Reference Example 4>
FIG. 6 is a diagram showing a configuration of a semiconductor inspection system according to Reference Example 4 of the present invention. In FIG. 6, 4 is a semiconductor inspection system, 51 is a semiconductor integrated circuit, 56 is an internal power supply line, 58 is a switch circuit, 59 is a control terminal, and 21 is a semiconductor inspection apparatus.

The operation of the semiconductor inspection apparatus 21 is basically the same as the operation of the semiconductor inspection apparatus 11 in Reference Example 1, but a potential is applied to the control terminal 59 of the switch circuit 58 by the first voltage supply unit 25. The point which was made is different. Here, the potential applied to the control terminal 59 is 0V. At this time, the switch circuit 58 formed of PMOS has a source-gate voltage of 0.8 V and is turned off.

Therefore, when connecting check of the power supply terminal 102, since the off-leakage current I ₂ from the internal circuit 105 does not flow to the power supply terminal 102, the potential Vm of the power supply terminal 102 to stabilize around a built-in voltage of the surge protection diode 104 become.

As described above, according to the semiconductor inspection system according to the fourth reference example , the connectivity of the power supply terminal 102 can be stably inspected with a small number of external terminal controls.

In the fourth reference example , the switch circuit is provided in the internal power supply line. However, the same effect can be obtained by providing the switch circuit in both the internal power supply line and the internal ground line.

< Reference Example 5>
FIG. 7 is a diagram showing a configuration of a semiconductor inspection system according to Reference Example 5 of the present invention. In FIG. 7, 5 is a semiconductor inspection system, 61 is a semiconductor integrated circuit, 67 is an internal ground line, 68 is a switch circuit, 69 is a control terminal, and 21 is a semiconductor inspection device.

The operation of the semiconductor inspection apparatus 21 is basically the same as the operation of the semiconductor inspection apparatus 11 in Reference Example 1, but a potential is applied to the control terminal 69 of the switch circuit 68 by the first voltage supply unit 25. The point which was made is different. Here, the potential applied to the control terminal 69 is −0.8V. At this time, the switch circuit 68 formed of NMOS has a source-gate voltage of −0.8 V and is turned off.

Therefore, since the internal off-leakage current I ₂ does not flow into the power supply terminal 102 during the connectivity test of the power supply terminal 102, the potential Vm of the power supply terminal 102 is stabilized near the built-in voltage of the surge protection diode 104.

As described above, according to the semiconductor inspection system of Reference Example 5, the connectivity of the power supply terminal 102 can be stably inspected with a small number of external terminal controls.

In the reference example 5, the switch circuit is provided on the internal ground line. However, the same effect can be obtained by providing the switch circuit on both the internal power supply line and the internal ground line.

<Embodiment 1 >
FIG. 8 is a diagram showing a configuration of the semiconductor inspection system according to Embodiment 1 of the present invention. In FIG. 8, 6 is a semiconductor inspection system, 71 is a semiconductor integrated circuit, 76 is an internal power supply line, 107 is an internal ground line, 78 is a switch circuit, and 111 is a semiconductor inspection apparatus.

The operation of the semiconductor inspection apparatus 111 is the same as that described in Reference Example 3. At this time, since the gate of the switch circuit 78 composed of PMOS is connected to the internal ground line 107, the potential becomes 0V, and the switch circuit 78 is turned off.

Therefore, since the internal off-leakage current I ₂ does not flow into the power supply terminal 102 during the connectivity test of the power supply terminal 102, the potential Vm of the power supply terminal 102 is stabilized near the built-in voltage of the surge protection diode 104. Further, during normal operation, the switch circuit 78 is in an ON state and does not affect the operation.

As described above, according to the semiconductor inspection system according to the first embodiment, the connectivity of the power supply terminal 102 can be stably inspected without increasing the number of external terminals.

In the first embodiment, the switch circuit is provided in the internal power supply line. However, the same effect can be obtained by providing the switch circuit in both the internal power supply line and the internal ground line.

<Embodiment 2 >
FIG. 9 is a diagram showing a configuration of a semiconductor inspection system according to Embodiment 2 of the present invention. In FIG. 9, 7 is a semiconductor inspection system, 81 is a semiconductor integrated circuit, 87 is an internal ground line, 88 is a switch circuit, and 111 is a semiconductor inspection device.

The operation of the semiconductor inspection apparatus 111 is the same as that described in Reference Example 3. At this time, since the gate of the switch circuit 88 composed of NMOS is connected to the internal power supply line 106, the potential becomes −0.8 V, and the switch circuit 88 is turned off.

Therefore, when connecting check of the power supply terminal 102, since the off-leakage current I ₂ from the internal circuit 105 does not flow to the power supply terminal 102, the potential Vm of the power supply terminal 102 to stabilize around a built-in voltage of the surge protection diode 104 become. Further, during normal operation, the switch circuit 88 is turned on and does not affect the operation.

As described above, according to the semiconductor inspection system according to the second embodiment, the connectivity of the power supply terminal 102 can be stably inspected without increasing the number of external terminals.

In the second embodiment, the switch circuit is provided in the internal ground line. However, the same effect can be obtained by providing the switch circuit in both the internal power supply line and the internal ground line.

  As described above, the present invention can reduce the influence of the off-leakage current of the internal circuit and perform stable inspection when inspecting the connectivity of the power supply terminal of the semiconductor integrated circuit by the voltage application voltage measurement method. Therefore, it is extremely useful and has high industrial applicability.

It is a figure which shows the structure of the semiconductor inspection system which concerns on the reference example 1 of this invention. It is a figure which shows the structure of the semiconductor inspection system which concerns on this reference example 2. It is a figure which shows the structure of the semiconductor inspection system which concerns on this reference example 3. It is a figure which shows the internal structure of the 1st board | substrate electric potential supply part in this reference example 3. FIG. It is a figure which shows the internal structure of the 2nd board | substrate potential supply part in this reference example 3. FIG. It is a figure which shows the structure of the semiconductor inspection system which concerns on this reference example 4. It is a figure which shows the structure of the semiconductor inspection system which concerns on this reference example 5. FIG. 1 is a diagram illustrating a configuration of a semiconductor inspection system according to a first embodiment. It is a figure which shows the structure of the semiconductor inspection system which concerns on this Embodiment 2. FIG. It is a figure which shows the structure of the conventional semiconductor inspection system.

DESCRIPTION OF SYMBOLS 3 Semiconductor test | inspection system 15 Internal circuit 41 Semiconductor integrated circuit 48 1st board | substrate potential supply part 49 2nd board | substrate potential supply part 102 Power supply terminal 103 Ground terminal 104 Surge protection diode 111 Semiconductor test | inspection apparatus 112 Load resistance 113 Voltage supply part 114 voltmeter

Claims (4)

A power supply terminal for supplying power;
A ground terminal for supplying a ground potential;
An internal power line connected to the power terminal;
An internal ground wire connected to the ground terminal;
A surge protection circuit connected between the internal power line and the internal ground line;
An internal circuit composed of a group of CMOS transistors and connected between the internal power supply line and the internal ground line;
A semiconductor integrated circuit comprising: a switch circuit connected between the surge protection circuit and the internal circuit in the internal power supply line and having a control terminal connected to the internal ground line. A power supply terminal for supplying power;
A ground terminal for supplying a ground potential;
An internal power line connected to the power terminal;
An internal ground wire connected to the ground terminal;
A surge protection circuit connected between the internal power line and the internal ground line;
An internal circuit composed of a group of CMOS transistors and connected between the internal power supply line and the internal ground line;
A semiconductor integrated circuit comprising: a switch circuit connected between the surge protection circuit and the internal circuit in the internal ground line and having a control terminal connected to the internal power supply line. A method for inspecting a semiconductor integrated circuit using a semiconductor inspection apparatus for inspecting connectivity of a power supply terminal of the semiconductor integrated circuit according to claim 1 or 2 in a voltage application voltage measurement method ,
The semiconductor inspection apparatus includes a load resistor connected to the power supply terminal of the semiconductor integrated circuit, a voltmeter for measuring the potential of the power supply terminal, and a voltage supply means connected to the load resistor. ,
A test method for a semiconductor integrated circuit, comprising: a step of measuring a potential of the power supply terminal by supplying a voltage to the power supply terminal of the semiconductor integrated circuit through the load resistor by the voltage supply means. The semiconductor integrated circuit according to claim 1 or 2,
A load resistance connected to the power supply terminal of the semiconductor integrated circuit; a voltmeter for measuring the potential of the power supply terminal; and a voltage supply means connected to the load resistance. A semiconductor inspection system comprising: a semiconductor inspection apparatus for inspecting connectivity of power supply terminals of an integrated circuit .

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