JP2022067364A - Manufacturing method of semiconductor integrated circuit, semiconductor integrated circuit - Google Patents

Abstract

To provide a semiconductor integrated circuit which does not need a regulator and an external terminal, and can apply a stress voltage to a drain of a transistor constituting an output circuit without connecting a load circuit to the outside, even if the output circuit has an open drain configuration.SOLUTION: A semiconductor integrated circuit according to the present invention includes a transistor connected to a signal output terminal and a load circuit connected to the signal output terminal, and the load circuit is configured so that it can switch whether or not to supply a load current to the transistor.SELECTED DRAWING: Figure 1

Description

The present invention relates to semiconductor integrated circuits.

In the process of manufacturing a semiconductor integrated circuit, an inspection process such as a burn-in test may be performed. The burn-in test is for detecting an initial defect by, for example, applying an overvoltage from a terminal of a semiconductor integrated circuit under a temperature load environment. In addition to the burn-in test, there are various tests in which a device is connected to a terminal of a semiconductor integrated circuit to carry out an inspection process.

Patent Document 1 describes a technique related to a gate screening test function such as a drive circuit of an insulated gate type device. The document provides a semiconductor integrated device capable of performing a gate screening test without the need to provide an additional circuit and without separately providing a gate screening terminal. A gate drive unit 12 for driving the gate of the voltage-controlled semiconductor element Q2 and a regulator 13 for supplying the gate drive voltage to the gate drive unit are provided, and the voltage control type is provided at the time of the gate screening test. It is provided with an external connection terminal tc capable of applying a gate screening voltage to the semiconductor element. 』(See summary).

Japanese Unexamined Patent Publication No. 2019-007823

In order to carry out the technique described in Patent Document 1, a regulator having an external terminal to which a stabilizing capacitance is added is required. Therefore, it cannot be applied to a semiconductor integrated circuit having no regulator. Further, since the technique described in Patent Document 1 controls the gate voltage of the drive circuit from an external terminal, simultaneous measurement is performed when there are restrictions on the power supply and signal generator provided in the device for performing burn-in such as wafer level burn-in. It is difficult to increase the number.

By the way, some semiconductor integrated circuits include an output circuit having an open drain configuration. An output circuit having an open drain configuration requires a load circuit such as a resistance element (for example, a pull-up resistor) outside the semiconductor integrated circuit. When a wafer level burn-in test is performed on such a semiconductor integrated circuit, it is necessary to supply a signal to the terminal to which the output circuit is connected, so that the test efficiency is lowered. On the other hand, when the terminal to which this output circuit is connected is tested in the open state, the stress voltage is not applied to the drain of the MOS transistor constituting the output circuit, so that the detection accuracy of the initial defect may be lowered. ..

The present invention has been made in view of the above problems, and even if a regulator and an external terminal are not required and the output circuit has an open drain configuration, the output circuit is configured without connecting a load circuit to the outside. It is an object of the present invention to provide a semiconductor integrated circuit capable of applying a stress voltage to the drain of a transistor.

The semiconductor integrated circuit according to the present invention includes a transistor connected to a signal output terminal and a load circuit connected to the signal output terminal, and whether or not the load circuit supplies a load current to the transistor. It is configured so that it can be switched.

According to the semiconductor integrated circuit according to the present invention, even if the output circuit has an open drain configuration, a stress voltage can be applied to the drain of the transistor constituting the output circuit without connecting a load circuit to the outside. Further problems, configurations, advantages, etc. of the present invention will be clarified by the following description of the embodiments.

It is a circuit block diagram of the semiconductor integrated circuit 1 which concerns on Embodiment 1. FIG. It is an output waveform of the semiconductor integrated circuit 1 in the case where the load circuit 102a is absent and the case where the load circuit 102a is present. It is a figure which shows the structural example of the load circuit 102a in Embodiment 2. It is a figure which shows the structural example of the load circuit 102a in Embodiment 3. FIG. It is a circuit block diagram of the semiconductor integrated circuit 1 which concerns on Embodiment 4. FIG. It is a figure which shows the structural example of the load circuit 102a in Embodiment 5. It is a figure which shows the structural example of the load circuit 102a in Embodiment 6.

<Embodiment 1>
FIG. 1 is a circuit configuration diagram of a semiconductor integrated circuit 1 according to the first embodiment of the present invention. The semiconductor integrated circuit 1 includes a power supply terminal VCS, a ground power supply terminal GND, a signal output terminal OUT, an output control circuit 101, an output circuit 102, and a voltage detection circuit 103. For example, 5V is supplied to the power supply terminal VCS during normal operation and 7V is supplied during burn-in.

The output control circuit 101 is a circuit that controls the signal line OUTB according to the data output to the signal output terminal OUT.

The output circuit 102 includes a load circuit 102a and an µtransistor 102b. In this embodiment, the load circuit 102a is composed of a polyclonal transistor. The drain of the polyclonal transistor is connected to the signal output terminal OUT, the source is connected to the power supply terminal VCS, and the gate is connected to the signal line BIB. The signal line BIB is controlled by the voltage detection circuit 103. The drain of the IGMP transistor 102b is connected to the signal output terminal OUT, the source is connected to the ground power supply terminal GND, and the gate is connected to the signal line OUTB. The signal line OUTB is controlled by the output control circuit 101.

The voltage detection circuit 103 is a circuit that drives the signal line BIB so that the load circuit 102a is turned off during normal operation and turned on during burn-in. In the present embodiment, since the load circuit 102a is a polyclonal transistor, the signal line BIB is driven to the same voltage as the power supply terminal VCS during normal operation, and is driven to the voltage Vb through which the load current flows during burn-in. It is desirable to do. As a result, the output circuit 102 operates in an open drain configuration during normal operation. Since the load circuit 102a is turned off during normal operation, it does not affect the load circuit connected to the outside.

The voltage detection circuit 103 can adjust the current value of the load current flowing through the Now's transistor 102b by adjusting the level of the voltage Vb. In other words, the voltage Vb can be adjusted according to the desired load current level.

FIG. 2 is an output waveform of the semiconductor integrated circuit 1 in the case where the load circuit 102a is not provided and in the case where the load circuit 102a is present. FIG. 2 shows a signal waveform when the load circuit 102a (PM Volume transistor) is turned on (that is, during a burn-in test). During the burn-in test, the power supply terminal VCS is connected to the power supply voltage, and the ground power supply terminal GND is connected to the ground potential.

When there is no load circuit 102a, the signal output from the signal output terminal OUT does not change even if the signal line OUTB is controlled, unless the load circuit is externally connected to the signal output terminal OUT. When the load circuit 102a is present, the potential of the signal output terminal OUT can be changed by controlling the signal line OUTB by the output control circuit 101 without connecting an external load circuit to the signal output terminal OUT. can. That is, a stress voltage can be applied to the drain of the NaOH transistor 102b.

<Embodiment 1: Summary>
The semiconductor integrated circuit 1 according to the first embodiment includes a load circuit 102a (SiO transistor) and an µtransistor 102b, and the drain of each transistor is connected to the signal output terminal OUT. As a result, the load circuit 102a can be turned off during normal operation so as not to affect the outside, and the load circuit 102a can be turned on during the burn-in test to apply a stress voltage to the nanotube transistor 102b. Since this stress voltage is supplied by the semiconductor integrated circuit 1 itself, it is not necessary to connect an external element to the signal output terminal OUT in order to apply the stress voltage.

<Embodiment 2>
FIG. 3 is a diagram showing a configuration example of the load circuit 102a according to the second embodiment of the present invention. The configuration other than the load circuit 102a is the same as that of the first embodiment. In the second embodiment, the load circuit 102a is composed of the resistance element R1 and the polyclonal transistor M1. The resistance element R1 is arranged between the drain of the epitaxial transistor M1 and the signal output terminal OUT.

In the second embodiment, since the current flowing through the load circuit 102a can be limited by the resistance element R1, it is not necessary to limit the current by the polyclonal transistor M1. Therefore, at the time of the burn-in test, the gate voltage (signal line BIB) of the polyclonal transistor M1 can be set to 0V, so that the voltage detection circuit 103 can be simplified as compared with the case where the signal line BIB is driven by the voltage Vb. In other words, the voltage detection circuit 103 does not need to generate a desired gate voltage level by voltage conversion or the like, and may output the ground potential as it is, so that the circuit configuration can be simplified.

<Embodiment 3>
FIG. 4 is a diagram showing a configuration example of the load circuit 102a according to the third embodiment of the present invention. The configuration other than the load circuit 102a is the same as that of the first embodiment. In the third embodiment, the load circuit 102a is composed of the polyclonal transistors M2 and M3. The drains of the polyclonal transistors M2 and M3 are connected to the signal output terminal OUT. The gate and source of the polyclonal transistor M3 are connected to the power supply terminal VCC. The gate of the polyclonal transistor M2 is driven by the signal line BIB.

The polyclonal transistor constituting the load circuit 102a acts as a protection circuit for protecting the nanotube transistor 102b. As a result, the mounting area of the output circuit 102 can be reduced.

Since the photography transistor for protection is generally designed to have a large channel width, the current may be large to be used as a load of the IGMP transistor 102b. In such a case, as shown in FIG. 4, two polyclonal transistors M2 and M3 may be used in combination, and M2 may be used as a substantial load circuit 102a.

<Embodiment 4>
FIG. 5 is a circuit configuration diagram of the semiconductor integrated circuit 1 according to the fourth embodiment of the present invention. In the first embodiment, the µtransistor 102b is used as an element for driving the signal output terminal OUT of the output circuit 102, but a polyclonal transistor may be used instead of the NaCl transistor 102b. FIG. 5 shows the circuit configuration. In this case, the load circuit 102a is composed of an msgid transistor. The voltage level of the signal line OUTB and the voltage level of the signal line BIB are each inverted of each voltage level in the first embodiment.

<Embodiment 5>
FIG. 6 is a diagram showing a configuration example of the load circuit 102a according to the fifth embodiment of the present invention. The configuration other than the load circuit 102a is the same as that of the fourth embodiment. The transistor M1 is an IGMP transistor. Therefore, the source of M1 is connected to the ground power supply terminal GND. Others are the same as in the second embodiment.

In the second embodiment, since the voltage detection circuit 103 outputs 0V as the gate voltage when M1 is turned on, voltage conversion or the like is not necessary. In the fifth embodiment, the voltage detection circuit 103 outputs the power supply potential as the gate voltage when M1 is turned on, so that voltage conversion or the like is not necessary in the same manner. Therefore, the circuit configuration can be simplified as in the second embodiment.

<Embodiment 6>
FIG. 7 is a diagram showing a configuration example of the load circuit 102a according to the sixth embodiment of the present invention. The configuration other than the load circuit 102a is the same as that of the fourth embodiment. In the sixth embodiment, the load circuit 102a is composed of the nanotube transistors M2 and M3. Therefore, the source of M2, the source of M3, and the gate of M3 are connected to the ground power supply terminal GND. Others are the same as in the third embodiment. Also in the sixth embodiment, the same effect as that of the third embodiment can be exhibited.

<About a modification of the present invention>
The present invention is not limited to the above embodiment, and includes various modifications. For example, the above-described embodiment has been described in detail in order to explain the present invention in an easy-to-understand manner, and is not necessarily limited to the one including all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

In the above embodiments, the MOS transistor is used as the transistor, but other transistors (switches) such as bipolar transistors may be used.

In the above embodiment, the output control circuit 101 and the voltage detection circuit 103 can be configured by hardware such as a circuit device that implements these functions, and software that implements these functions is provided as a CPU (Central Processing Unit). It can also be configured by executing an arithmetic unit such as).

1: Semiconductor integrated circuit 101: Output control circuit 102: Output circuit 102a: Load circuit 102b: MOSFET transistor 103: Voltage detection circuit R1: Resistance elements M1, M2, M3: MOS transistor

Claims (10)

It is a method of manufacturing semiconductor integrated circuits.
The semiconductor integrated circuit is
Power terminal,
Signal output terminal,
A voltage detection circuit that generates a control signal according to the voltage of the power supply terminal,
An output circuit that outputs the output signal of the semiconductor integrated circuit to the signal output terminal,
Equipped with
The output circuit is
A load circuit connected between the power supply terminal and the signal output terminal,
The first transistor connected to the signal output terminal,
Equipped with
The load circuit is controlled by the control signal and is controlled by the control signal.
The method comprises a step of performing a burn-in test on the semiconductor integrated circuit.
In the step of performing the burn-in test, the voltage detection circuit is characterized in that the voltage level at which the load current flows from the load circuit to the first transistor is set as the voltage level of the control signal. How to make an integrated circuit. The semiconductor integrated circuit is further provided with a ground terminal.
The semiconductor integrated circuit further includes an output control circuit for controlling the first transistor.
The load circuit has a second transistor and
The method further
Steps to connect the power supply terminal to the power supply voltage,
Step of connecting the ground terminal to the ground potential,
Have,
In the step of carrying out the burn-in test, the voltage detection circuit causes the load current to flow from the load circuit to the first transistor by turning on the second transistor by the control signal.
In the step of carrying out the burn-in test, the output control circuit carries out the load test of the first transistor while passing the load current through the first transistor by turning on / off the first transistor. The method for manufacturing a semiconductor integrated circuit according to claim 1. The load circuit is
Load circuit transistor,
A resistance element arranged between the drain terminal of the load circuit transistor and the signal output terminal,
Consists of
In the step of carrying out the burn-in test, the voltage detection circuit sets the ON potential for turning on the load circuit transistor as the voltage level of the control signal.
The semiconductor integrated circuit according to claim 1, wherein the ON potential is a ground potential when the load circuit transistor is a polyclonal transistor, and is a power supply potential when the load circuit transistor is an IGMP transistor. Production method. The load circuit is
1st load circuit transistor,
2nd load circuit transistor,
Consists of
The gate terminal of the first load circuit transistor is arranged so as to receive the control signal from the voltage detection circuit.
The drain terminal of the first load circuit transistor and the drain terminal of the second load circuit transistor are connected to the signal output terminal.
The source terminal of the first load circuit transistor, the gate terminal of the second load circuit transistor, and the source terminal of the second load circuit transistor may be such that the first load circuit transistor and the second load circuit transistor are polyclonal transistors. For example, it is connected to the power supply terminal, and if the first load circuit transistor and the second load circuit transistor are IGMP transistors, it is connected to the ground potential.
In the step of carrying out the burn-in test, the voltage detection circuit sets a potential for turning on the first load circuit transistor as the voltage level of the control signal, so that the voltage detection circuit does not pass through the second load circuit transistor. The method for manufacturing a semiconductor integrated circuit according to claim 1, wherein a current is supplied to the first transistor via the first load circuit transistor. The output circuit is
The first transistor is composed of an NaCl transistor and is arranged between the signal output terminal and the ground terminal.
Whether the second transistor is configured by being composed of a polyclonal transistor and being arranged between the power supply terminal and the signal output terminal.
or,
The output circuit is
The second transistor is composed of an µtransistor and is arranged between the signal output terminal and the ground terminal.
The manufacture of the semiconductor integrated circuit according to claim 2, wherein the first transistor is composed of a polyclonal transistor and is arranged between the power supply terminal and the signal output terminal. Method. It is a semiconductor integrated circuit
The semiconductor integrated circuit is
Power terminal,
Signal output terminal,
A voltage detection circuit that generates a control signal according to the voltage of the power supply terminal,
An output circuit that outputs the output signal of the semiconductor integrated circuit to the signal output terminal,
Equipped with
The output circuit is
A load circuit connected between the power supply terminal and the signal output terminal,
The first transistor connected to the signal output terminal,
Equipped with
The voltage detection circuit is a semiconductor integrated circuit characterized by outputting the control signal whose voltage level is set so that a current does not flow to the first transistor via the load circuit. The semiconductor integrated circuit is further provided with a ground terminal.
The load circuit is composed of a second transistor connected to the power supply terminal.
The power supply terminal is connected to the power supply voltage and
The ground terminal is connected to the ground potential and is connected to the ground potential.
The semiconductor integrated circuit according to claim 6, wherein the voltage detection circuit outputs the control signal for turning off the second transistor. The load circuit is
Load circuit transistor,
A resistance element arranged between the drain terminal of the load circuit transistor and the signal output terminal,
Consists of
The voltage detection circuit sets an OFF potential for turning off the load circuit transistor as the voltage level of the control signal.
The semiconductor integrated circuit according to claim 6, wherein the OFF potential is a power supply potential when the load circuit transistor is a polyclonal transistor, and is a ground potential when the load circuit transistor is an IGMP transistor. The load circuit is
1st load circuit transistor,
2nd load circuit transistor,
Consists of
The gate terminal of the first load circuit transistor is arranged so as to receive the control signal from the voltage detection circuit.
The drain terminal of the first load circuit transistor and the drain terminal of the second load circuit transistor are connected to the signal output terminal.
The source terminal of the first load circuit transistor, the gate terminal of the second load circuit transistor, and the source terminal of the second load circuit transistor may be such that the first load circuit transistor and the second load circuit transistor are polyclonal transistors. For example, it is connected to the power supply terminal, and if the first load circuit transistor and the second load circuit transistor are IGMP transistors, it is connected to the ground potential.
The semiconductor integrated circuit according to claim 6, wherein the voltage detection circuit sets a potential for turning off the first load circuit transistor as a voltage level of the control signal. The output circuit is
The first transistor is composed of an NaCl transistor and is arranged between the signal output terminal and the ground terminal.
Whether the second transistor is configured by being composed of a polyclonal transistor and being arranged between the power supply terminal and the signal output terminal.
or,
The output circuit is
The second transistor is composed of an µtransistor and is arranged between the signal output terminal and the ground terminal.
The semiconductor integrated circuit according to claim 7, wherein the first transistor is composed of a polyclonal transistor and is arranged between the power supply terminal and the signal output terminal.

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