JP2000055978A - Power source current measuring device of complementary metal oxide semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power source current measuring device of CMOS (complementary metal oxide semiconductor) integrated circuit capable of speedily and accurately IDDq testing without increasing much the terminal number of chip. SOLUTION: A chip 1 is provided with a power source terminal TDD used for both power supply in normal use and power supply in IDDq testing. Between the power source terminal TDD and a CMOS integrated circuit 2, a current- voltage converter 11 is provided to convert a power source current IDD into a voltage VCUTs. Here the equivalent resistance value of current-voltage converter 11 is set so small a value so that the voltage drop in the case of flowing a maximum stationary power source current IDDq does not exceed an allowable voltage lowering width of the CMOS integrated circuit 2 and the power source current IDD converges sufficiently quicker than normal operation period. Furthermore after the voltage VCUTs is amplified to VCUTs in an amplifier 12, it is compared with a predetermined reference voltage VREF in a measured value comparison judgment part 14 and judged good or bad.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CMOS (Compl.
The present invention relates to a power supply current measuring device suitable for an _IDDq test for judging _{pass / fail} of a CMOS integrated circuit based on a static leakage current flowing through a power supply terminal of an integrated circuit, and in particular, despite a small number of pins. More specifically, the present invention relates to a power supply current measuring device for a CMOS integrated circuit capable of measuring with high accuracy and high speed.

[0002]

_{2. Description of the Related} Art At present, in the semiconductor industry, an _IDDq test is widely used as a method of judging the quality of a CMOS integrated circuit (hereinafter abbreviated as CUT). In the I _DDq test, a large current flows only when the state of the internal circuit (internal node) of the CUT _changes ,
This is a test using the property that almost no current flows, and a pass / fail judgment is made based on a minute fluctuation of the static leakage current flowing to the power supply voltage terminal of the CUT.

For example, when a defect occurs in a certain portion of an internal node of a CUT and a resistive short exists between the power supply or ground (GND) level and the portion, the resistance value of the short is relatively small. In this case, the node
Normal operation cannot be performed, and the defect can be detected by input / output determination. On the other hand, if the resistance value of the short circuit is extremely large, the node logically becomes “0” or “0”.
The level determined to be 1 "can be output, and the defect cannot be detected from the input / output determination.
Even in this case, the resistance short circuit causes
A current that causes a slight voltage level fluctuation flows. I
_{The DDq} test detects this current to detect whether or not an abnormality has occurred in each internal node.

[0004] Specifically, a power supply current measuring device is arranged between the CUT and the power supply, and after keeping the state of each internal node in a stationary state, the power supply current (I _DDq ) in the stationary state is measured. . The measured value is compared with a reference value, and a pass / fail judgment is made. In this I _DDq test, the quiescent power supply current I _{DDq needs} to be measured both when the state of each internal node is “0” and when it is “1”. Using a function test pattern or the like for testing the logical function of the CUT for the purpose of detection,
The quiescent power supply current I _DDq is measured while keeping the state of each internal node of the UT different from time to time.

Here, the normal level of the quiescent power supply current I _{DDq depends on} the state of the internal node of the CUT and is approximately 0 μm.
A] to several hundred [μA] in some cases. Therefore, in order to improve the determination accuracy, the power supply current measuring device _often determines _{pass / fail} by comparing the stationary power supply current I _DDq with a reference value specified for each measurement.

For example, Japanese Patent Application Laid-Open No. 6-58981 discloses a configuration in which a power supply current measuring circuit 103 is built in a chip 101 having a CUT 102 as shown in FIG. In this configuration, a power supply terminal T _TEST for testing is added separately from the power supply terminal T _{DD in} normal use, and a branch point provided between the CUT 102 and the power supply terminal T _DD is connected to a power supply terminal for testing. A current detection resistor 111 is provided between T _TEST .

In the I _DDq test, the normal power supply voltage V
_A voltage V _TEST higher than _DD is _supplied to a test power supply terminal T _TEST
Is applied to When the state of the internal node of the CUT 102 is stationary, the CUT 102 and the current detecting resistor 111
The voltage V _{CUT at} the connection point with the power supply decreases in proportion to the quiescent power supply current I _DDq . In this state, the comparator 112
Compares the reference voltage V _REF supplied from the outside and the voltage V _CUT, the voltage V _CUT may falls below the reference voltage V _REF, and outputs a defect detection signal V _FLT indicating abnormality. The comparator 112 is connected to a test power supply terminal T _TEST
Is the power supply.

When the comparison is completed, the next test pattern is input, and the combination of the states of the internal nodes of the CUT 102 changes to another combination. In this transition state, a much larger power supply current I _DDt flows than in the stationary state. In this case, the diode 113 provided in parallel with the current detection resistor 111 conducts, and the CUT 102
Is maintained at a value that allows the CUT 102 to operate normally.

[0009]

However, in the power supply current measuring device for a CMOS integrated circuit having the above configuration, I _DDq
There is a problem that it is difficult to reduce the time required for the test and the number of terminals of the chip increases.

Specifically, the voltage V _CUT and the reference voltage V _REF compared by the comparator 112 are very close to the power supply voltage V _DD applied to the power supply terminal T _DD during normal use. It is necessary to apply, as a power supply voltage, a voltage higher than the power supply voltage V _DD by at least the threshold value of the transistor included in the comparator 112. Here, similarly to the CUT 102, when the comparator 112 is configured by an enhancement type transistor, the threshold value is 0.6
[V]. Since this value is larger than the voltage drop allowed in the CUT 102, the chip 101
A terminal for supplying the power supply voltage of the comparator 112 (power supply terminal T _TEST for testing) is indispensable. In addition,
In general, the voltage drop allowed in the CUT 102 is limited to 10% or less of the power supply voltage V _{DD in} normal use. When the power supply voltage V _DD is 3 [V], the voltage drop is about 0.3 [V]. is there.

The resolution of the comparator 112 is usually about 1 [mV] with high accuracy, but in order to detect the fluctuation of the voltage V _CUT due to the fluctuation of the stationary power supply current I _DDq at this resolution. It is necessary to set the resistance value of the current detecting resistor 111 to a sufficiently large value and set the voltage drop of the resistor 111 large. However, CUT
In a range smaller than the voltage drop allowed in 102,
When the voltage drop of the resistor 111 is set, the detection accuracy is extremely reduced.

For example, if the resolution of the voltage measurable by the comparator 112 is 1 [mV / point], 0.3 [V]
In the range, 300 [points] can be compared. On the other hand, as described above, the quiescent power supply current I _DDq may reach from approximately 0 [μA] to several hundreds [μA]. Therefore, _if the maximum value of the quiescent power supply current I _DDq is 1000 [μA],
The resolution of the current that can be measured by the comparator 112 is:
3 [μA / point], and sufficient detection accuracy cannot be obtained.

In general, when there is a stuck-at fault, a minute stationary power supply current I _DDq flows even at rest. The quiescent power supply current I _DDq when a defect occurs due to a large resistive short _circuit, and the quiescent power supply current I _DDq when there is no defect.
_DDq is a very close value. In particular, a large-scale CMOS integrated circuit 102 currently manufactured is often provided with a pull-up resistor or a pull-down resistor, and even if the CMOS integrated circuit 102 has no defect,
A certain amount of power supply current I _DDq at rest flows. Therefore, sufficient detection accuracy is required to detect a defect.

As a result, in the above-described conventional configuration, in order to improve the detection accuracy, it is necessary to set the voltage drop at the current detection resistor 111 to be larger than the above-described limit.
A power supply terminal T _TEST for testing is indispensable in addition to the power supply terminal T _{DD in} normal use.

Here, the number of pins that can be installed on the chip 101 is limited by the dimensions of the chip 101. On the other hand, as the degree of integration increases, the number of pins required by the CUT 102 increases, and as the mounting density increases, there is a demand for chips 101 having smaller dimensions. Therefore, a reduction in the number of pins is strongly required.

In addition, when the resistance value of the current detecting resistor 111 is set to be large, the time constant becomes large, so that it takes time until the stationary power supply current I _DDq is stabilized. Here, in the I _DDq test, it is necessary to measure the quiescent power supply current I _DDq for each state of each internal node of the _{CUT 102. Therefore} , if one measurement time increases, I _DDq
The time required for the entire _DDq test is extremely long.

Furthermore, since the time required for one measurement is long, if the CUT 102 operates at a normal frequency, the stationary power supply current I _DDq cannot be measured correctly. As a result, I
The operating frequency during the _DDq test needs to be set much lower than the normal operating frequency. Therefore, although the same test pattern as the test pattern for the function test is used, the _IDDq test must be performed separately from the function test performed at the normal operation frequency. As a result, the time required for the entire test process of the chip 101 also becomes longer.

The present invention has been made in view of the above problems, and has as its object to provide a power supply current measuring device for a CMOS integrated circuit capable of measuring with high accuracy and high speed despite the small number of pins. It is to realize.

[0019]

The C according to the first aspect of the present invention.
In order to solve the above problem, a power supply current measuring device for a MOS integrated circuit is provided between a power supply terminal and a CMOS integrated circuit, and converts a power supply current of the CMOS integrated circuit into a voltage.
Current-voltage conversion means, and a first voltage-amplification means for amplifying the converted voltage.
Amplifying means, and a reference value setting means for setting a reference voltage,
Comparing the amplified voltage with the reference voltage, a CMOS
Determining means for determining the quality of the integrated circuit.

In the above configuration, when the I _DDq test is performed, a power supply voltage is applied to the CMOS integrated circuit via the power supply terminal. Here, when the internal node of the CMOS integrated circuit is in a quiescent state, an extremely small quiescent power supply current flows from the power supply terminal to the CMOS integrated circuit as compared with the operation. In this state (at rest), for example, the first current-voltage converter implemented as a resistance component or the like disposed between the power supply terminal and the CMOS integrated circuit converts the stationary power supply current into a voltage. The first amplifier amplifies the voltage. The amplified voltage is compared with a reference voltage by a determination unit to determine the quality of the CMOS integrated circuit.

According to the above configuration, the voltage converted by the first current-voltage converter is amplified by the first amplifier.
As a result, the equivalent resistance value of the first current-voltage converter can be determined regardless of the resolution of the determination unit.

Here, in order to carry out the I _DDq test at high speed, it is necessary that the quiescent power supply current be stabilized in a short period, and the equivalent resistance value of the first current-voltage conversion means is set to a small value. Is good. On the other hand, the resolution of the determination means has a limit determined by the circuit configuration and the like. Therefore, in order to improve the determination accuracy, it is desirable that the input voltage be large.

According to the above configuration, the equivalent resistance value of the first current-voltage converter can be determined irrespective of the resolution of the determination unit. Therefore, even if the resolution of the determination unit is the same, compared with the conventional configuration. Thus, the equivalent resistance value can be set small. As a result, it is possible to realize a power supply current measuring device for a CMOS integrated circuit that satisfies both the improvement of the determination accuracy and the reduction of the determination time.

Further, in the power supply current measuring device for a CMOS integrated circuit according to the second aspect of the present invention, in the configuration according to the first aspect of the present invention, the first current-to-voltage conversion means includes a resistor provided between an input and an output. And a resistance value of the resistor portion is set such that a quiescent power supply current of the CMOS integrated circuit is stabilized in a period shorter than a normal operation cycle of the CMOS integrated circuit. .

In the above configuration, the power supply current at rest can be stabilized in a short period by setting the resistance value of the resistor.
Even when the OS integrated circuit is operating at a normal frequency, the power supply current measuring device of the CMOS integrated circuit can determine the pass / fail. Therefore, the I _DDq test can be performed simultaneously with the function test for testing the logic function of the CMOS integrated circuit. This eliminates the need to provide a special period for the I _DDq test, thereby significantly reducing the test period of the power supply current measuring device for the CMOS integrated circuit.

According to a third aspect of the present invention, there is provided a power supply current measuring device for a CMOS integrated circuit, wherein the first current-to-voltage conversion means comprises the first current-to-voltage converter. A resistor provided between the input and output of the conversion means, and a voltage drop suppressor provided in parallel with the resistor and conducting when the voltage drop of the resistor exceeds a predetermined voltage. It is characterized by.

In the above configuration, when the power supply current of the CMOS integrated circuit increases, for example, when the state of the internal node of the CMOS integrated circuit changes, the voltage drop of the resistor increases. When the voltage drop exceeds a predetermined voltage (threshold value), for example, a voltage drop suppression unit constituted by a diode or the like conducts, and maintains the voltage drop at the threshold value. Thereby, the width of decrease in the power supply voltage applied to the CMOS integrated circuit is suppressed to the threshold value.

According to the above configuration, despite the fact that the resistor is provided between the power supply terminal and the CMOS integrated circuit,
The maximum value of the power voltage drop can be determined. Therefore,
Even if the power supply current increases, the power supply voltage is maintained at a voltage at which the CMOS integrated circuit can operate, and the CMOS integrated circuit can continue to operate normally.

Further, in the power supply current measuring device for a CMOS integrated circuit according to the invention of claim 4, in the configuration of the invention of claim 3, the predetermined voltage is equal to a power supply voltage allowed in the CMOS integrated circuit. It is characterized in that it is set to a value equal to or smaller than the decrease width.

According to the above configuration, the maximum value of the decrease width is C
The power supply voltage is limited to the range of the reduction of the power supply voltage allowed in the MOS integrated circuit. Therefore, the CMOS integrated circuit can operate normally even when the power supply voltage during normal operation is supplied to the power supply terminal. As a result, the power supply terminal used for power supply during normal operation and the power supply terminal used for the _IDDq test can be shared, and the number of terminals can be reduced.

When the first amplifier is driven by a voltage applied to the power supply terminal, the difference between the input voltage of the amplifier and the power supply voltage is a voltage drop in the first current-voltage converter. Therefore, when the voltage drop in the first current-voltage converter is small, the first amplifier cannot be realized by a circuit such as an enhancement type CMOS inverter. Here, if a depletion type CMOS inverter is used as the first amplifying means, the power consumption increases. On the other hand, if a terminal different from the power supply terminal is provided to supply a power supply voltage to the first amplifying means, the number of terminals increases.

On the other hand, the CM according to the invention of claim 5
A power supply current measuring device for an OS integrated circuit is described in claim 1, 2, 3, or 4.
In the configuration of the invention according to the fourth aspect, the first amplifying unit includes a level shifter that shifts the voltage converted by the current-voltage conversion unit, and an amplifier that amplifies the shifted voltage. And

In the above configuration, the voltage converted by the first current-voltage converter is level-shifted by the level shifter and amplified by the amplifier. Therefore, even when the voltage drop in the first current-voltage converter is small, a difference between the voltage input to the amplifier and the voltage applied to the power supply terminal can be secured.

As a result, for example, the amplifier can be constituted by a circuit with low power consumption such as an enhancement type CMOS inverter, so that the number of terminals can be increased without increasing the number of terminals.
The power consumption of the power supply current measuring device for the MOS integrated circuit can be reduced.

According to a sixth aspect of the present invention, in the power supply current measuring device for a CMOS integrated circuit according to the first, second, third, fourth, or fifth aspect of the invention, the reference value setting means sets the amount of current to be supplied. A current source that can be specified, a second current-to-voltage converter that is arranged between the current source and the power supply terminal and that converts a current supplied by the current source into a voltage, and amplifies the converted voltage. A second amplifying means for generating the reference voltage.

In the above configuration, similarly to the first current-voltage conversion means and the first amplification means (first system), the current supplied from the current source is supplied to the second current-voltage conversion means and the second current-voltage conversion means. The voltage is converted to a reference voltage by the amplifying means (second system). Therefore, for example, it is easy to set the characteristics of both systems to be the same, for example, by forming both systems with circuits having the same layout. As a result, the judging means can judge the quality of the CMOS integrated circuit with higher accuracy than when directly instructing the reference voltage.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the present invention.
This will be described below with reference to FIG.
That is, the power supply current measuring device of the CMOS integrated circuit according to the present embodiment is a device of a built-in current sensor (BICS) type, for example, as shown in FIG. 2 and a power supply current measuring device 3 thereof.

In addition to the input / output terminals of the CUT 2 (see FIG. 2), the chip 1 includes a ground terminal T _GND maintained at the ground level GND, and a control voltage V indicating a criterion in the _IDDq test. A control terminal T _CTL to which _CTL is applied _;
And a defect detection terminal T _FLT defects defect detection signal V _FLT indicated whether it is found is output by the test. In this configuration, since the control terminal T _CTL is provided, the criterion can be changed in spite of the built-in current sensor type device.

Further, the chip 1 is provided with a power supply terminal T _{DD that} is used for both power supply during the I _DDq test and power supply during normal use. Further, in the power supply current measuring device 3 according to the present embodiment, the comparison of the stationary power supply current I _DDq is performed in synchronization with the clock signal CK.
The chip 1 has a clock terminal _TCK .

In the I _DDq test, as in the normal use,
The power supply voltage V _DD is applied to the power supply terminal T _DD , and the ground terminal T _GND is grounded. Further, a control voltage _VCTL is applied to the control terminal _TCTL . Furthermore, the state of each internal node (internal circuit) (not shown) in the CUT 2 is determined by, for example, inputting a predetermined test pattern to the input / output terminal of the CUT 2. When the state of each internal node is stopped, the power supply current measuring device 3 sets the power supply current
And _DDQ, reference current I which is instructed as the control voltage V _CTL
REF (to be described later) to determine pass / _fail , and outputs a defect detection signal V _FLT from a defect detection terminal _TFLT . The pass / fail judgment is made for all combinations of states ("0" or "1") of each internal node to be inspected.
As the test pattern, for example, a function test pattern for testing a logical function of the CUT 2 for detecting a stuck-at fault is used.

More specifically, the power supply current measuring device 3 includes a power supply current I _DD which is disposed between the power supply terminal T _DD of the chip 1 and the power supply input of the CUT 2 and flows between them.
Current conversion to _CUTS - voltage converter (first current-voltage conversion means) 11, amplifier for outputting a voltage V _CuTa amplifies the voltage V _CUTS (first amplifying means) 12, the control voltage A reference value setting unit (reference value setting means) for outputting a reference voltage V _REFa as a reference for determining the voltage V _CUTa based on V _CTL
13 and a measured value comparing / determining unit (determining means) 14 for comparing the two voltages V _CUTa and V _REFa to generate a defect detection signal V _FLT.
And a clock generator 15 that supplies a clock signal to the measurement value comparison / determination unit 14.

A resistor 11a is provided between the input and output of the current-voltage converter 11, as shown in FIG. For example, as shown in FIG.
It is composed of an element equivalent to a resistor (indicated by R in the figure). The resistor 11a may be, for example, the resistor itself or a parasitic resistance of a wiring as long as the resistor is an element equivalent to the resistor. Further, it can be realized by a circuit using MOS transistors. As a result, the current-voltage converter 11 can convert a current into a voltage with linear characteristics.

Here, the resistance value of the resistance portion 11a is _maintained even when the largest static power supply current I _DDq flows.
1a is lower than the power supply voltage V _DD allowed by the CUT2.
Is set so as not to exceed the range of decrease. Specifically, in the general CUT 2, a voltage drop of about 10% of the power supply voltage V _DD is allowed. Therefore, _assuming that the normal power supply voltage V _DD is 3 [V] and the maximum value of the quiescent power supply current I _DDq is 1000 [μA], the resistance value of the resistor 11a is set to 300 [Ω] or less. Note that the resistance portion 11
The resistance value of a is not limited to this numerical value.
Allowable voltage drop in _UT2 and quiescent power supply current I _DDq
Is determined based on the maximum value of

Further, in the current-voltage converter 11 according to the present embodiment, the resistor 11a is connected in parallel with the resistor 11a.
Is provided with a voltage drop suppressing unit 11b for limiting the voltage between both ends to a predetermined threshold value or less. The voltage drop suppressing unit 11
b is configured by an element equivalent to a diode, for example, as shown in FIG. Here, the above-mentioned threshold value is also CU
The power supply voltage V _DD is set so as not to exceed the allowable decrease in the power supply voltage V _DD at T2. As an example, using the above numerical values, the threshold value is set to 0.3 [V] or less. Actually, the power supply voltage V _DD applied from the outside to the power supply terminal T _DD has some error, so that the resistance value of the resistor 11a and the voltage drop suppressor 11b
Is desirably set lower than the calculated value.

In the above configuration, as in the case where the state of the internal node (internal circuit) of the CUT 2 transitions between “0” and “1”, the transitional power supply current I _DDq which is much larger than the quiescent power supply current I _DDq. When I _DDt flows and the voltage across the resistor 11a exceeds the threshold, the voltage drop suppressor 11b conducts. As a result, the voltage across the resistor 11a, that is, the voltage drop of the current-voltage converter 11 is suppressed to the threshold value or less, and the power supply voltage V _DD allowed by the CUT 2 is reduced to the width or less.

As a result, for example, as shown in FIG.
CUT2 when the voltage drop suppressing unit 11b is not provided
Unlike the power supply input (voltage V1 _CUTs ), the power supply input (voltage V _CUTs ) to the CUT 2 according to the present embodiment can keep the fall from the normal power supply voltage V _DD within an allowable range.
In the example shown in FIG. 11, although the power supply current I _DD has increased to 250 [mA], the decrease width of the voltage V _CUTs is
0.3 [V] or less. As a result, although the same power supply voltage V _DD is supplied from the same power supply terminal T _DD as during normal use, the CUT 2 can continue to operate normally. Incidentally, the voltage drop suppression unit 11b, can be realized by a simple element like a diode, according to the power supply current I _DD, than construction for correcting the power supply voltage V _DD applied to the power supply terminal T _DD, the circuit configuration Can be simplified.

The amplifying unit 12 is configured by connecting transistors Tp1 and Tn1 operating as a level shifter 12a and transistors Tp2 and Tn2 operating as an amplifier 12b in series, for example, as shown in FIG. ing. More specifically, the level shifter 12
3A, a p-channel transistor Tp1 is a depletion-type FET (Depletion type FET), and a gate of the transistor Tp1 has a voltage V from a connection point between the current-voltage converter 11 and CUT2 shown in FIG.
_CUTs are applied. On the other hand, an n-channel transistor T
A predetermined bias voltage is applied to the gate of n1. The drains of the transistors Tp1 and Tn1, which are the outputs of the level shifter 12a, are connected to each other. The power supply voltage V _DD is applied to the source of the transistor Tp1, and the source of the transistor Tn1 is grounded.

In the above configuration, since the transistor Tp1 is a depression type, a current flows between the source and the drain even if the gate potential is very close to the power supply voltage V _DD . Therefore, a current _larger than the quiescent power supply current I _DDq flows between the source and the drain of the transistor Tp1. Further, the transistor Tn1 is always conductive by a predetermined bias voltage, and is used as a resistor. As a result, the level of the voltage V _CUTs is shifted by a width determined by the bias voltage.

Further, the level shifter 12 can be used during normal use.
During a period in which a is not used, no bias voltage is applied to the transistor Tn1, and the transistor Tn1 is shut off. Therefore, in spite of the depletion type, no current flows through the transistor Tp1 during this period, and the power consumption of the power supply current measuring device 3 can be suppressed.

On the other hand, the amplifier 12b is an inverter having a CMOS structure, and the input transistors Tp2 and Tn
2 are connected to each other, and the transistor Tp
1 · Tn1 connected to the drain. The drains of the transistors Tp2 and Tn2 are connected to each other, and can output the voltage V _CUTa as the output of the amplifier 12b. The power supply voltage V _DD is applied to the source of the transistor Tp2, and the source of the transistor Tn2 is grounded.

In the above configuration, both transistors Tp2 · T
n2 is used as an inverter in an amplification mode, amplifies the gate potentials of the transistors Tp2 and Tn2 (the drain potentials of the transistors Tp1 and Tn1), and generates a voltage V
_{Generate CUTa} . As a result, as shown in FIG. 12, the fluctuation _range of the voltage V _CUTs input to the amplifier 12 is 0.3 [V].
Although it is as small as within, the fluctuation _range of the output voltage V _CUTa is a very large value of about 2 [V]. FIG. 12 shows the case where the power supply voltage V _DD is set to 3 [V] and the CU
It is a simulation result at the time of using equivalent resistance instead of T2. Further, in the same figure, the resistance value of the resistance portion 11a is 50 [Ω], 120 [Ω], 170 [Ω], 250 [Ω].
2 shows both voltages V _CUTs and V _CUTa when they are set to [Ω] and 1000 [Ω], respectively. In FIGS. 12 and 13, for example, in the case of 50 [Ω],
As in V _CUTs50 and V _CUTa50 shown in FIG. 12, each resistance value is distinguished by adding a subscript indicating the resistance value.

Here, as an index of the accuracy of the amplification unit 12,
FIG. 13 shows the differential value D of the amplified voltage V _CUTa . As shown in the drawing, for example, the resistance value of the resistance portion 11a is 250
When [Ω] is set, the differential value D ₂₅₀ = dV
_CUTa250 / dI _DDq indicates that the quiescent power supply current I _DDq is 20
In the range of [μA] to 50 [μA], 25 [mV / μ
A], which is a high value. Therefore, when determining the quiescent power supply current I _DDq in this range, the resistance value is set to 25.
If it is set to 0 [Ω], amplification can be performed with high accuracy. In this case, for example, if the resolution of the measured value comparison / determination unit 14 shown in FIG. 1 is 3 [mV / point], 3 [mV] / 25 [mV /
μA] = 0.12 [μA / point], so the power supply current measuring device 3 can measure the stationary power supply current I _DDq with a very high accuracy of 0.12 [μA / point]. This value is about 10 times or more better than the conventional accuracy. Further, the resistance value of the differential value D ₁₂₀ in the case of 120 [Ω], the quiescent supply current I _DDQ is reduced at 100 [μA] or more regions. Therefore, when the resistance value is set to 120 [Ω], it is more preferable to measure the quiescent power supply current I _DDq of 100 [μA] or less.

On the other hand, in the present embodiment, as shown in FIG. 3, the reference value setting unit 13 shown in FIG. It is configured similarly to the circuit that generates V _CUTa . Specifically, as shown in FIG.
Resistor 13 similar to voltage drop suppressor 11b / amplifier 12
a, a voltage drop suppressing unit 13b and an amplifying unit 13c are provided. The resistor 13a and the voltage drop suppressor 13b
Corresponds to the second current-voltage conversion means described in the claims, and the amplifying section 13c corresponds to the second amplification means.

In particular, each of the members 13a to 13a according to this embodiment
3c is formed with the same circuit configuration, the same layout, and the same size as the corresponding members 11a, 11b, and 12. For example, the transistor Tn12 is formed with the same size as the corresponding transistor Tn2.

Therefore, even if variations in the manufacturing process or changes in the ambient temperature occur, the voltage V _CUTs is _changed to the voltage V _CUTa.
Circuit characteristics and the voltage V _REFs to the voltage V _REFa
The circuit characteristics of the system that amplifies
It is relatively easy to always match the two circuit characteristics. As a result, the quiescent power supply current I _DDq and the reference current I _REF can be compared with very high accuracy.

Meanwhile, (shown in the drawing VR) the reference current value setting unit 13d operates as an equivalent resistance of the normal CUT2, based on the control voltage V _CTL, the connection point between the resistor portions 13a an amplifier 13c The current I _REF flowing from the device can be increased or decreased. For example, as shown in FIG. 7, the reference current value setting unit 13d includes an n-channel MOS transistor Tn21, and a control voltage V _CTL is applied to a gate of the transistor Tn21 from a control terminal T _CTL shown in FIG. Is done. The drain of the transistor Tn21 is connected to the resistor 13a.
The source is connected to the ground, and the source is grounded. In this configuration, as shown in FIG. 14, the reference current I _REF flowing through the reference current value setting unit 13d is accurately controlled based on the control voltage V _CTL .

[0057] The measurement value comparison section 14 according to the present embodiment (see FIG. 1), to comparing the voltage V _CuTa and the voltage V _REFa with high accuracy, the clock inputted to the clock terminal T _CK It operates in synchronization with the signal CK. For example,
As shown in FIG. 8, the measured value comparison / determination unit 14 includes a switched capacitor type analog comparator 14a that outputs a voltage _VA corresponding to the difference between the two voltages V _CUTa and V _REFa.
And the two voltages V _CUTa and V _REFa based on the voltage V _A.
It provided a determining section 14b the magnitude of an output unit 14c for converting the output voltage V _B of the determination section 14b to the logical potential ( "0" or "1"), and outputs a defect detection signal V _FLT is Have been.

Before describing the members 14a to 14c in detail, the clock generator 15 for generating the clock signals CK1 to CK3 and CK1n to CK3n to be applied to the members 14a to 14c will be briefly described. That is, for example, as shown in FIG. 9, the clock generator 15 is configured by cascading inverters Inv1 to Inv9, and the input of the first-stage inverter Inv1 is:
It is connected to the clock terminal _TCK shown in FIG. Also,
The output of the ninth-stage inverter Inv9 is the clock signal C
The output of the inverter Inv8 at the preceding stage is supplied to the measured value comparison / determination unit 14 as K3.
The clock signal CK3n has a phase opposite to that of K3. Similarly, 7
And the outputs of the inverters Inv7 and Inv6 of the sixth stage become clock signals CK2 and CK2n.
The outputs of the inverters Inv5 and Inv4 at the stage are output as clock signals CK1 and CK1n,
Given to.

On the other hand, in the measured value comparison / determination section 14, the analog comparator 14a outputs the stationary power supply current I from the amplification section 12 shown in FIG.
Switch voltage V _CuTa corresponding to _DDq is input S11
And the reference voltage V from the reference value setting unit 13 shown in FIG.
_REFa is input to the switch S12 and both switches S11
A capacitor C11 having one end connected to the output of S12
And an inverter Inv11 having the other end of the capacitor C11 connected to the input, and a switch S13 capable of connecting the input and output of the inverter Inv11. Each of the switches S11 and S12 is an analog switch,
The conduction / cutoff is controlled based on two clock signals having phases opposite to each other. Clock signals CK3 and CK3 are supplied to both switches S11 and S12 as clock signals.
n is applied. However, both switches S11 and S1
2, the clock signals CK3 and CK3n are applied in reverse, and the clock signal CK3 is at a low level (logic "
0 "), the switch S11 conducts, whereas the switch S12 conducts when the clock signal CK3 is at a high level (logic" 1 ").
The clock signal CK2 · CK2n is applied to 13 and is turned on when the clock signal CK2 is at a high level.

In the above configuration, the analog comparator 14
a, if the clock signal CK is at the low level, the input voltage V _REFa to the capacitor C11, while the clock signal CK is at a high level, as shown in FIG. 15, while the input voltage V _CuTa, recorded By comparing the voltage V _REFa with the voltage V _REFa , an output voltage _VA corresponding to the difference between the two voltages V _REFa and V _CUTa can be output. FIG. 15 shows that the frequency of the clock signal CK is 1
00 [MHz], as the voltage V _REFa, with give 1.8 V, as the voltage V _CuTa, the simulation results in the case of applying the 2 [V] or 1.797 [V].

The determination unit 14b determines whether the inverter Inv
21 and the analog comparator 14
amplifies the output voltage V _A of a, and generates an output voltage V _B. Accordingly, the output voltage V _B while the clock signal CK is at the high level approaches the logic “1” when the _measured voltage V _CUTa is higher than the reference voltage V _REFa , and when the measured voltage V _CUa is _lower than the reference voltage V _REFa , the output voltage V _B becomes lower. V _B is closer to the logic "0".

[0062] Further, the output unit 14c is a two-stage transmission gate latches, as a latch in the first stage, the switch S3 to the voltage V _B is applied to one end
1, an inverter Inv31 connected to the other end of the switch S31, an inverter Inv32 cascaded and connected to the inverter Inv31, and an inverter Inv.
A switch S32 arranged between the output of the inverter 32 and the input of the inverter Inv31. Switch S
Both clock signals CK1 and CK1n are input to 31 and S32 as clock signals. However, both switches S31 and S32 are connected to clock signals CK1 and CK1n.
Are connected in reverse, and the switch S31 is turned on while the clock signal CK1 is at the low level, whereas the switch S32 is turned on while the clock signal CK1 is at the high level. On the other hand, switches S41 and S42 and an inverter I connected in the same manner as the first stage latch are used as the second stage latch.
nv41 and Inv42. However, contrary to the first stage, the clock signals CK1 and CK1n are supplied so that when the clock signal CK1 is at a low level, the switch S41 is turned off and the switch S42 is turned on. A switch S41 which is an input of the second-stage latch
Is connected to the output of the inverter Inv31. Further, the output of the inverter Inv41 is supplied to the defect detection terminal T _FLT shown in FIG.
It is connected to the. As a result, the output unit 14 c
As shown in 5, when the clock signal CK is output voltage V _B is high-level determination section 14b at the low level, the logic "0", when a low level, the defect detection signal V _FLT logic "1" Can be output.

[0063] In this result, the power supply current measuring device 3 shown in FIG. 10, the defect detection signal V _FLT output from the measured value comparison determination unit 14, when the voltage V _CuTa below the voltage V _REFa, i.e., at rest The power supply current I _DDq is _equal to the reference current I
_{When REF} is exceeded, the logic “1” and the voltage V _CUTa are smaller, that is, the quiescent power supply current I _DDq shown in FIG.
Is less than the reference current I _REF , the logic becomes “0”. Although FIG. 10 shows the connection of each member of the power supply current measuring device 3, the clock generator 15 is omitted for convenience of explanation.

Here, as described above, the equivalent resistance value of the current-voltage converter 11 shown in FIG.
The resistance value of (a) is set to an extremely small value so that the CUT 2 does not exceed an allowable voltage drop even when the maximum stationary power supply current I _DDq flows. The resistance of the resistance section 11a and the voltage drop suppression section 11b is maintained at a sufficiently small value, for example, by using a circuit including a MOS transistor. As a result, the time constant of the current-voltage converter 11 is extremely small,
The quiescent power supply current I _DDq is stabilized in a period sufficiently shorter than the normal operation cycle of the CUT 2, for example.

The time constant indicating the speed at which the stationary power supply current I _DDq is stabilized is, for example, from the power supply terminal T _DD to CUT 2.
To the path from the power supply terminal T _DD to the CUT 2 and the load capacitance of the CUT 2.
[Hz], the above condition can be satisfied by setting the resistance value of the resistance portion 11a to a sufficiently low value of, for example, about 50 [Ω] to 1000 [Ω].

As a result, the power supply current measuring device 3
2 is operating at the normal operating frequency,
The stationary power supply current I _DDq can be accurately measured, and _{pass / fail} can be determined. Therefore, not only can the required time of the I _DDq test be significantly reduced, but also the I _DDq test and the function test using the same test pattern can be performed simultaneously. This eliminates the need for the conventional I _DDq test time, and can greatly reduce the time required for the entire CUT 2 test.

As an example, at an operating frequency of 100 [MHz], the resistance value of the reference current value setting unit 13d is set to 300.
[KΩ], the reference value current I _REF is set to 10 [μA], and the resistance value of the resistor 11a is set to 120 [Ω].
Was simulated. As a result,
As shown in FIG. 16, the resistor simulating CUT2 has 9 resistors.
When passing a quiescent power supply current I _DDQ of [μA], the power supply current measuring device 3 judges the CUT2 to normal, as shown in FIG. 17, when the quiescent supply current I _DDQ is 11 [μA] Was determined to be abnormal. That is, the power supply current measuring device 3 determines the quality of the CUT 2 at a very high operating frequency of 100 [MHz] with a very high accuracy of 1 [μA].

Incidentally, in the above description, the resistance portion 1 shown in FIG.
Although the case where the resistance values of 1a and 13a are set to suitable values in advance has been described, resistors having a plurality of resistance values may be prepared and switched. Further, for example, similarly to the reference current value setting unit 13d shown in FIG. 3, the resistance value may be changed according to the control voltage from the control terminal.

As described above, when variable resistors are used as the resistance portions 11a and 13a, the power supply current measuring device 3 is provided in the chip 1 as shown in FIG.
The waveform of the output voltage V _CUTs of the current-voltage converter 11 can be made sharp or gentle. Thereby, as shown in FIG. 13, the detection accuracy of the power supply current measuring device 3 can be changed. For example, improved by increasing the resistance, the waveform of the voltage V _CUTS changes sharply, since the decline of the voltage V _CUTS becomes relatively large, quiescent supply current I _DDQ is the detection accuracy in the minute region it can. Therefore, the quiescent power supply current I
If the resistance values of the resistance parts 11a and 13a are set in accordance with the reference current I _REF which is a criterion for determining _DDq , both resistance parts 11a
The detection accuracy can be improved over a wider range than when the resistance value of 13a is fixed.

Although the power supply current measuring device 3 according to the present embodiment is provided with the clock terminal _TCK , a circuit that operates without using the clock signal CK may be used as the measured value comparison / determination unit 14. For example, the clock terminal _TCK can be omitted. The power supply current measuring device 3 according to the present embodiment
The ability to operate in the normal operating frequency during the CUT2, for example if CUT2 is CPU, when the chip 1 already has a clock terminal T _CK is without any trouble, can share the clock terminal T _CK.

Further, in this embodiment, the defect detection signal V
_{Although a} defect detection terminal T _FLT is provided to output _FLT , a register for storing the defect detection signal V _FLT is provided, and if the contents of the register are accessed by the input / output terminal of the CUT 2 shown in FIG. The detection terminal T _FLT can be omitted. Similarly, for example, a register for storing a value indicating a control voltage V _CTL provided, if access to the contents of the register by the input and output terminals of CUT2, can be omitted control voltage V _CTL. However, if the defect detection terminal T _FLT or the control terminal T _CTL is separately provided, it is not necessary to input a predetermined pattern to the input terminal of the CUT 2 and access each of the above-mentioned registers. Can be determined.

[0072]

As described above, the power supply current measuring device for a CMOS integrated circuit according to the first aspect of the present invention has a power supply terminal and a CM.
A first current-voltage converter arranged between the OS integrated circuit for converting a power supply current of the CMOS integrated circuit into a voltage, a first amplifier for amplifying the converted voltage, and a reference for setting a reference voltage This configuration includes a value setting unit and a determination unit that compares the amplified voltage with a reference voltage to determine whether the CMOS integrated circuit is good or not.

According to the above configuration, the voltage converted by the first current-to-voltage converter is amplified by the first amplifier.
Therefore, the equivalent resistance value of the first current-voltage converter can be determined regardless of the resolution of the determiner. Therefore, a CMO that satisfies both the improvement of determination accuracy and the reduction of determination time
There is an effect that a power supply current measuring device for an S integrated circuit can be realized.

According to the power supply current measuring device for a CMOS integrated circuit according to the second aspect of the present invention, as described above, in the configuration of the first aspect, the first current-voltage converting means is provided between the input and the output. The resistance value of the resistance portion is set so that the power supply current at rest of the CMOS integrated circuit is stabilized during a period shorter than the normal operation cycle of the CMOS integrated circuit. is there.

According to the above configuration, the stationary power supply current is stabilized in a short period of time by setting the resistance value of the resistance portion.
Even when the CMOS integrated circuit operates at a normal frequency, the power supply current measuring device for the CMOS integrated circuit can determine the pass / fail. Therefore, the I _DDq test can be performed simultaneously with the function test, and the test period of the CMOS integrated circuit can be greatly reduced.

The power supply current measuring device for a CMOS integrated circuit according to the third aspect of the present invention is as described above.
In the configuration of the invention described above, the first current-to-voltage converter is provided in parallel with the resistor provided between the input and output, and the voltage drop of the resistor exceeds a predetermined voltage. And a voltage drop suppressing unit that conducts in a case.

According to the above configuration, although the resistor is provided between the power supply terminal and the CMOS integrated circuit,
The maximum value of the power voltage drop can be determined. Therefore, there is an effect that the CMOS integrated circuit can continue to operate normally even if the power supply current increases.

In the power supply current measuring device for a CMOS integrated circuit according to the fourth aspect of the present invention, as described above, in the configuration of the third aspect of the present invention, the predetermined voltage is allowed in the CMOS integrated circuit. In this configuration, the power supply voltage is set to a value equal to or smaller than the decrease width.

According to the above configuration, the CMOS integrated circuit can operate normally even when the power supply voltage during normal operation is supplied to the power supply terminal. Therefore, the power supply terminal used for power supply during normal operation and the power supply terminal used for the _IDDq test can be shared, and the number of terminals can be reduced.

The power supply current measuring device for a CMOS integrated circuit according to the invention of claim 5 is as described above.
In the configuration of the invention according to the fourth aspect, the first amplifying means includes a level shifter for shifting the voltage converted by the current-to-voltage converting means, and an amplifier for amplifying the shifted voltage. .

According to the above configuration, even if the voltage drop in the first current-to-voltage converter is small, the difference between the voltage input to the amplifier and the voltage applied to the power supply terminal is ensured by the level shifter. Is done. Therefore, since the amplifier can be configured by a circuit with low power consumption, the power consumption of the power supply current measuring device for the CMOS integrated circuit can be reduced without increasing the number of terminals.

The power supply current measuring device for a CMOS integrated circuit according to the invention of claim 6 is as described above.
In the configuration of the invention described in 3, 4, or 5, the reference value setting means is arranged between a current source capable of specifying an amount of current to be supplied and the current source and the power supply terminal, and And a second amplifying means for amplifying the converted voltage to generate the reference voltage.

According to the above configuration, similarly to the first current-to-voltage converter and the first amplifier (the first system), the current supplied by the current source is equal to the second current-to-voltage converter and the second amplifier. The signal is converted into a reference voltage by the second amplification means (second system). Therefore, it is easy to set the characteristics of both systems to be the same, and it is possible to further improve the determination accuracy of the power supply current measuring device for the CMOS integrated circuit.

[Brief description of the drawings]

FIG. 1 illustrates one embodiment of the present invention, wherein a CMO
FIG. 2 is a block diagram illustrating a main configuration of a chip including an S integrated circuit and a power supply current measuring device thereof.

FIG. 2 is a block diagram showing general inputs and outputs of the CMOS integrated circuit.

FIG. 3 is a block diagram illustrating the chip in further detail.

FIG. 4 is a circuit diagram showing a current-voltage converter in the power supply current measuring device for a CMOS integrated circuit.

FIG. 5 is a circuit diagram showing an amplifying unit in the power supply current measuring device for a CMOS integrated circuit.

FIG. 6 is a circuit diagram showing a reference value setting unit in the power supply current measuring device for a CMOS integrated circuit.

FIG. 7 is a circuit diagram showing a configuration example of a reference current value setting section in the reference value setting section.

FIG. 8 is a circuit diagram showing a measured value comparison and determination unit in the power supply current measuring device for a CMOS integrated circuit.

FIG. 9 is a circuit diagram showing a clock generator of a measured value comparison / determination unit in the power supply current measuring device for a CMOS integrated circuit.

FIG. 10 is a circuit diagram showing an entire power supply current measuring device for the CMOS integrated circuit.

FIG. 11 is a waveform diagram showing an operation of the current-to-voltage converter and showing an output voltage of the current-to-voltage converter.

FIG. 12 is a diagram showing the operation of the current-voltage conversion unit and the amplification unit, and is a waveform diagram showing input / output voltages of the amplification unit when resistance values of resistors of the current-voltage conversion unit are set to different values. It is.

FIG. 13 is a waveform diagram showing the detection accuracy of the current-voltage converter and the amplifier, and showing the derivative of the output voltage of the amplifier when the resistances of the resistors are set to different values.

FIG. 14 is a graph showing characteristics of the reference current value setting section and showing a reference current value with respect to a control voltage.

FIG. 15 is a waveform diagram showing operation waveforms of the power supply current measuring device of the CMOS integrated circuit, and showing a result of simulating each voltage.

FIG. 16 is a waveform diagram showing an operation waveform of the power supply current measuring device of the CMOS integrated circuit, and showing a result of simulating each voltage when the power supply current at rest is a normal value.

FIG. 17 is a waveform diagram showing an operation waveform of the power supply current measuring device of the CMOS integrated circuit, and showing a result of simulating each voltage when the power supply current at rest is an abnormal value.

FIG. 18 illustrates a conventional example, and is a block diagram illustrating a main configuration of a chip including a CMOS integrated circuit and a power supply current measuring device thereof.

[Explanation of symbols]

Reference Signs List 2 CMOS integrated circuit 3 Power supply current measuring device 11 Current-voltage converter (first current-voltage converter) 11a Resistor 11b Voltage drop suppressor 12 Amplifier (first amplifier) 12a Level shifter 12b Amplifier 13 Reference value setting Unit (reference value setting unit) 13a Resistance unit (second current-voltage conversion unit) 13b Voltage drop suppression unit (second current-voltage conversion unit) 13c Amplification unit (second amplification unit) 13d Reference current value setting unit ( Current source) 14 Measured value comparison and judgment unit (judgment means) T _DD power supply terminal

Claims (6)

[Claims] A first terminal connected between a power supply terminal and the CMOS integrated circuit for converting a power supply current of the CMOS integrated circuit into a voltage;
Current-voltage converting means, first amplifying means for amplifying the converted voltage, reference value setting means for setting a reference voltage, and comparing the amplified voltage with the reference voltage,
A power supply current measuring device for a CMOS integrated circuit, comprising: means for determining whether the integrated circuit is good or bad. 2. The method according to claim 1, wherein the first current-to-voltage converter includes a resistor provided between an input and an output, and a resistance value of the resistor is shorter than a normal operation cycle of the CMOS integrated circuit. 2. The power supply current measuring device for a CMOS integrated circuit according to claim 1, wherein the power supply current at rest of the CMOS integrated circuit is set to be stable. 3. The first current-to-voltage conversion means is provided in parallel with a resistor provided between the input and output, and the resistor is provided.
3. The power supply current measuring device for a CMOS integrated circuit according to claim 1, further comprising: a voltage drop suppressing unit that conducts when a voltage drop of the resistor unit exceeds a predetermined voltage. 4. The power supply current measurement of a CMOS integrated circuit according to claim 3, wherein said predetermined voltage is set to a value equal to or less than a reduction width of a power supply voltage allowed in said CMOS integrated circuit. apparatus. 5. The apparatus according to claim 1, wherein the first amplifying means includes a level shifter for shifting the voltage converted by the first current / voltage converting means, and an amplifier for amplifying the shifted voltage. The power supply current measuring device for a CMOS integrated circuit according to claim 1, 2, 3, or 4. 6. The reference value setting means is disposed between a current source capable of designating a current amount to be supplied and the current source and the power supply terminal, and converts a current supplied by the current source into a voltage. A second current-to-voltage conversion unit, a second current-to-voltage conversion unit that amplifies the converted voltage to generate the reference voltage
And amplifying means.
The power supply current measuring device for a CMOS integrated circuit according to 2, 3, 4 or 5.