JPH09159721A - Method for measuring semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure the characteristics of a MOS(metal oxide semiconductor) transistor over a wide range without using any monitor chip. SOLUTION: A semiconductor integrated circuit 10 is incorporated with an N-channel MOS transistor 14 which works as a pull-up resistor. The drain, gate, and source of the transistor 14 are respectively connected to the input terminal 17, Vcc terminal 15, and GND terminal 16 of the circuit 10. When the electric current flowing to the input terminal 17 is measured with an ammeter 18 by changing the voltage of a power source 19, the source and drain currents of the transistor 14 can be measured directly and the threshold voltage and gain constant of the circuit 10 can be measured from the graph plotting the source and drain currents.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to evaluation of a manufacturing process for forming a semiconductor integrated circuit, such as a metal oxide semiconductor field effect transistor (hereinafter referred to as "MOS transistor").
Is abbreviated. ), A method for measuring a semiconductor integrated circuit for evaluating characteristics such as threshold value and gain constant.

[0002]

2. Description of the Related Art Conventionally, P which constitutes a semiconductor integrated circuit
The threshold voltage and the gain constant of the channel type MOS transistor and the N channel type MOS transistor are treated as one of important parameters for evaluating the semiconductor integrated circuit. This is because the history of the semiconductor manufacturing process is reflected in these characteristics. If these can be measured by a large-scale integrated circuit (hereinafter abbreviated as “LSI”) tester or the like, the manufacturing process and quality control of the semiconductor integrated circuit become very easy. For example, in order to perform screening for removing a semiconductor integrated circuit that causes a defect that occurs only at high temperature or a defect that occurs only at low temperature, it is necessary to perform various tests specified in advance at high temperature and low temperature. However, these defects include those that occur depending on the threshold voltage or gain constant of the MOS transistor. Therefore, if the threshold voltage and the gain constant of the MOS transistor are managed within a certain specification, that is, the specification standard range, and screening is performed to remove those outside the range, the man-hours for the high temperature test and the low temperature test can be reduced.

Conventionally, a monitor chip for measuring characteristics is simultaneously formed on the same semiconductor substrate as the semiconductor integrated circuit, and the characteristics of the monitor chip are measured to evaluate the semiconductor integrated circuit. The monitor chip includes a P-channel type MOS transistor and an N-channel type M for exclusive use in threshold voltage measurement.
An OS transistor is formed, and a pad for connecting a needle probe of an LSI tester is provided to each of the source, drain, and gate electrodes.

FIG. 12 shows a basic configuration for performing characteristic measurement using a monitor chip in (a), and shows an example of measurement results in (b). As shown in FIG.
In the channel-type MOS transistor 1, the source 2 is set to the reference common ground potential, and the drain voltage Vsd and the gate voltage Vg are applied to the drain 3 and the gate 4 from the drain voltage source 5 and the gate voltage source 6, respectively. The source / drain current Isd is measured by the ammeter 7. FIG.
As shown in (b), if the absolute value of the drain voltage Vsd becomes larger than a certain level, the source / drain current Isd enters a saturation region where it becomes almost constant even if the drain voltage Vds is changed.

Source / drain current I in the saturated region and the unsaturated region of the N-channel MOS transistor 1.
The sd is, for example, the following formula published as the formula (2.5) on page 17 of "LSI Technology" issued as a fifth edition by the Institute of Electrical Communication of Japan on July 10, 1981. It is represented by Formula 1 and Formula 2, respectively. In addition,
The threshold voltage is Vth and the gain constant is β.

Isd = (β / 2) × (Vg−Vth) ² (1) Isd = 0 (2) Here, when the first expression is Vg> Vth, the second expression is Vg <V
applied in the case of th. In FIG. 12A, if the gate voltage Vg given from the gate voltage source 6 to the gate 4 of the N-channel type MOS transistor 1 is changed and the source / drain current Isd indicated by the ammeter 7 is plotted, the threshold voltage Vth and the gain are obtained. The constant β can be obtained. It is assumed that the threshold voltage Vth and the gain constant β reflect the manufacturing process of the semiconductor integrated circuit and the like, and the characteristics of the semiconductor integrated circuit itself also change in response to the changes.

A method of measuring a threshold voltage and a gain constant using a P-channel type MOS transistor and an N-channel type MOS transistor included in the semiconductor integrated circuit itself without using a monitor chip is disclosed in, for example, Japanese Patent Laid-Open No. 2-187. Proposed in 1569. In this prior art, an input buffer composed of a P-channel type MOS transistor and an N-channel type MOS transistor is used as an evaluation MOS transistor of a semiconductor integrated circuit. That is, one or both of the threshold voltage and the gain constant are obtained by measuring the power supply voltage value connected to the input buffer and the current consumption of the corresponding input buffer.

[0008]

A P-channel type MOS formed as a monitor chip which is generally used in the past.
In the method of measuring the threshold voltage and gain constant of a transistor or N-channel MOS transistor, it is necessary to specially prepare a monitor chip for measurement on the same semiconductor substrate as the semiconductor integrated circuit. The separate preparation increases the number of pads and may increase the chip size.

In the prior art of Japanese Patent Laid-Open No. 2-1569, although the chip size does not increase, the measurement principle
It is necessary to be able to calculate the current consumption of the input buffer that is measured from the power supply current. The power supply voltage value connected to the input buffer and the current consumption of the input buffer are measured, and either or both of the threshold voltage and the gain constant are obtained.Therefore, measure the current consumption at the power supply pin and measure the corresponding input buffer. This is because the consumed current is calculated. That is,
It is a prerequisite for applying this prior art that the current consumption of circuits other than the input buffer to be measured does not interfere with the measurement of the current consumption of the input buffer. For example, in FIG. 1 of this prior art, the current value indicated by the ammeter 7 is the sum of the current consumption value of the input buffer circuit 5 and the current consumption value of the semiconductor circuit 6, and the current consumption value of the semiconductor circuit 6 is Dependent. Therefore, the operation of the semiconductor circuit 6 needs to be set so that the current consumption is reduced as much as possible.

An object of the present invention is to provide a method for measuring a semiconductor integrated circuit which does not require the use of a monitor chip and can be easily applied to a wide range of semiconductor integrated circuits.

[0011]

The present invention provides a measuring method for evaluating a semiconductor integrated circuit including a MOS transistor capable of directly measuring the source / drain current Isd.
Sufficient voltage is applied between the source and drain of the MOS transistor, the source / drain current Isd is measured under a plurality of power supply voltage conditions, and the characteristic of the MOS transistor is determined based on the measurement result. It is a method of measuring a semiconductor integrated circuit, which is characterized by calculating. According to the present invention, a sufficient voltage is applied between the source and drain of the MOS transistor to bring it into a saturated state,
When the power supply voltage is changed, the gate voltage changes and the source
The drain current Isd changes. Source / drain current Isd
Can be measured directly, so that the characteristics can be easily measured. Further, since there are many semiconductor integrated circuits including MOS transistors capable of directly measuring the source / drain current, they can be widely applied.

According to the present invention, the MOS transistor is connected to pull up or pull down an input terminal or an output terminal, and the source / drain current Isd is connected to the input terminal or the output terminal to which the MOS transistor is connected. It is characterized by measuring the current flowing in the. According to the invention, since the MOS transistor is connected so as to pull up or pull down the input terminal or the output terminal, the source / drain current Isd can be easily measured by measuring the current flowing through the input terminal or the output terminal. Can be measured.

In the present invention, the MOS transistor is used as an output buffer whose source or drain is connected to the output terminal, and the source-drain current Isd is a current flowing through the output terminal to which the MOS transistor is connected. It is characterized by measuring. According to the present invention, since the source / drain current Isd to the output buffer flows through the output terminal, it can be easily measured.

Further, according to the present invention, the characteristic of the MOS transistor is at least one of a threshold voltage and a gain constant. According to the present invention, since the gate voltage of the MOS transistor is changed by the power supply voltage and the source / drain current Isd is measured, the characteristics of at least one of the threshold voltage and the gain constant can be easily measured.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic configuration of a first embodiment of the present invention. In the semiconductor integrated circuit 10,
An input circuit 11 and an internal logic circuit 12 are included. An N-channel MOS transistor 14 that operates as a pull-down resistor is connected to the input side of the input buffer 13 in the input circuit 11. The gate, source and drain of the N-channel type MOS transistor 14 are the Vcc terminal 15 which is a positive power source terminal and the G side which is a ground side power source terminal.
They are connected to the ND terminal 16 and the input terminal 17, respectively. The N-channel MOS transistor 14 is in the ON state, the source / drain current Isd can be measured by the ammeter 18 inserted between the input terminal 17 and the Vcc terminal 15, and the gate voltage is equal to the voltage of the power supply 19. Therefore, the voltage applied to the input terminal 17 when measuring the range of the source-drain voltage Vsd where the above-mentioned first expression holds, that is, the pull-down current, is the N-channel type MOS.
If the relationship between the power supply voltage and the input current is measured at least twice within a range large enough to allow a saturation current to flow between the source and drain of the transistor 14,
The threshold voltage Vth and the gain constant β can be obtained by the method described later.

FIG. 2 shows a schematic configuration of the second embodiment of the present invention. The semiconductor integrated circuit 20 includes an input / output circuit 21 and an internal logic circuit 22. On the input / output side of a high impedance (hereinafter abbreviated as “HiZ”) input / output buffer 23 in the input / output circuit 21, an N-channel MOS transistor 2 that operates as a pull-down resistor
4 are connected. The gate, source and drain of the N-channel type MOS transistor 24 have a Vcc terminal 25 which is a positive side power supply terminal and a ground side power supply terminal GND.
It is connected to the terminal 26 and the input / output terminal 27, respectively. The N-channel MOS transistor 24 is in the ON state, the source / drain current Isd can be measured by the ammeter 18 inserted between the input / output terminal 27 and the Vcc terminal 25, and the gate voltage is equal to the voltage of the power supply 19. . Therefore, the measurement can be performed by the same procedure as the embodiment of FIG.

FIG. 3 shows a schematic configuration of the third embodiment of the present invention. The semiconductor integrated circuit 30 includes an output circuit 31 and an internal logic circuit 32. Output circuit 3
An N-channel MOS transistor 34 that operates as a pull-down resistor is connected to the output side of the output buffer 33 in the circuit 1. N-channel MOS transistor 34
The gate, source, and drain of are connected to the Vcc terminal 35, which is the positive power supply terminal, the GND terminal 36, which is the ground power supply terminal, and the input / output terminal 37, respectively. The N-channel MOS transistor 34 is in the ON state, and the source / drain current Isd is output terminal 37 and Vcc.
It can be measured by the ammeter 18 inserted between the terminal 35 and the gate voltage, and the gate voltage is equal to the voltage of the power supply 19. Therefore, if the output buffer 33 is set to the high impedance state, the measurement can be performed by the same procedure as the embodiment of FIG.

FIG. 4 shows a schematic configuration of the fourth embodiment of the present invention. The semiconductor integrated circuit 40 includes an output circuit 41 and an internal logic circuit 42. Output circuit 4
1 includes a series circuit of a P-channel type MOS transistor 43 and an N-channel type MOS transistor 44. The drain and gate of the P-channel MOS transistor 43 and the drain and gate of the N-channel MOS transistor 44 are commonly connected. The sources of the P-channel type MOS transistor 43 and the N-channel type MOS transistor 44 are respectively connected to the Vcc terminal 45 which is the positive power source terminal and the GND terminal 46 which is the ground side power source terminal. The commonly connected gates and drains are connected to the output side and the output terminal 47 of the internal logic circuit 42, respectively.
The output state of the N-channel MOS transistor 44 is changed to LO.
If the logic level on the W side, that is, the ON state can be set, the source / drain current Isd of the N-channel type MOS transistor 44 is output at the LOW level by the ammeter 18 inserted between the output terminal 47 and the Vcc terminal 45. It can be measured as an electric current. As the gate voltage, a voltage equal to the voltage of the power supply 19 is given from the internal logic circuit 42. The source-drain voltage of the N-channel MOS transistor 44 is equal to the voltage applied to the output terminal 47 when measuring the LOW level output current. Therefore, as long as the voltage applied to the output terminal 47 is large enough to allow the saturation current to flow between the source and drain of the N-channel MOS transistor 44, the relationship between the power supply voltage and the input current should be at least twice. If the above measurement is performed, the threshold voltage Vth and the gain constant β can be obtained by the method described later. Such an output circuit 41 is a CMOS
Widely used as a semiconductor integrated circuit.

FIG. 5 shows a schematic configuration of the fifth embodiment of the present invention. The semiconductor integrated circuit 50 includes an input circuit 51 and an internal logic circuit 52. Input circuit 5
A P-channel type MOS transistor 54 that operates as a pull-up resistor is connected to the input side of the input buffer 53 in 1. P-channel MOS transistor 54
The source, gate, and drain of are connected to the Vcc terminal 55, which is the positive power supply terminal, the GND terminal 56, which is the ground power supply terminal, and the input terminal 57, respectively.
The P-channel MOS transistor 54 is in the ON state, and the source / drain current Isd is the same as the input terminal 57 and GND.
It can be measured by the ammeter 18 inserted between the terminal 56 and the terminal 56, and the gate voltage is equal to the voltage of the power supply 19. Therefore, if the signs of voltage and current are made negative, the above-mentioned first
The range of the source-drain voltage Vsd where the formula is satisfied, that is, the voltage applied to the input terminal 17 when measuring the pull-down current is such that a saturation current can flow between the source and drain of the N-channel MOS transistor 14. If the relationship between the power supply voltage and the input current is measured at least twice within a sufficiently large range, the threshold voltage Vth and the gain constant β can be obtained by the method described later.

FIG. 6 shows a schematic configuration of the sixth embodiment of the present invention. The semiconductor integrated circuit 60 includes an input / output circuit 61 and an internal logic circuit 62. On the input / output side of the HiZ input / output buffer 63 in the input / output circuit 61,
A P-channel MOS transistor 64 that operates as a pull-up resistor is connected. The source, gate and drain of the P-channel MOS transistor 64 are connected to the Vcc terminal 65 which is a positive power source terminal, the GND terminal 66 which is a ground power source terminal, and the input / output terminal 67, respectively. P-channel MOS transistor 64
Is an ON state, and the source / drain current Isd is an ammeter 18 inserted between the input / output terminal 67 and the GND terminal 66.
And the gate voltage is equal to the voltage of the power supply 19. Therefore, the measurement can be performed by the same procedure as the embodiment of FIG.

FIG. 7 shows a schematic configuration of the seventh embodiment of the present invention. The semiconductor integrated circuit 70 includes an output circuit 31 and an internal logic circuit 32. Output circuit 3
The input / output side of the output buffer 73 in 1 is a P-channel MOS transistor 74 that operates as a pull-up resistor.
Is connected. P-channel type MOS transistor 7
The source, gate and drain of No. 4 are connected to the Vcc terminal 75, which is the positive power supply terminal, the GND terminal 76, which is the ground power supply terminal, and the input / output terminal 77, respectively. The P-channel type MOS transistor 74 is in the ON state, and the source / drain current Isd is output to the output terminal 37 and GN.
It can be measured by the ammeter 18 inserted between the D terminal 75 and the D terminal 75, and the gate voltage is equal to the voltage of the power supply 19. Therefore, if the output buffer 73 is set to the high impedance state, the measurement can be performed by the same procedure as the embodiment of FIG.

FIG. 8 shows a schematic configuration of the eighth embodiment of the present invention. The semiconductor integrated circuit 80 includes an output circuit 81 and an internal logic circuit 82. Output circuit 8
1 includes a series circuit of a P-channel type MOS transistor 83 and an N-channel type MOS transistor 84. The drain and gate of the P-channel MOS transistor 83 and the drain and gate of the N-channel MOS transistor 84 are commonly connected. The sources of the P-channel type MOS transistor 83 and the N-channel type MOS transistor 84 are connected to the Vcc terminal 85 which is the positive power source terminal and the GND terminal 86 which is the ground side power source terminal, respectively. The commonly connected gates and drains are connected to the output side of the internal logic circuit 82 and the output terminal 87, respectively.
The output state of the P-channel type MOS transistor 83 is set to HI.
If the logic level on the GH side, that is, the ON state can be set, the source / drain current Isd of the P-channel type MOS transistor 83 is output at the HIGH level by the ammeter 18 inserted between the output terminal 87 and the GND terminal 85. It can be measured as an electric current. As the gate voltage, a voltage equal to the voltage of the power supply 19 is given from the internal logic circuit 82. The source / drain voltage of the P-channel MOS transistor 83 is equal to the voltage applied to the output terminal 87 when measuring the HIGH level output current. Therefore, the voltage applied to the output terminal 87 is the P-channel type MOS.
If the relationship between the power supply voltage and the input current is measured at least twice within a range large enough to allow a saturation current to flow between the source and drain of the transistor 83,
The threshold voltage Vth and the gain constant β can be obtained by the method described later.

FIG. 9 shows a method for obtaining the threshold voltage Vth and the gain constant β from the measurements in the above-described first to eighth embodiments. However, the condition is that measurement is performed under the following three conditions. The voltage applied to the measurement terminal is the power supply voltage.
Always equal to Vcc. The initial value of the power supply voltage Vcc is preset to a value expected to satisfy the above-mentioned first equation.
Until the measurement is completed, even if the power supply voltage Vcc is changed, the range where the first expression is satisfied is not exceeded.

The first embodiment will be described below.
Starting from step a1, the parameter i is initialized to 0 in step a2. At step a3, an initial value is set for the power supply voltage Vcc. In step a4, the same voltage value as the power supply voltage Vcc is applied to the input terminal 17 which is a measuring terminal, and the value is set to Vin (i). In step a5, the pull-down current is measured and the value is set to Iin (i). At step a6, it is judged whether or not the measurement has been completed, for example, two measurements have been completed. If it is determined that the power supply voltage Vcc has not ended, the process proceeds to step a7, and the value of the power supply voltage Vcc is set to a value that is changed by ΔV. In step a8, the parameter i is incremented by 1, and the process returns to step a4.

When it is determined that the measurement is completed in step a6, the process proceeds to step a9. At step a9, Vin
(I) and √Iin (i) are plotted as a graph and approximated to a straight line by the method of least squares. Next, step a10
Then, when the intersection of the straight line and the X axis is obtained, the voltage indicated by the intersection becomes the threshold voltage Vth. In step a11, the slope of the straight line is obtained, and the gain constant β is obtained as its value. The process ends at step a12.

In the second to eighth embodiments, the input terminal 57, the input / output terminals 27 and 67, and the output terminal 37,
The threshold voltage Vth and the gain constant β can be obtained by plotting the measured values with 47, 77, and 87 as measuring terminals.

10 and 11 show examples of measurement results corresponding to the first and fifth embodiments, respectively.
In FIG. 11, the sign of the measured voltage and the current is inverted and displayed as a positive value, so that the threshold voltage Vth to be obtained is calculated.
Must have a negative sign.

In each of the embodiments, the terminals connected to the outside of the package of the semiconductor integrated circuit are used as the measurement terminals, but when testing in the state of a wafer or a chip, the probe needle is used as in the conventional monitor chip. It can be used for measurement if it is connected to a pad or the like that can be electrically connected.

[0029]

As described above, according to the present invention, a sufficient voltage is applied between the source and drain of a MOS transistor to bring it into a saturated state. Therefore, the power supply voltage is changed to change the source-drain current Isd. By directly measuring
The characteristics of the semiconductor integrated circuit can be easily measured without separately forming a monitor chip. Further, since there are many semiconductor integrated circuits including MOS transistors capable of directly measuring the source / drain current, they can be applied to a wide range of semiconductor integrated circuits. For example, the source / drain current Isd may be measured at a measuring terminal such as an input terminal even when the consumption current is large due to a defective product or the like, and thus the present invention can be applied in many cases.

Further, according to the present invention, since the MOS transistor is connected so as to pull up or pull down the input terminal or the output terminal, the current flowing through the input terminal or the output terminal is measured to obtain the source / drain. The current Isd can be easily measured.

Further, according to the present invention, since the source / drain current Isd to the output buffer flows through the output terminal, it can be easily measured.

Further, according to the present invention, since the source / drain current Isd is measured by changing the gate voltage of the MOS transistor according to the power supply voltage, it is possible to easily measure the characteristic of at least one of the threshold voltage and the gain constant. You can

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of a first embodiment of the present invention.

FIG. 2 is a block diagram showing a schematic configuration of a second embodiment of the present invention.

FIG. 3 is a block diagram showing a schematic configuration of a third embodiment of the present invention.

FIG. 4 is a block diagram showing a schematic configuration of a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a schematic configuration of a fifth embodiment of the present invention.

FIG. 6 is a block diagram showing a schematic configuration of a sixth embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a seventh embodiment of the present invention.

FIG. 8 is a block diagram showing a schematic configuration of an eighth embodiment of the present invention.

FIG. 9 is a flowchart showing a measuring method according to the first embodiment of the present invention.

FIG. 10 is a graph showing an example of measurement results according to the first embodiment of the present invention.

FIG. 11 is a graph showing an example of measurement results according to the fifth embodiment of the present invention.

FIG. 12 is a block diagram showing an outline of a characteristic measuring method using a conventional monitor chip.

[Explanation of symbols]

10, 20, 30, 40, 50, 60, 70, 80 Semiconductor integrated circuit 11, 51 Input circuit 12, 22, 32, 42, 52, 62, 72, 82 Internal logic circuit 14, 24, 34, 44 N-channel Type MOS transistors 15, 25, 35, 45, 55, 65, 75, 85 V
cc terminal 16, 26, 36, 46, 56, 66, 76, 86 G
ND terminal 17,57 Input terminal 18 Ammeter 19 Power supply 27,67 Input / output terminal 37,47,77,87 Output terminal 54,64,74,83 P channel type MOS transistor

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 29/78 H01L 29/78 301T

Claims (4)

[Claims] 1. A measurement method for evaluating a semiconductor integrated circuit including a MOS transistor capable of directly measuring a source / drain current Isd, which is a voltage sufficient to bring a saturated state between a source and a drain of the MOS transistor. Is applied, the source / drain current Isd is measured under a plurality of power supply voltage conditions, and the characteristic of the MOS transistor is calculated based on the measurement result. 2. The MOS transistor is connected to pull up or pull down an input terminal or an output terminal, and the source / drain current Isd is a current flowing through the input terminal or the output terminal to which the MOS transistor is connected. The method for measuring a semiconductor integrated circuit according to claim 1, wherein: 3. The MOS transistor is used as an output buffer whose source or drain is connected to an output terminal, and as the source / drain current Isd, a current flowing to the output terminal to which the MOS transistor is connected is measured. The method for measuring a semiconductor integrated circuit according to claim 1, wherein: 4. The method for measuring a semiconductor integrated circuit according to claim 1, wherein the characteristic of the MOS transistor is at least one of a threshold voltage and a gain constant.