JPS6138576A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To measure the noise margin of an input buffer stably in a short time by providing a detecting circuit, which detects the output state of an input circuit, and a selecting circuit which selects the output of the detecting circuit and the output of an internal logic circuit. CONSTITUTION:An input terminal 1d for test is provided besides input terminals 1a-1c and output terminals 2a-2c. The output of an input buffer 11d is connected to the input of an inverter 5a, and the output of the inverter 5a is inputted to the input of an inverter 5b and one inputs of two-input AND gates 4a- 4e, and the output of the inverter 5b is inputted to two-input AND gates 3a- 3f. Though the signal transmitted to the internal logic circuit is in the low level when the input of the test terminal 1d is set to the low level, the signal level transmitted to the internal logic can be set freely at the input buffer test time if a circuit is added or changed, and thus, the noise margin is tested stably.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a logic circuit made of a semiconductor integrated circuit, and particularly to the configuration of a cover circuit.

(Description of Prior Art) Conventionally, when testing the noise margin of an input buffer in a semiconductor integrated circuit, especially a logic circuit, using an LSI tester, etc., it has been necessary to determine whether or not to perform a noise margin test according to the threshold level of the manually operated buffer. The noise margin is tested by applying a signal having a voltage or current with an amplitude corresponding to the noise margin to the manual buffer and operating the logic circuit. Therefore,
A noise margin test is almost the same as a functional test of the logic circuit, and as the function of the logic circuit becomes more complex, the test pattern for measuring the noise margin also tends to become more complex. There was a drawback that the test time increased.

Additionally, when measuring the noise margin of the input buffer using the method described above, the output changes, and in some cases, a large current flows through the output buffer, which generates noise on the power supply line or GND line of the logic circuit. The disadvantage was that the logic circuit malfunctioned and the noise machine of the input buffer could not be stably measured.

(Object of the Invention) Therefore, an object of the present invention is to provide a logic circuit having a circuit that can stably and quickly measure the noise margin of a manual buffer.

(Explanation of Examples) An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an example of a logic circuit manufactured as a conventional semiconductor integrated circuit. In the figure, 1a, 1b+IC are input terminals 2a, 2b, and 2C are output terminals, 118 to 11C are input buffer circuits, and 12a to 12C are output buffer circuits. Reference numeral 20 denotes an internal logic circuit, and since the content of the internal logic circuit is not discussed in the present invention, the description thereof will be omitted.

FIG. 2 is a circuit diagram of an example in which the present invention is applied to the logic circuit of FIG. 1. Figure 2 shows input terminals 13 to 1c, 2
In addition to the output terminals a to 2C, a test input terminal 1d is newly added.

Connect the output of the input buffer lid to the input of the inverter 5a, and connect the output of 5a to the input of the inverter 5b and the two-man power AND.
The input signal is input to one of gates 4a to 4e, and the output of gate 5b is input to two-man power AND gates 3a to 3f. Reference numeral 20 denotes an internal logic circuit, which is omitted as in FIG. The outputs of the input buffers lla to llc are input to the other inputs of the two-man power AND game) 3a to 3c+ and 4a to 4C, respectively. The outputs of 3a to 3C are input to 20 internal logic circuits, and the outputs of 4a to 4C are each input to a 3-man OR gate 6.
The output of the OR gate 6 is connected to the AND gate 4e, and the output of the OR gate 6 is input to the AND gate 7.
The output of is connected to an AND gate 4d, the outputs of 3d and 4d are input to a two-man OR gate 8a, and the outputs of 3e and 4e are input to a two-man OR gate 8b. The remaining inputs of 3d to 3f are connected to the output of the internal logic circuit 20.

Now, if the input of input terminal 1d is set to "1", AND
Since gates 38 to 3f are fighting, input terminals 1a to IC
The input signal is transmitted as is to the internal logic circuit. Furthermore, since the AND gates 3d to 3f are also open, the outputs of the internal logic circuits are output to the output terminals 2a to 2C, and have exactly the same function as the circuit shown in FIG. When the input of the input terminal 1d is set to O", the AND gates 3a to 3f are closed,
AND gates 4a to 4e open. Therefore, "0" is input to the internal logic circuit instead of the signals input to the input terminals 1a to IC. Further, the input of the output buffer 12C is also fixed at "O", and the output of the output terminal 2C remains at "0".

Suppose now that a signal at a level of 00° is applied to the input terminals 1a to IC in accordance with the noise margin inherent to each person's cover 7a. If all the outputs of the input buffers are 0, the output of the 0 gate 6 will be 0, and 0 will be output to the output terminal 2b.On the other hand, if any one of the outputs of the input buffers lla to 11C is If there is an output other than "O", information "1" is output to the output terminal 2b. That is, 1.1a
The "0" level noise margin test of the input buffer 7 of ~11C can be performed by simply checking that the output of the output terminal 2b is "0".

Also, when testing the noise margin of input buffers 1a to 11C, input terminals 1a to 1c
Apply the signal of °′1″1″ to be tested to 11a
If the outputs of ~11C are all 1°, the output of the AND gate 7 becomes 1'', and 1'' is output to the output terminal 2a. If any of the outputs from 113 to 11C is “0”
”, then “O” should be output to the output terminal 2a.

As mentioned above, in order to test the LOW level noise margin of input buffers 7alla to 11C, input terminal 1
It is sufficient to apply a LOW level voltage or current according to the threshold voltage (current) specific to each input buffer to the ICs a to IC, and test whether "0" is output to the output terminal 2b. , also) (similarly on the i g h level side) apply a signal of 1 i g h level to the input,
It is sufficient to test whether 1" is output to the output terminal 2a. As a result, in order to perform the noise margin test of the input buffers lla to 11C, the input buffers 13 to I
It is only necessary to apply one high and one low level signal to the input terminal of C at least once each, and the test time can be extremely shortened.

Furthermore, in the example shown in FIG. 2, if the input to the test terminal 1d is set to LOW level, the signal transmitted to the internal logic circuit will be LOW.
However, by adding or changing circuits, it is possible to freely set the signal level transmitted to the internal logic circuit when testing the input buffer, making it possible to test the noise margin more stably. You can also make it possible.

Furthermore, the AND gate 3f added between the input of the output buffer 12c and the internal logic circuit in the circuit diagram of FIG.
This gate is used to prevent the noise margin test from becoming unstable due to changes in the output of the circuit due to noise, etc., but if this is not necessary, there is no need to add such a gate.

Further, it is also possible to add or change a circuit so that the test can be performed in a more stable state, and for example, it is possible to set the output to be high impedance during a noise margin test.

In the example in Figure 2, the number of input terminals is 4 including the test terminal, and 3 output terminals, but when the number of input and output terminals increases in a larger logic circuit, it is especially difficult to perform input noise margin tests. It is also possible to apply the present invention only to the input terminals and leave the other input terminals as they are, or to divide the input terminals and output terminals into several groups and apply the method shown in Figure 2 for each group. It is also possible to apply a circuit like this and use a common control terminal.

As described above, by applying the present invention, it is possible to realize an integrated circuit logic circuit that can stably measure the noise margin of an input buffer in a short time.

[Brief explanation of the drawing]

FIG. 1 is a conventional circuit diagram, and FIG. 2 is a circuit diagram of an embodiment of the present invention. 1a+1b, 1c+1d...input terminal, 2a, 2b, 2c...output terminal. 11 a, 1 l b, 11 c, 11
d...Input buffer circuit, 12a, 12b,
12c...Output buffer circuit H3a + 3
b g 3 C+ 3 d + 3 e+ 3 f H
4a, 4b, 4c, 4d, 4
e - 2-man powered AND gate, 5a, 5b... Inverter, 6... 3-man powered OR gate, 7...
...3-man-powered AND gate, 8a8b...2-man-powered OR gate, 20...M Internal logic circuit other than output buffer\'9/ Hand 1 Figure! $2nd

Claims (1)

[Claims] In a logic circuit including an input circuit, an internal logic circuit, and an output circuit, a detection circuit detects an output state of the input circuit, and a selection circuit selects and outputs an output of the detection circuit and an output of the internal logic circuit. A semiconductor integrated circuit comprising: