JPS6385379A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To dispense with an external testing circuit and a control signal observing terminal and to test the transition time of a tri-state output buffer easily, accurately, stably and rapidly, by mounting a testing control circuit in an integrated circuit. CONSTITUTION:At the time of a usual operation mode, a mode control signal is 1 and a tri-state output buffer 12 is controlled to an output enable state and an output disable state corresponding to 0 and 1 of a buffer control signal C. At the time of a test mode, the mode control signal becomes 0 and the output of an AND circuit 17 becomes 0 and, therefore, the output buffer 12 always becomes the output enable state. Since the output of a NAND circuit 14 becomes 1 and the control signal C passes through an OR circuit 15 and the inverted signal of the control signal C is inputted to the output buffer 12 through the NAND circuit 16, the inverted logic of the buffer control signal C becomes observable at a tri-state output terminal 11 and a transition time can be tested.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to semiconductor integrated circuits, and particularly relates to test control circuits for tri-state output buffers. Diagnosis is an important issue when manufacturing custom LSIs such as standard cell semiconductor integrated circuits), especially testing the tristate transition time (output enable time, output disable time) of tristate output buffers. Ease of use, accuracy, stability, and continuous speed are required.

Conventionally, in order to test the tristate transition time, a tristate output terminal 32 connected to the output side of a tristate output buffer 31 of KLSI is used as shown in FIG.
resistor R,, R, capacitor C, switch circuit S□,
Connect external test circuits 33 such as S, , S, etc.
Alternatively, as shown in FIG. 4, an output buffer 42 for the control signal C of the tri-state output buffer 41 is provided inside the LSI, and an output terminal (control signal observation terminal 43)
was provided separately from the tri-state output terminal 44.

However, the method of externally connecting the test circuit shown in FIG. 3 is affected by the stray capacitance of test equipment and test equipment, and it is difficult to perform tests easily, accurately, stably, and quickly. Further, by providing the control signal observation terminals 43 as shown in FIG. 4, it is possible to easily test the tristate transition time. Therefore, there is a problem in that it is difficult to employ it in a custom LSI having a large number of tri-state output terminals 44. Furthermore, the control signal observation terminal 43 is completely unnecessary during actual use of the custom LSI.j9. There is also a problem in terms of effective use of LSI terminals.

(Problems to be Solved by the Invention) As described above, when externally attaching a test circuit for a tri-state output buffer, accurate and stable testing is difficult, and the present invention provides a control signal observation terminal. This was done to solve the problem of increasing the number of terminals and lowering the efficiency of terminal usage), eliminating the need for external test circuits and control signal observation terminals, and providing tri-state output. It is an object of the present invention to provide a semiconductor integrated circuit that can easily, accurately, stably, and quickly test the tri-state transition time of a buffer.

[Structure of the Invention] (Means for Solving the Problems) The semiconductor integrated circuit of the present invention is controlled to an output enable state or an output disable state according to a control input,
a tri-state output buffer whose output is connected to a tri-state output terminal, and is controlled by a mode control signal;
In the normal operation mode, the test control circuit controls the integrated circuit internal output signal to the tri-state output buffer, controls the tri-state output buffer to an output enable state, and inputs a buffer control signal to the tri-state output buffer. It is characterized by

(Function) The test control circuit is built into the integrated circuit, and in the test mode, the buffer control signal is output to the tristate output terminal via the tristate output buffer.
Easy, accurate, stable testing of tri-state transition times
This can be done quickly.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows one of a group of output parallel circuits 10 provided in a custom LSI (Large Scale Integrated Circuit) of a dirt array type or standard cell type, and a tristate output terminal 11 on the output side thereof. The output buffer circuit 10 includes a tri-state output buffer 12
In the normal operation mode, the input signal from the previous stage (LSI internal output signal 0ut) is guided to the tristate output buffer 12, and the tristate output buffer 1
In the tri-state transition time test mode, the tri-state output buffer 7
2 to a mode control signal output enable state, and a test control circuit 13 for guiding a buffer control signal thereto.

The test control circuit 13 is configured, for example, as shown in the figure. That is, the LSI internal output signal is one input), and the mode control signal N/T (high level "'1" in normal operation mode N, low level "'0" in test mode T) is the other input. A two-man powered first NAND circuit 14 serves as an input, and a buffer control signal C is connected to one input,
A two-man OR circuit 15 whose other input is the mode control signal; It consists of a second NAND circuit 16 operated by two people which serves as an input, and an AND circuit 12 whose inputs are the buffer control signal C and mode control signal, respectively, and whose output is a control input of the tristate output buffer 12. .

Next, the operation of the output buffer circuit 10 will be explained. In the normal operation mode, the so-do control signal is '1', and the AND circuit 17 passes the buffer control signal C;
The first NAND circuit 14 passes the LSI internal output signal and at the same time inverts the level, and the output of the or-dirt 15 is 'l', so the second NAND circuit 16 passes the output of the first NAND circuit 14. Therefore, the tri-state output buffer 12 is controlled to be in an output enable state or an output disable state according to IQIII, 1"1" of the output control signal C. Output 7a 12
When the output is enabled, the LSI internal output signal passes through the first NAND circuit 14, the second NAND circuit 16, and the tristate output buffer 12, and is output from the tristate output terminal 11.

On the other hand, in the test mode, the mode control signal is not 60'' and the output of the AND circuit 17 is O', so the tri-state output buffer 12 is always in the output enable state. The output of the NAND circuit 14 is '1', the buffer control signal C passes through the OR circuit 15, and the output of the OR circuit 15 passes through the second NAND circuit 16, so that the level is inverted. In this way, since the inverted signal of the buffer control signal 6 is input to the tristate output buffer 12, the inverted logic of the buffer control signal C can be observed at the tristate output terminal 11. In other words, the output enable time is the time from when the buffer control signal C reaches the ``θ'' level until the observation output signal reaches the 1'' level, and after the buffer control signal C reaches the ``1'' level. The time it takes for the observation output signal to reach the "O" level is the output disable time. In this case, the path difference between the buffer control signal C and the tristate output terminal 1 between the test mode and the normal operation mode, that is, If the output 8277 circuit is designed so that the difference in propagation speed of the buffer control signal C becomes clear, the tri-state transition time can be tested very accurately.

In addition, during the DC test of the custom LSI mentioned above, the mode control signal is set to 11", and the buffer control signal C is set to 'O".
By setting the tristate output buffer 12 to '1', it is possible to check whether the tristate output buffer 12 changes from the output enable state to the output disable state (the high impedance state of the tristate output terminal 11).

According to the test control circuit for the tri-state output buffer of the above embodiment, the circuit is built in the semiconductor integrated circuit, and 9) sets the test mode for the tri-state transition time of the tri-state output buffer using the mode control signal. The transition time can be tested by observing the pan-flash control signal output to the tri-state output terminal.

Therefore, if a test circuit is attached externally as in the past,
There is no need to provide a dedicated control signal observation terminal.
The above test can be performed easily, accurately, stably, and quickly, without increasing the number of terminals of the LSI or reducing the efficiency of terminal utilization.

Note that one dedicated mode control signal input terminal may be provided in order to input the mode control signal to the custom LSI and commonly provide it to the output buffer circuit group as described above, but if the custom LSI It is also possible to input a combination of inputs that are not used at all, and to discriminate this within the LSI to generate the mode control signal as described above.

Furthermore, although the above embodiment has shown an output 8177 circuit, the present invention is not limited to this, and as shown in FIG. An output 8277 circuit 10 may also be connected. In this case, the input buffer 20 has the output of the AND circuit 17 as a control input, and enters an input disable/enable state in response to the output enable/disable state of the tristate output buffer 12.

[Effects of the Invention] As described above, according to the semiconductor integrated circuit of the present invention, a tri-state output buffer test control circuit is built-in, and a tri-state output buffer control signal is output to the tri-state output terminal during testing. Therefore, tri-state transition time tests can be performed easily, accurately, stably, and quickly, and are extremely effective when applied to custom LSI@.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an output buffer circuit of a custom LSI according to one embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram showing an input/output 2777 circuit according to another embodiment, and FIG. The figure is a circuit diagram showing a tri-state output buffer and external test circuit in a conventional custom LSIK, and FIG. 4 is a circuit diagram showing a tri-state output buffer system and a control signal output buffer system in a conventional custom LSI. . 1 No.. Tri-state output terminal, 12.. Tri-state output buffer, 13.. Test control signal. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2

Claims (1)

[Claims] A tri-state output buffer that is controlled to an output enable state or an output disable state according to a control input and whose output is connected to a tri-state output terminal, and a tri-state output buffer that is controlled by a mode control signal and that outputs an integrated circuit internal output signal in the normal operating mode. The buffer control signal is input to the tri-state output buffer, and the buffer control signal is used as a control input of the tri-state output buffer, and in the tri-state transition time test mode, the tri-state output buffer is controlled to an output enable state, and the buffer control signal is input to the tri-state output buffer. 1. A semiconductor integrated circuit comprising: a test control circuit for inputting data to an output buffer.