JPS60196954A - Integrated circuit - Google Patents

Integrated circuit

Info

Publication number
JPS60196954A
JPS60196954A JP5301484A JP5301484A JPS60196954A JP S60196954 A JPS60196954 A JP S60196954A JP 5301484 A JP5301484 A JP 5301484A JP 5301484 A JP5301484 A JP 5301484A JP S60196954 A JPS60196954 A JP S60196954A
Authority
JP
Japan
Prior art keywords
logic
circuit
output
signal line
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5301484A
Other languages
Japanese (ja)
Inventor
Takao Hirose
廣瀬 隆雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5301484A priority Critical patent/JPS60196954A/en
Publication of JPS60196954A publication Critical patent/JPS60196954A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To offer an integrated circuit having an internal logic circuit and necessary times to test the electric condition of input and output terminals are made short. CONSTITUTION:When data from outside are applied to a coincidence detecting circuit through a signal line 21, the coincidence detecting signals when input data are all logic ''1'' or logic ''0''. This coincidence detecting signal enter to an output selecting circuit 13 in a test condition output circuit 12 through a signal line 24, and enters in an output selecting circuit 13 through an internal logic circuit 10 and a signal line 23. The output selecting circuit 13 alternatively selects signals coming through the inner logic circuit 10 and signals coming directly from the coincidence detecting circuit 11 through the signal line 24, and supplies the result to a signal line 26. The boundary value of an input terminal can be measured by a change of the logic condition of an output terminal of a package when logic ''0'' is applied from an input terminal to all signal lines 21, and then when one of the above is made of approach from a logic ''0'' condition to logic ''1'' condition.

Description

【発明の詳細な説明】 (技術分野) 本発明は集積回路に関し、特に論理回路を内部に有する
集積回路に関する。
TECHNICAL FIELD The present invention relates to integrated circuits, and more particularly to integrated circuits having logic circuits therein.

(従来技術) 従来、内部に論理回路を有する°集積回路の入出力端子
の電気的特性を調べるときは、半導体基板を収納してい
るパッケージの入力端子に論理回路の機能に合せたテス
ト信号を人力し、パッケージの出力端子にテスト結果會
示す信号を出力させていた。
(Prior art) Conventionally, when investigating the electrical characteristics of the input/output terminals of an integrated circuit that has an internal logic circuit, a test signal tailored to the function of the logic circuit is applied to the input terminal of the package that houses the semiconductor substrate. A signal indicating the test result was output to the output terminal of the package by hand.

最近のように集積回路が大規模化し、集積される素子数
が増大し、回路が複雑になってくると、出力端子に所望
の信号を出力させるために要するテスト信号も増大し、
入出力端子の電気的特性の試験に要する時間も非常に大
きくなるという欠点がありた。
As integrated circuits have recently become larger in scale, the number of integrated elements has increased, and circuits have become more complex, the test signals required to output a desired signal to the output terminal have also increased.
This method has the disadvantage that it takes a very long time to test the electrical characteristics of the input/output terminals.

(発明の目的) 本発明の目的は、上記欠点を除去し、内部論理回路を有
し、かつ入出力端子の電気的状態のテストに要する時間
が短くてすむ集積回路を提供することにある。
OBJECTS OF THE INVENTION It is an object of the present invention to provide an integrated circuit which eliminates the above-mentioned drawbacks, has an internal logic circuit, and requires less time to test the electrical states of input/output terminals.

(発明の構成) 本発明の集積回路は、半導体基板に形成された内部論理
回路と、該内部論理回路の出力端に人力端の一部が接続
して前記半導体基板に形成され残。
(Structure of the Invention) The integrated circuit of the present invention includes an internal logic circuit formed on a semiconductor substrate, and a part of a human power terminal connected to an output terminal of the internal logic circuit, which remains formed on the semiconductor substrate.

シの入力端が前記半導体基板を収納するパッケージのテ
スト信号入力端子に接続し出力端が前記バ、ケージの出
力端子に接続しテスト信号の入力により”θ″または1
″を出力するテスト状態出力回路とを含んで構成される
The input end of the cage is connected to the test signal input terminal of the package that houses the semiconductor substrate, and the output end is connected to the output terminal of the cage.
and a test status output circuit that outputs ``.

(実施例) 次に、本発明の実施例について図面を用いて説明する。(Example) Next, embodiments of the present invention will be described using the drawings.

第1図は本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.

この実施例は、半導体基板1に形成された内部論理回路
10と、同じく半導体基板1に形成され半導体基板1を
収納するパッケージの入力端子に入力端が信号線21で
接続し出力端が信号線22で内部論理回路10の入力端
に接続する一致検出回路11と、同じく半導体基板1に
形成され、入力端が内部論理回路10の出力端と一致検
出回路11の出力端とパッケージのテスト入力端子にそ
れぞれ信号線23,24.25で接続し出力端がパッケ
ージの出力端子に信号線26で接続しテスト信号の入力
により”0″または”1′′を出力するテスト状態出力
回路12とを含んで構成される。
In this embodiment, an internal logic circuit 10 formed on a semiconductor substrate 1 is connected to an input terminal of a package which is also formed on the semiconductor substrate 1 and houses the semiconductor substrate 1 through a signal line 21, and an output end is connected to a signal line 21. A coincidence detection circuit 11 connected to the input terminal of the internal logic circuit 10 at 22, and a coincidence detection circuit 11 also formed on the semiconductor substrate 1, whose input terminals are connected to the output terminal of the internal logic circuit 10, the output terminal of the coincidence detection circuit 11, and the test input terminal of the package. and a test status output circuit 12, which is connected to the terminals by signal lines 23, 24, and 25, respectively, and whose output end is connected to the output terminal of the package by a signal line 26, and which outputs "0" or "1" when a test signal is input. Consists of.

第2図は第1図に示すテスト状態出力回路の詳細プロ、
り図である。
Figure 2 shows the details of the test status output circuit shown in Figure 1.
This is a diagram.

テスト状態出力回路12内には内部論理回路10の出力
線数と同数の出力選択回路13を有し、各出力選択回路
は信号線23,24.25によって信号全入力し、信号
線26により出力をする。
The test state output circuit 12 has the same number of output selection circuits 13 as the number of output lines of the internal logic circuit 10, and each output selection circuit receives all signals through signal lines 23, 24, and 25, and outputs through signal line 26. do.

次に、この実施例の動作について説明する。Next, the operation of this embodiment will be explained.

信号線21を通して外部からデータが一致検出回路11
に入力されると、一致検出回路11は、入力データがす
べて論理″I″かあるいはすべて論理newのときに一
致検出信号を出力する。この一致検出信号は信号線24
乞通ってテスト状態出力回路12内の出力選択回路13
に人シ、また信号線22.内部論理回路10.信号a2
3 ’に通して出力選択回路13に入る。出力選択回路
13は内部論理回路10を通って信号線23から入って
くる信号と一致検出回路11から信号線24を通って直
接に入ってくる信号とを二者択一に選択し、その結果′
!!f−信号線26に出力する。
Data is transmitted from the outside through the signal line 21 to the coincidence detection circuit 11.
, the coincidence detection circuit 11 outputs a coincidence detection signal when all the input data are logic "I" or all logic new. This coincidence detection signal is sent to the signal line 24.
Output selection circuit 13 in test status output circuit 12
In addition, the signal line 22. Internal logic circuit 10. signal a2
3' and enters the output selection circuit 13. The output selection circuit 13 selectively selects between the signal coming from the signal line 23 via the internal logic circuit 10 and the signal coming directly from the coincidence detection circuit 11 via the signal line 24. ′
! ! It is output to the f-signal line 26.

今、パッケージの入力端子から信号線21のすべてに論
理no°を入力し、次にそのうちの1つを論理″0・”
から論理″′1″の状態に近づけると、パッケージの出
力端子の論理状態が変ることによシ、入力端子の境値(
”1″とOnとを区別して認識する境界の値)を測定で
きる0 また、入力端子のすべてに論理”1″を人力し、そのう
ちの一つを論理゛1″から論理“0″の状態に近づける
と出力端子の論理状態が変化することによシその入力端
子の境値が測定できることになる。
Now, input logic no° to all signal lines 21 from the input terminal of the package, and then input logic "0" to one of them.
When approaching the logic ``'1'' state, the logic state of the output terminal of the package changes, causing the boundary value of the input terminal (
In addition, by manually inputting logic "1" to all input terminals, one of them can be changed from logic "1" to logic "0". When the value approaches , the logic state of the output terminal changes and the boundary value of the input terminal can be measured.

端子特性のテストの方法には二連シする。その第1は、
入力端子にすべて論理”1″またはすべて論理′0゛を
入れたとき出力端子に論理11 l′が出力され、入力
端子に論理71″と@0″とを混ぜて入れたとき出力端
子に論理″θ″が出力されるようにする0その第2は、
入力端子にすべて論理”1”またはすべて論、埋”o’
を入れたとき出力端子にすべて論理″0″が出され、入
力端子に論理″11とθ″とを混ぜて入れると出力端子
に論理″1″が出力されるようにする0上記の二つの方
法のいずれを用いても良い0このようにして高レベル出
力電圧Vo H,低レベル出力電圧VoLの出力端子特
性全測定することができる。
There are two methods for testing terminal characteristics. The first is
When all logic ``1'' or all logic ``0'' is input to the input terminal, logic 11 l' is output to the output terminal, and when a mixture of logic 71'' and @0'' is input to the input terminal, logic is output to the output terminal. The second one is 0 which causes ``θ'' to be output.
All input terminals are logic “1” or all logic is buried “o”
If you input logic ``11'' and θ'' to the input terminal, logic ``1'' will be output to the output terminal. In this manner, all output terminal characteristics of the high level output voltage VoH and the low level output voltage VoL can be measured.

(発明の効果) 以上詳細に説明したように、本発明は、少ないテストパ
ターンで入力端子と出力端子の電気的特性を測定するこ
とができ、従って入出力端子のテストに要する時間が短
くてすむ集積回路を得ることができるという効果紮有す
る。
(Effects of the Invention) As explained in detail above, the present invention can measure the electrical characteristics of input terminals and output terminals with a small number of test patterns, and therefore the time required for testing input/output terminals can be shortened. This has the advantage that an integrated circuit can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例のプロ、り図、第2図は第1
図に示すテスト状態出力回路の詳細ブロック図である。 1・・・・・・半導体基板、10・・・・・・内部論理
回路、11・・・・・・一致検出回路、12・・・・・
・テスト状態出力回路、13・・・・・・選択出力回線
、21〜26・・・・・・信号線Q
Figure 1 is a professional diagram of one embodiment of the present invention, and Figure 2 is a diagram of the first embodiment of the present invention.
FIG. 3 is a detailed block diagram of the test status output circuit shown in the figure. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 10... Internal logic circuit, 11... Coincidence detection circuit, 12...
・Test status output circuit, 13...Selection output line, 21-26...Signal line Q

Claims (1)

【特許請求の範囲】[Claims] 半導体基板に形成された内部論理回路と、該内部論理回
路の出力端に入力端の一部が接続して前記半導体基板に
形成され残シの入力端が前記半導体基板を収納するパッ
ケージのテスト信号入力端子に接続し出力端が前記パッ
ケージの出力端子に接続しテスト信号の人力によ、a”
o″またはl+1″を出力するテスト状態出力回路とを
含む仁とを特徴とする集積回路。
A test signal of an internal logic circuit formed on a semiconductor substrate, and a package formed on the semiconductor substrate with a part of the input terminal connected to the output terminal of the internal logic circuit, and the remaining input terminal housing the semiconductor substrate. The input terminal is connected to the output terminal of the package, and the test signal is input manually.
and a test status output circuit that outputs o'' or l+1''.
JP5301484A 1984-03-19 1984-03-19 Integrated circuit Pending JPS60196954A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5301484A JPS60196954A (en) 1984-03-19 1984-03-19 Integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5301484A JPS60196954A (en) 1984-03-19 1984-03-19 Integrated circuit

Publications (1)

Publication Number Publication Date
JPS60196954A true JPS60196954A (en) 1985-10-05

Family

ID=12931044

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5301484A Pending JPS60196954A (en) 1984-03-19 1984-03-19 Integrated circuit

Country Status (1)

Country Link
JP (1) JPS60196954A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746559A (en) * 1985-11-18 1988-05-24 Fuji Photo Film Co., Ltd. Magnetic recording medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4746559A (en) * 1985-11-18 1988-05-24 Fuji Photo Film Co., Ltd. Magnetic recording medium

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