JPS6230971A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS6230971A JPS6230971A JP60169491A JP16949185A JPS6230971A JP S6230971 A JPS6230971 A JP S6230971A JP 60169491 A JP60169491 A JP 60169491A JP 16949185 A JP16949185 A JP 16949185A JP S6230971 A JPS6230971 A JP S6230971A
- Authority
- JP
- Japan
- Prior art keywords
- input
- external terminal
- output
- semiconductor integrated
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業−にの利用分野〕
本発明は半導体集積回路装置に関し、特に半導体集積回
路装置の外部との入出力回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an input/output circuit for connecting the semiconductor integrated circuit device to the outside.
一′４′導体基板十に、Ｉ−ランジスタ、抵抗等を形成
し名々を導体で配線し所望の機能を実現する半導体集積
回路装置は、製造技ｉトｉの進歩に従い１個のチップ上
に数多くの機能を集積化することが可能となっており、
ワンチップＣｐＬＴあるいはゲー ｌ−アレーのように
大規模で多くの入出力ピンを持つ半導体集積回路装置が
増大している。Semiconductor integrated circuit devices, in which I-transistors, resistors, etc. are formed on a 1'4' conductor substrate and the components are wired with conductors to achieve a desired function, have been fabricated on a single chip with advances in manufacturing technology. It is now possible to integrate numerous functions into
Semiconductor integrated circuit devices, such as one-chip CpLTs or game arrays, are increasing in size and having many input/output pins.
大規模な半導体集積回路ｙ・置の試験は一般にＬＳＩテ
スタと呼ばｈる試験装置を用いて行い一機能の確認およ
びカタログ記載の入力しきい値電圧。Testing of large-scale semiconductor integrated circuits is generally carried out using a test device called an LSI tester to confirm the functionality and meet the input threshold voltage specified in the catalog.
出力電圧、遅延時間等の試験を行う。Perform tests on output voltage, delay time, etc.
この種の半導体集積回路装置は一般に第２図に示すよう
に外部端子２．〜２ｎ ＋ ５１〜５ ｎ、入力増幅器
１、〜１１個回路３と、出力増幅器４、〜４ｎ、からな
り、各入力増幅器１．−１．ｎ、の入出力端には入出力
６！１．測用の端子が存在１−ないため、面接入力増幅
器の入出力を外部から観測できないために、従来機能を
確認するためのテストバタン、あるいは入力しきい値電
圧を測定するために用意したテストバタンを所定の電圧
で半導体集積回路装置に与え、その出力を出力期待値と
比較することでお・こなっていた。This type of semiconductor integrated circuit device generally has an external terminal 2.0 as shown in FIG. ~2n + 51~5n, consisting of an input amplifier 1, ~11 circuits 3, and an output amplifier 4, ~4n, each input amplifier 1. -1. The input and output terminals of n and 6!1. Since there is no terminal for measurement, the input and output of the interview input amplifier cannot be observed from the outside. This was done by applying a predetermined voltage to the semiconductor integrated circuit device and comparing the output with the expected output value.
しかしながら、従来の試験方法ではテストバタンを用い
入力しきい値電圧を試験しようとすると、内部回路によ
っては入力信号の競合によって正確な値が測定できない
ことがある。また内部動作にマージンがない場合や、電
源雑音に弱い回路である場合＼入力しきい値電圧は充分
な特性を持っているにもかかわらず、測定結果が悪化す
る等の欠点があった。However, when attempting to test the input threshold voltage using a test button in the conventional test method, an accurate value may not be measured due to competition of input signals depending on the internal circuit. Furthermore, if there is no margin for internal operation or if the circuit is sensitive to power supply noise, the measurement result may deteriorate even though the input threshold voltage has sufficient characteristics.
本発明は入力増幅器の入出力を直接観測できる半導体集
積回路装置を提供するものである。The present invention provides a semiconductor integrated circuit device in which input and output of an input amplifier can be directly observed.
Ｃ問題点を解決するための手段〕
本発明は入力側に外部端子に、捷だ出力側を内部回路に
それぞれ接続した複数個の入力増幅器を並設した半導体
集積回路装置において、一つの入力増幅器の出力側を他
の一つの入力増幅器の入力側外部端子に結線し、その配
線に開閉スイッチを設けたことを特徴とする半導体集積
回路装置であるＯ
〔実施例〕
次に本発明の一実施例について図面を参照して説明する
。第１図は本発明の一実施例である。第１図において、
第１の入力増幅器１□の入力は第１の外部端イ２．に接
続さ１土、出力は内部回路３に接続されるとともに外部
から制御可能な開閉スイッチ６１を介して第２の外部端
子２２に接続されている。Means for Solving Problem C] The present invention provides a semiconductor integrated circuit device in which a plurality of input amplifiers are arranged in parallel, each having its input side connected to an external terminal and its twisted output side connected to an internal circuit. O is a semiconductor integrated circuit device characterized in that the output side of the input amplifier is connected to the input side external terminal of another input amplifier, and an on/off switch is provided on the wiring. An example will be explained with reference to the drawings. FIG. 1 shows an embodiment of the present invention. In Figure 1,
The input of the first input amplifier 1□ is connected to the first external terminal A2. The output is connected to the internal circuit 3 and is also connected to the second external terminal 22 via an externally controllable open/close switch 61.
外部から制御可能なスイッチ６□を導通状態とすると、
第１の外部端子２、から信号を入力し、第２の外部端子
２２ヲ観測することで第１の入力増幅器１１０入力しき
い値電圧等の特性を容易かつｉｌＥ確に測定することが
できる。舶Ｓ構造の半導体集積回路装置の場合、゛入力
増幅器の入力インピーダンスは非常に高いから第２の入
力増幅器１２の影響は無視することができる。When the externally controllable switch 6□ is made conductive,
By inputting a signal from the first external terminal 2 and observing the second external terminal 22, characteristics such as the input threshold voltage of the first input amplifier 110 can be easily and accurately measured. In the case of the semiconductor integrated circuit device having the S-structure, the influence of the second input amplifier 12 can be ignored because the input impedance of the input amplifier is very high.
第２の入力増幅器１２０入力は第２の外部端子２□に接
続され、出方は内部回路３に接続されるとともに外部か
ら制御可能なスイッチ６、を介して第３の外部端子２３
に接続される。このように次々と入力増幅器１１〜１ｎ
を外部から制御可能なスイッチ６□〜６ｎを介してカス
ケードに接続する。The input of the second input amplifier 120 is connected to the second external terminal 2□, and the output is connected to the internal circuit 3 and connected to the third external terminal 23 via a switch 6 that can be controlled from the outside.
connected to. In this way, input amplifiers 11 to 1n are input one after another.
are connected in cascade through externally controllable switches 6□ to 6n.
第ｎの入力増幅器片の特性は外部から制御可能なスイッ
チ６ｎを導通状態にすることで第ｎ、の外部端子２ｎと
第？Ｌ＋１の外部端子２７Ｌ＋］を用いて測定できる・
半導体集積回路装置の規模が大きくなり外部端子に接続
される入力増幅器が増加した場合、外部から制御可能な
スイッチ６、〜６７＋、に直列に電流制限素子を含１せ
、外部から制御可能なスイッチを連動させ１個の外部端
子を制御端子とし２個の外部端子の増加で外部端子に接
続される入力増幅器すべてについて特性を容易かつ正確
に測定することができる。捷たこの場合スイッチを連動
させて動作させても良い。The characteristics of the n-th input amplifier piece can be determined by turning on the externally controllable switch 6n, thereby connecting the n-th external terminal 2n and the ?th? L+1 external terminal 27L+] When the scale of the semiconductor integrated circuit device increases and the number of input amplifiers connected to the external terminal increases, the current limiter is connected in series to the externally controllable switches 6, ~67+. By including one external terminal and interlocking an externally controllable switch, one external terminal is used as a control terminal, and with the addition of two external terminals, the characteristics of all input amplifiers connected to the external terminal can be easily and accurately measured. be able to. In this case, the switches may be operated in conjunction with each other.
以」二説明したように本発明は入力増幅器の出力を外部
から制御可能なスイッチを介して、他の入力増幅器に接
続されている外部端子に接続することで１人力増幅器の
特性を簡単にしかも内部回路の動作とは無関係に測定で
き、特に大規模で多くの入力ピンを持つ半導体集積回路
装置においても外部試験端子としてスイッチの制御のた
めの外部端子と内部観測用の外部端子の２端子を追加す
るだけで外部端子に接続される入力増幅器すべてについ
て特性を容易かつ正確に測定できる効果がある。As explained above, the present invention simplifies the characteristics of a single-power amplifier by connecting the output of an input amplifier to an external terminal connected to another input amplifier via an externally controllable switch. It can be measured independently of the operation of the internal circuit, and even in semiconductor integrated circuit devices that are large-scale and have many input pins, two terminals can be used as external test terminals: an external terminal for switch control and an external terminal for internal observation. By simply adding this, it is possible to easily and accurately measure the characteristics of all input amplifiers connected to external terminals.
第１図は本発明の一実施例を示す構成図、第２図は従来
の半導体集積回路装置を示す構成図であるＯFIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional semiconductor integrated circuit device.
Claims (1)
れぞれ接続した複数個の入力増幅器を並設した半導体集
積回路装置において、一つの入力増幅器の出力側を他の
一つの入力増幅器の入力側外部端子に結線し、その配線
に開閉スイッチを設けたことを特徴とする半導体集積回
路装置。(1) In a semiconductor integrated circuit device in which a plurality of input amplifiers are installed in parallel, the input side is connected to an external terminal, and the output side is connected to an internal circuit, the output side of one input amplifier is connected to the output side of another input amplifier. A semiconductor integrated circuit device, characterized in that it is connected to an input-side external terminal, and that the wiring is provided with an on/off switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169491A JPS6230971A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60169491A JPS6230971A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6230971A true JPS6230971A (en) | 1987-02-09 |
Family
ID=15887510
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60169491A Pending JPS6230971A (en) | 1985-07-31 | 1985-07-31 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6230971A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010082238A1 (en) * | 2009-01-16 | 2010-07-22 | パナソニック株式会社 | Semiconductor integrated circuit and electronic information device |
| WO2021124508A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
| WO2021125348A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
| WO2021124506A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
-
1985
- 1985-07-31 JP JP60169491A patent/JPS6230971A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2010082238A1 (en) * | 2009-01-16 | 2010-07-22 | パナソニック株式会社 | Semiconductor integrated circuit and electronic information device |
| WO2021124508A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
| WO2021125348A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
| WO2021124506A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
| WO2021125302A1 (en) * | 2019-12-19 | 2021-06-24 | ヤマハ発動機株式会社 | Vehicle |
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