JPS61149866A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To inspect the phase difference of an internal signal accurately with simple constitution by outputting a pulse signal corresponding to the time difference of variations between two logical signals in a semiconductor integrated circuit to the outside of the semiconductor integrated circuit. CONSTITUTION:An internal signal generating circuit 1 generates and outputs two internal signals A and B to a logical circuit 2. If the internal signals A and B have a phase difference, an exclusive OR circuit 3 generates and outputs a a phase difference signal C with pulse width corresponding to the phase difference to an output terminal 6 through an output control circuit 4 and an output buffer circuit 5. The pulse width of this phase difference pulse signal C is measured to know the phase difference between the internal signals A and B. At this time, paths of the internal signals A and B to the output terminal 6 become equal, so the pulse width of the phase difference pulse signal is set equal to the phase difference between the internal signals A and B.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit that includes a configuration that allows the phase difference between two internal signals to be easily and reliably tested.

2. Description of the Related Art In general, in a semiconductor integrated circuit, the phase difference between two different signals within the circuit often has a large effect on the operation of the circuit, and it becomes necessary to inspect it when testing the semiconductor integrated circuit. For this reason, in conventional semiconductor integrated circuits, each internal signal is output separately to the outside.
Problems to be Solved by the Invention In such conventional circuits, the two internal signals must be separately drawn out to the outside, so the output terminals for the two signals are There may be cases where the route to the destination is different. In this case 9
, due to differences in signal line wiring and logic circuits, etc.
The phase difference between the two signals used internally is different from the phase difference measured externally, making it difficult to know the exact phase difference. Furthermore, since the two signals are output separately to the outside, two output terminals are occupied at the same time.

The present invention has been made in view of these points, and an object of the present invention is to provide a semiconductor integrated circuit that can accurately test the phase difference of internal signals with a simple configuration.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention takes two logic signals inside a semiconductor integrated circuit as input, and generates a pulse signal corresponding to the time difference between changes in the two logic signals. , the pulse signal is output to the outside of the semiconductor integrated circuit.

Effect of the Invention With the above-described configuration, the present invention directly generates internally a signal having a pulse width corresponding to the difference in change time of two internal signals, and then outputs the signal to the outside by connecting two signal line paths. The difference between them becomes small, and the phase difference can be measured with high precision. Furthermore, since only one pulse signal is output, the terminals can be used effectively.

Embodiment FIG. 1 is a circuit diagram schematically showing a semiconductor integrated circuit in an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an internal signal generating circuit which generates two internal signals, HI and B, and outputs them to the logic circuit 2. Reference numeral 3 designates an exclusive OR circuit, ie, an XX-0R circuit, which inputs the internal signals A and B, and outputs a phase difference pulse signal C. Reference numeral 4 denotes an output control circuit, which controls whether the output E of the logic circuit 2 is output to the terminal 6 or the phase difference pulse signal C is output to the terminal 6. 5 is an output buffer circuit.

FIG. 2 shows a waveform diagram when the output control circuit 4 is controlling to output the phase difference pulse signal O to the output terminal 6 in the circuit shown in FIG. For example, when there is a phase difference of td between internal signals A and B as shown in FIG. 2, the output C of the EX-OR circuit 3 is The signal becomes "H" level, and a phase difference pulse signal C having a pulse width tw corresponding to the phase difference td is generated. This phase difference pulse signal C is sent to an output terminal 6 via an output control circuit 4 and an output buffer circuit 6.
is output to. Therefore, by measuring the pulse width of the phase difference pulse signal appearing at the output terminal, the internal signal A
and B can be known. In this case, the routes to the internal signal person and the output terminal 6 of B are equal,
KX-OR circuit 3. By appropriately selecting the circuit constants of the output control circuit 4 and the output buffer circuit 5, the output terminal 6
The pulse width of the phase difference pulse signal can be set to be equal to the phase difference between the internal signals and B. Further, since the internal signals M and B are not outputted, the configuration of the output control circuit is simplified, and the area required for wiring can be reduced.

In the above explanation, the phase difference pulse signal C is 1! :X-0
We have described the case where R circuit 3 generates 1i:
-N OR circuit -N A N D circuit
A similar effect can be obtained by using a circuit.

Figure 3 shows EX, which is the phase difference pulse signal generation circuit in Figure 1.
-This is an embodiment in which the OR circuit 3 is replaced with a launch circuit 7, and the configuration is the same as that of FIG. 1 except for the launch circuit.

FIG. 4 shows a waveform diagram when the output control circuit 4 is controlling the phase difference pulse signal C to be outputted to the output terminal 6 in the circuit shown in FIG. When the internal signal waveforms A and B are input to the latch circuit as shown in FIG. 4, the pulse width tw' corresponding to the phase difference td between the internal signal waveforms A and B is A phase difference pulse signal is generated, and a phase difference pulse signal as shown at D in FIG. 4 is outputted to the output terminal 6 via the output control circuit 4 and the output buffer 5. Therefore, by measuring the pulse width of the phase difference pulse signal appearing at the output terminal 6,
The phase difference between the internal signals and B can be known. In this case as well, by appropriately selecting the circuit constants of the latch circuit 7, output control circuit 4, and output buffer circuit 5, the pulse width of the phase difference pulse signal appearing at the output terminal 6 can be adjusted to match the phase difference between the internal signals A and B. They can be made equal and the phase difference can be known accurately. In the above description, the case where the latch circuit 7 in FIG. 3 is configured with a NoFt circuit has been described, but the same effect can be obtained even if the launch circuit is configured with a NAND circuit.

Effects of the Invention As described above, according to the present invention, it is possible to accurately determine the phase difference of internal signals with an extremely simple configuration without requiring a large wiring area, and for this measurement, only one output is required. It has the effect of occupying only the terminal, and is extremely useful in practice.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor integrated circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of main parts of the circuit of FIG. 1, and FIG. 3 is a circuit diagram of a semiconductor integrated circuit according to another embodiment of the present invention. 4 are waveform diagrams of essential parts of the circuit of FIG. 3. 1...Internal signal generation circuit, 2...Logic circuit, 3゜Complete...Phase difference pulse generation circuit, 4...
... Output control circuit, 6 ... Output vanofer circuit, 6 ... Output terminal. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure 2: □

Claims (1)

[Claims] a logic circuit that receives a first logic signal and a second logic signal as input and outputs a pulse signal corresponding to a time difference between a change in the first logic signal and a change in the second logic signal; A semiconductor integrated circuit that has means for outputting to the outside.