JPS588778B2 - Electric pulse extraction circuit - Google Patents

Description

[Detailed description of the invention] The present invention relates to an electrical pulse extraction circuit.

When controlling and adjusting electrical equipment, making various measurements, etc. using pulses, it is often necessary to remove the pulses from the source as necessary.

However, conventionally, no suitable extraction circuit has been known that can arbitrarily extract the required number of pulses generated periodically or non-periodically from a pulse generation source without impairing the pulse width.

The present invention aims to provide such an extraction circuit,
It is equipped with a control signal generation circuit that is excited by the input of a control pulse, and a gate circuit that outputs the input pulse applied to the input terminal to the output terminal, and the gate circuit is operated at a fixed timing by the control signal from the control signal generation circuit. At the same time, the control signal generation circuit and the gate circuit are reset by the output pulse from the gate circuit, so that a predetermined number of pulses can be extracted from the output terminal each time a control pulse is applied to the control signal generation circuit. It is characterized by the following structure.

Embodiments of the present invention will be described in detail below with reference to the drawings.

As shown in FIG. 1, the extraction circuit of the present invention includes a control signal generation circuit, an input signal check circuit, a gate circuit, and a reset circuit.

The control signal generation circuit includes a monostable multivibrator M1 that oscillates when a control pulse is input to a control signal terminal C, and a monostable multivibrator M1 that is excited by its output and continuously generates a control signal until it is reset by a reset signal from a reset circuit. The output terminal Q1 of this flip-flop circuit RS1 is connected to one input terminal A11 of an AND circuit AND1 in the input signal check circuit.

The above input signal check circuit checks the control signal output from the control signal generation circuit and the input pulse applied to the input terminal ■, and outputs a set signal when only the control signal is input. AND circuit AND1
, input terminal ■ and the other input terminal A of the AND circuit AND1
12, and a monostable multivibrator M2 connected to the output side of the AND circuit AND1.
The output side of 2 is connected to the input terminal S2 of the flip-flop circuit RS2 in the gate circuit.

Further, the gate circuit is the flip-flop circuit R.
S2 and an AND circuit AND2, this AND circuit A
The output terminal Q2 and the input terminal ■ of the flip-flop circuit RS2 are connected to the two input terminals A22 and A22 of the ND2, respectively, and the output side of the AND circuit AND2 is connected to the output terminal O. The flip-flop circuit RS2 operates in response to the set signal, and outputs the input pulse applied to the input terminal (2) to the output terminal O until it is reset by the set signal from the reset circuit.

Further, the reset circuit includes an OR circuit OR in which two input terminals are connected to the output terminal 0 and the reset terminal J;
NOT circuit NO connected sequentially to the output side of this OR circuit
T2 and a monostable multivibrator M3, and the output side of the monostable multivibrator M3 is connected to the flip-flop circuit R in the control signal generation circuit and gate circuit.
It is connected to the other input terminals R1 and R2 of SI and RS2, respectively, and the monostable multivibrator M3 is oscillated by the reset pulse input to the reset terminal J or the output pulse output from the gate circuit. The flip-flop circuits RSI and RS2 are reset by the reset signal outputted thereby.

Next, the operation of the extraction circuit having the above configuration will be explained.

To extract a pulse, first input a reset pulse from the outside to the reset terminal J, and output a reset signal by oscillating the monostable multivibrator M3 via the OR circuit OR and NOT circuit NOT2. Reset flip-flop circuits RS1 and RS2.

As a result, the outputs at the output terminals Q1 and Q2 of the two flip-flop circuits RSI and RS2 are both held at logic level "0".

Next, when a control pulse is input to the control terminal C, the monostable multivibrator M1 oscillates due to this control pulse, and its output is sent to the input terminal S of the flip-flop circuit RSI.
1, the flip-flop circuit RS1
is excited and the output at the output terminal Q1 becomes "1",
This is input as a control signal to the input terminal A11 of AND1 in the input signal checker circuit.

The output of the control signal from the flip-flop circuit RS1 continues until it is reset by a reset signal from the reset circuit.

Here, when the signal level at the input terminal ■ is "0", that is, when no pulse is input, the output of the NOT circuit NOT1 in the input signal checker circuit is 1.
'', and this is applied to the other input terminal A12 of the AND circuit AND1, so the output of the AND circuit AND1 becomes "1", the monostable multivibrator M2 oscillates, and the signal is applied to the input terminal S2 of the flip-flop circuit RS2 in the gate circuit. A set signal is output.

Therefore, this flip-flop circuit RS2 is excited, and one input terminal A2. A signal "1" is input to the terminal.

This state of flip-flop circuit RS2 persists until it is reset by a reset signal from the reset circuit.

In this state, when the signal level at the input terminal I becomes "1", that is, when a pulse is input, the AND circuit AND2
Since the inputs of the two input terminals A2, , A22 both become "1", the output also becomes "1", and this is taken out from the output terminal O.

Subsequently, when the input of the above pulse is completed and the signal level of the input terminal ■ becomes "0" again, the output of the AND circuit AND2 also becomes "0", and one pulse is thereby extracted to the output terminal O. It turns out.

Thus, the output change of the AND circuit AND2 is input to the OR circuit OR in the reset circuit, and the NOT circuit NO.
A reset signal is output by oscillation of the monostable multivibrator M3 via T2, and the flip-flop circuit RS in the control signal generation circuit and gate circuit is
I and RS2 are both reset.

By this reset, the input terminal A of the AND circuit AND2
The input to 21 becomes "0", and even if a pulse is subsequently input to input terminal (2), it is not extracted to output terminal O.

Thereafter, the above operation is repeated every time a control pulse is input to the control terminal C, and a pulse is extracted from the output terminal O.

Note that when the control signal from the control signal generation circuit is input to the AND circuit AND1 in the input signal checker circuit, if the signal level at the input terminal ■ is "1", the output of the NOT circuit NOT1 is "0". ”, the output of the AND circuit AND1 becomes “0”, so the monostable multivibrator M2 does not oscillate, and after the input of the pulse to the input terminal ■ is completed and the signal level becomes “0”,
It oscillates and a set signal is output.

The extraction circuit of the present invention can extract a pulse signal at any time as described above, and therefore can be effectively used for sampling pulses.

FIG. 2 shows an example of its application, where A is an extraction circuit of the present invention and G is a crystal oscillator as a pulse generation source.

In this way, when the pulse from the crystal oscillator G is input to the input terminal 1 of the extraction circuit A, and a pulse signal with an arbitrary variable period is input to the control terminal C as a control pulse, the one shown in Fig. 2 is a variable frequency pulse. Acts as an oscillator.

The stability of the pulse width of this pulse oscillator is determined only by the stability of the crystal oscillator and is not affected by any other factors, so it is significantly superior to the stability of conventional pulse oscillators. becomes.

In addition, conventionally, the operation checker of pulse width measuring instruments and time interval measuring instruments was performed indirectly by the tarotsuta pulse provided in each instrument, but the output of the extraction circuit of the present invention is directly connected to the above measuring instruments. By inputting the information, the actual operation can be confirmed, so adjustments, failures, etc. can be easily and quickly performed.

As described in detail above, according to the present invention, it is possible to reliably extract pulses generated periodically or aperiodically from a pulse generation source without damaging the pulse width.
Moreover, by operating the reset circuit based on the extracted number of pulses, any number of pulses can be freely extracted.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a blotter showing an embodiment of an extraction circuit according to the present invention, and FIG. 2 is an explanatory diagram of an example of its application. C...Control signal terminal, ■...Input terminal, 0...Output terminal, J...Reset signal terminal.

Claims (1)

[Claims] 1 A control signal generation circuit that is excited by a control pulse input to a control signal terminal and continuously outputs a control signal until it is reset; an input signal check circuit that checks input pulses and outputs a set signal when only a control signal is input; excited by the set signal output from the input signal check circuit; a gate circuit that outputs the input pulse from the terminal to the output terminal; excited by the output pulse output from the gate circuit or the reset pulse input to the reset signal terminal, and outputs a reset signal for the signal generation circuit and the gate circuit; An electric pulse extraction circuit characterized by: a reset circuit and an electric pulse extraction circuit.