JPS61228702A - Crystal oscillation circuit - Google Patents

Abstract

PURPOSE:To conduct a logic test with high reliability by providing an analog switch in parallel with a DC block capacitor so as to make the analog switch conductive at test thereby supplying a stable signal to a clock circuit. CONSTITUTION:Since a level at a T terminal 20 is at H normally and a level of a terminal C of the analog switch 22 via an inverter 23 at L, the terminals A, B of the analog switch 22 are opened and the circuit acts like a conventional oscillation circuit. In bringing the level of the terminal 20 to L at the logic test by an external operation, the level of the terminal C of the analog switch 22 goes to H via the inverter 23, the analog switch 22 is conducted and a DC blocking resistor 7 and a bias resistor 8 are short-circuited. As a result, an Xin terminal 2 and the input terminal of an inverter 4 are connected directly. In inputting a test clock signal from an Xin terminal 2 in this state, the signal is sent directly to the input terminal of the inverter 4 via the analog switch 22 and a signal being the inversion of the test clock signal is inputted to a clock circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a crystal oscillation circuit built into an electronic watch having a DC prevention capacitor, and particularly to an improvement of the crystal oscillation circuit in consideration of testing of the electronic watch. Regarding improvements.

[Conventional technology]

Conventionally, a crystal oscillation circuit for an electronic timepiece as shown in FIG. 2 has been proposed. (For example, JP-A-59-32206) No. 2
In the figure, 1 is the output crystal connection terminal (X out
2 is an input crystal connection terminal (hereinafter abbreviated as Xin terminal), and 3 is a crystal resonator connected to the Xout terminal 1 and the Xin terminal 2. Note that the X out terminal 1 and the Xin terminal 2 are configured on an IC chip, and are connected to the crystal resonator 6 using means such as wire bonding.

4 is an inverter made up of CMO8, and a reference signal P. is outputting. 5 is a DC feedback resistor connected to the input terminal and output terminal of the inverter 4, and 6 is an oscillation stabilizing resistor connected to the output terminal of the inverter 4 and the Xout terminal 1. 7 is the input terminal of inverter 4 and Xi
A DC blocking capacitor 8 is connected between the n terminal 2 and the Xin terminal 2, and a bias resistor 8 is connected between the input terminal of the inverter 40 and the Xin terminal 2 to stabilize the DC level of the Xin terminal 2. 9 is an oscillation capacitor inserted between the old XO terminal 1 and the ground, 10 is an oscillation capacitor inserted between the Xin terminal 2 and the ground, and each of the above elements constitutes a crystal oscillation circuit. There is.

11 is a reference signal P from the crystal oscillation circuit.

This is a watch circuit that operates on the basis of , but the details thereof are not related to the gist of the present invention, so a description thereof will be omitted. Note that the portions surrounded by broken lines in FIG. 2 indicate elements configured within the IC chip.

Next, the operation of the crystal oscillation circuit having the above configuration will be explained.

When a signal such as noise is input to the input terminal of the inverter 40, a signal having a level opposite to that of the input signal is output from the output terminal of the inverter 4. As a result, a potential difference is created in the crystal oscillator 3, and the crystal oscillation circuit starts oscillating at the unique frequency of the crystal oscillator 3, and the inverter 4 generates a reference signal P. is output, and the reference signal P. Therefore, the timepiece circuit 11 is driven.

[Problems to be Solved by the Invention] Normally, in a watch IC, it is necessary to perform a logic test to check the operation of the circuit after completion of manufacturing and after mounting on a circuit board. Conventionally, when performing a logic test on the oscillation circuit of an electronic watch as shown in FIG. 2, a test clock signal was input from the Xin terminal 2 or the Xout terminal 1. However, the Xin
When inputting the test clock signal from terminal 2,
Since the bias resistor 8 has a high resistance and there is the DC blocking capacitor 7, the DC level is not transmitted to the input terminal of the inverter 40, making the operation of the inverter 4 unstable. Furthermore, when a test clock signal is input from the X out terminal 1, since the stabilizing resistor 6 is present, the resistance value of the stabilizing resistor 6 and the output resistance value of the inverter 4 may be compromised. The level of the signal input to the clock circuit 11 becomes unstable. Therefore, the Xin terminal 2
Or, no matter which one of the X out terminals 1 inputs the test clock signal, a stable signal is input to the clock circuit 11, which lowers the reliability of the logic test.

The purpose of the present invention is to solve the above-mentioned conventional problems,
The purpose of the present invention is to provide a crystal oscillation circuit for increasing the reliability of logic tests.

[Means for solving problems]

In order to achieve the above object, the present invention has the following configuration. That is, the crystal oscillation circuit according to the present invention includes an I
In a crystal oscillation circuit having a C chip, an inverter provided in the IC chip, and a capacitor connected between the input of the inverter and the crystal connection terminal, a switch means connected in parallel to the capacitor and the switch means A switch control means for controlling the IC chip is provided, and the switch control means is controlled by an external terminal provided on the IC chip.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of an electronic timepiece using a crystal oscillation circuit showing an embodiment of the present invention. In FIG. 1, the same elements as those in FIG. 2 are given the same numbers and their explanations will be omitted. To explain the different parts in Fig. 1 from Fig. 2,
20 is a test mode designation terminal (T terminal), which is normally set to H by a pull-up resistor 21. 22 is an analog switch, whose A terminal and B terminal are respectively connected to both ends of the DC blocking capacitor 7;
A T terminal 20 is connected to a C terminal of an analog switch 22 via an inverter 26. When the C terminal is H, the analog switch 22 conducts between the A terminal and the B terminal, and the L
This is a switch that is opened when

The operation of the crystal oscillation circuit of the electronic timepiece with the above configuration will be explained.

Since the T terminal 20 is normally at I4, the C terminal of the analog switch 22 via the inverter 26 is at L.

Therefore, since the analog switch 22 is in an open state between the A terminal and the B terminal, the circuit configuration is electrically the same as that in FIG. 2. Therefore, the crystal oscillation circuit of FIG. 1 according to the present invention operates in the same way as the conventional crystal oscillation circuit shown in FIG. 2 in the normal state.

Next, the operation when performing a logic test for checking the operation of a circuit, which is a feature of the present invention, will be explained.

During a logic test, the T terminal 20 is set to L[ by external operation.
do. As a result, the C terminal of the analog switch 22 becomes H via the inverter 23, the analog switch 22 becomes conductive, and the DC blocking resistor 7 and bias resistor 8 are short-circuited.

As a result, the Xin terminal 2 and the inverter 40 input terminal are directly connected. When a test clock signal is input from the Xin terminal 2 in this state, it is directly transmitted to the input terminal of the inverter 40 via the analog switch 22, and an inverted signal of the test clock signal is input to the clock circuit 11.

That is, the analog switch 22 causes the inverter 4 to
Since the DC level is transmitted to the 0 input terminal, the inverter 4 operates stably and the timepiece circuit 11 can be reliably driven.

〔Effect of the invention〕

As described in detail above, according to the present invention, the Xi
By providing an analog switch in parallel with the DC blocking capacitor between the n terminal and the input terminal of the inverter, and making the analog switch conductive during testing, it is possible to supply a stable signal to the clock circuit. It is possible to perform highly reliable logic tests.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an oscillation circuit of an electronic timepiece according to the present invention, and FIG. 2 is a block diagram of an oscillation circuit of a conventional electronic timepiece. 1... Crystal connection terminal for output, 2... Crystal connection terminal for input, 6... Crystal resonator, 4... Inverter, 7... ...DC blocking capacitor, 20...
・Test mode designation terminal, 22... Analog switch,

Claims (1)

[Claims] IC equipped with a crystal connection terminal for connecting a crystal resonator
In a crystal oscillation circuit having a chip, an inverter provided in the IC chip, and a capacitor connected between the input of the inverter and the crystal connection terminal, a switch means connected in parallel to the capacitor is provided, and the switch means is connected in parallel to the capacitor. A crystal oscillation circuit characterized in that the means is controlled by an external terminal provided on the IC chip.