JPS6252837B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device having multiple counting functions and testing functions thereof.

Conventionally, in an integrated circuit device for a watch, for example, in which a plurality of counting circuits are provided on a semiconductor chip, each counting circuit is connected in series, and the counting end signal (carry signal) of the preceding counting circuit is transmitted. It is used as a counting input signal for the counting circuit in the subsequent stage. especially,
In a watch integrated circuit, each counting circuit counts seconds, minutes, and
It is assigned as a counting means corresponding to the hour, day, year, etc. Furthermore, the clock integrated circuit is provided with a mechanism for testing the counting operation of the counting circuit, and this includes a mechanism for supplying a test clock signal to each counting circuit independently, and a mechanism for testing the counting operation of the counting circuit. There was one in which the power was supplied to both counting circuits at the same time.

However, in the former case, each counting circuit must be tested separately, which requires a large amount of testing time and is therefore not practical.
Moreover, in the latter case, it is very difficult to confirm the carry signal of the counting circuit. Furthermore, when integrating the clock function on a single chip using LSI technology, there was a restriction on the number of terminals that could be used, which caused major problems in the hardware configuration of the test function.

SUMMARY OF THE INVENTION An object of the present invention is to provide an integrated circuit device equipped with a mechanism that allows testing of a counting circuit easily and in a short period of time.

The integrated circuit according to the invention provides a first input signal between the input of the counting means having at least a first, second and third counting circuit coupled in series and a first input terminal to which the first input signal is supplied. 1 switch means, and second, third and fourth switches are provided between the inputs of the first, second and third counting circuits and a second input terminal to which the second input signal is supplied. means are respectively provided, in the first mode of operation the first switch means is made conductive and the second to fourth switch means are cut off, and in the second mode of operation the second and fourth switch means are made conductive and the first switch means are made conductive. and the third switch means is cut off or the third switch means is made conductive and the first, second and fourth switch means are made conductive.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and is a block diagram of essential parts when applied to a timepiece circuit. A signal oscillated from an oscillation circuit 1 such as a crystal oscillator or a ceramic oscillator is supplied to a frequency dividing circuit 2 and frequency-divided at a predetermined frequency division ratio. As a result, a clock signal is generated which is applied to the first input terminal T ₁ as a first input signal.
is supplied to The counting means has first to fourth counting circuits 3 to 6, each of which is divided into seconds, minutes, hours, and days, and has a second signal s, a minute signal m, an hour signal h, and a day signal D. are respectively output to a display section (not shown). OR on the input side of counting circuits 3 to 6
Gates 7 to 10 are provided respectively, and a carry signal from the counting circuit at the previous stage is supplied through these OR gates. A first switch 11 is connected between the first input terminal _T1 and the input of the counting means.

In addition, a test clock is provided as a second input signal.
TC is supplied to the second input terminal _T2 . The test clock TC to terminal _T2 is connected via signal line 16 to the second
It is supplied to one end of each of the fifth switches 12 to 15. The other ends of each of these switches 12 to 15 are connected to the inputs of counting circuits 3 to 6 via OR gates 7 to 10, respectively.

The first to fifth switches 11 to 15 are controlled to be turned on or off by control signals C ₀ to C ₂ from a control circuit 19. The control circuit 19 selectively generates control signals C ₀ to C ₂ depending on the operating mode.

That is, during clock operation, which is the first operation mode, the control circuit 19 generates a control signal _C0 and supplies it to the first switch 11 via the signal line 20, while other control signals Does not generate C ₁ or C ₂ . Therefore, the first switch 11 is conductive,
The second to fifth switches 12 to 15 are turned off. As a result, the clock signal to the terminal _T1 is supplied to the counting circuit 3 via the OR gate 7, and the counting circuits 4 to 6 in the subsequent stage are respectively supplied to the counting circuit 3 in the preceding stage.
It receives the carry signal (carry signal) from 5 to 5 and executes a counting operation. Second, minute, hour, and day data s, m, h, and D are output to a display section (not shown).

Next, in the test operation which is the second operation mode,
A check is required as to whether each of the counting circuits 3 to 6 executes a predetermined counting operation and outputs a carry signal. For this purpose, the control circuit (controller) 19 stops generating the control signal C ₀ to shut off the first switch 11 and first generates the control signal C ₁ . This signal _C1 is supplied to the second and fourth switches 12 and 14 via the signal line 17, and these become conductive. The test clock TC at terminal _T2 is thereby supplied to the counting circuits 3 and 5. At this time, since the control signal _C2 is not generated, the third and fifth switches 13 and 15 are in the cut-off state. Therefore,
It is possible to check the counting operations of the counting circuits 3 and 5, as well as the presence or absence of the output of the carry signal and the input state to the next stage counting circuits 4 and 6 that receive it. Next, the control circuit 9 stops the control signal C ₁ and outputs the signal C ₂
occurs. Control signal C ₀ remains stopped.
Therefore, the third and fifth switches 13,1
5 is conductive and the first, second and fourth switches 1
1, 12 and 14 are in a cut-off state. A test clock TC is supplied to the counting circuits 4 and 6, and a check similar to that described above is performed. Thus, in the test operation, which is the second operation mode, the test clock is applied to non-adjacent counting circuits among consecutive counting circuits. In particular, in the case of a clock circuit, it is preferable to pair odd-numbered stages and even-numbered stages.

Therefore, just by switching the control signals C ₁ and C ₂ ,
The operation of all counting circuits can be checked quickly and easily. In particular, when a person checks while looking at the actual display, it is easier to see if the display part changes every 1 or 2 digits than if all digits change at the same time, so this embodiment also has this point. The effect is large. Moreover, the basic functions of the watch can be viewed with a simple operation of just flipping an interlock switch once. Further, in testing in the mounted state, the wiring may be done so that the signal from the frequency divider 2 can be used as the test clock TC, for example, or, of course, an external terminal may be used to use an external clock signal.

Although it is preferable for each switch to be formed of a semiconductor element for reasons of integration, it is sufficient that the switch has a function of being controlled to be conductive or non-conductive in response to a control signal. Furthermore, the control signals C ₁ and C ₂ may be provided internally with a program-controlled controller 19, or may be input from the outside. It will be easily understood that these changes can be selected and used as appropriate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of essential parts of an embodiment in which the integrated circuit device of the present invention is applied to a timepiece circuit. 1... Oscillator, 2... Frequency divider, 3-6... Counting circuit, 7-10... OR gate, 11-15...
Switch, 16... signal line for test clock transfer, 7, 18, 20... control signal line, 19... controller.

Claims (1)

[Claims] 1 counting means having at least first and second input terminals to which first and second input signals are supplied, first, second and third counting circuits coupled in series; a first switch means provided between the input terminal of the counting means and the input of the counting means;
and second, third and fourth switch means respectively provided between the input of the third counting circuit, and in the first operation mode, the first switch means is made conductive and the second, third and fourth 3 and a fourth switch means are cut off, and in a second mode of operation, the second and fourth switch means are made conductive and the first and third switch means are cut off, or the third switch means is turned off. an integrated circuit device characterized by comprising: control means for making the first, second and fourth switch means conductive and cutting off the first, second and fourth switch means.