JPS642229B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to integrated circuits, and particularly to integrated circuits (hereinafter referred to as ICs) for electronic timekeeping.

In recent years, there has been an increasing demand for smaller ICs for electronic watches. A prerequisite for this miniaturization is that it has fewer external terminals.

By the way, after an IC is manufactured, it is tested to see if the internal circuit operation is normal. Moreover,
Shortening the test time will also contribute to cost reduction, and various testing methods have been proposed for this purpose. In particular, recent electronic watches have year, month, day, and stopwatch functions in addition to displaying the time.
Testing using an oscillation signal from an internal oscillation circuit requires an enormous amount of time to check all operations. For this reason, a predetermined counting circuit section, for example, only the counter section corresponding to "minutes" is selected, and a frequency signal much higher than the actual operating frequency is applied to it to complete the test in a short time. There is. This selection of a predetermined counting section is performed by a control circuit that generates data to be specified based on input data from the outside.

This will be explained in detail with reference to FIG. for watches
As is well known, in an IC, the output of an oscillation circuit 1 using a piezoelectric vibrator such as a crystal is divided by a frequency divider 2, and this is input to a counting circuit 3 to obtain data corresponding to time. It is supplied to the display device via the display drive circuit 4. Further, during testing, an input signal from the outside is applied via the input terminal 6 instead of using the oscillation signal of the oscillation circuit 1 as an input signal. The counting circuit 3 has counting sections facing each other for seconds, minutes, hours, months, and days.Therefore, it is necessary to check whether all of these counters are normal using the input signal from the input terminal 6. takes an enormous amount of time.

For this reason, the control circuit 5 specifies a predetermined counting section of the counting circuit 3, and tests are performed by applying a high-speed pulse supplied to the high-speed pulse input terminal 8. The data to be specified by the control circuit 5 is obtained by external signal input data from the test code creation input terminal 7. Note that the control circuit 5 is built into a watch IC.

The above configuration reduces the test time. However, the number of external terminals necessary to obtain a test code generation signal to the control circuit 5 increases as the number of operating functions of the counting circuit 3 increases. For this reason, the element area of the watch IC has increased, resulting in disadvantages such as deterioration in yield and increase in element price.

An object of the present invention is to provide an integrated circuit that eliminates the above-mentioned drawbacks, reduces the number of external terminals and reduces the element area without increasing test time, and thereby achieves improved yield and reduced cost. be.

According to the present invention, a frequency divider circuit configured with a plurality of frequency dividers that divides an input signal, and a counter configured with a plurality of counters that receive the output of the frequency divider circuit via a gate circuit. a circuit, a control terminal, an external pulse input terminal, means for closing the gate circuit when a control signal is applied to the control terminal, and at least a portion of the frequency divider configured in response to the control signal; the control circuit which inputs the output of each of the frequency generators and applies the pulse input to the external pulse terminal to a predetermined counter of the counting circuit based on the input data; The counting circuit counts the output of the frequency divider circuit when no signal is applied, and inputs the output to the external pulse terminal into a counter specified by the signal input to the input terminal when the control signal is applied. An integrated circuit is obtained, which is characterized in that the pulses are applied.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram showing one embodiment of the present invention, and the same functional parts as in FIG. 1 are denoted by the same numbers, and the explanation thereof will be omitted. The difference is that a gate circuit 9 is provided between the frequency dividing circuit 2 and the counting circuit 3, and the input to the control circuit 5 is taken from the output of the frequency divider at each stage constituting the frequency dividing circuit 2. It is not necessary to take out all the outputs of each frequency divider of the frequency dividing circuit 2, but it is sufficient to take out a predetermined number. Further, the gate circuit 9 and the control circuit 5 are operated by a switching signal from a test mode switching signal line 10.

That is, first, the input oscillation signal from the input terminal 6 is frequency-divided by the frequency dividing circuit 2, and this signal is supplied to the counting circuit 3 via the gate circuit 9. The counting circuit 3 generates a time display signal and supplies it to the display drive circuit 4. This determines whether the frequency dividing circuit is operating normally.

Next, by inputting the switching signal to the test mode switching signal terminal 10, the gate circuit 9 closes its gate (that is, cuts off the transmission of the output of the frequency dividing circuit 2 to the counting circuit), and The supply of the output of the circuit 2 is stopped. At the same time, the control circuit 5 becomes operational. Then, a signal is input from the input terminal 6 to the counting circuit 3 in order to create designated data. This is input to the frequency dividing circuit 2, which is composed of a plurality of frequency dividers, the output of each of which represents the above input data. The control circuit 5 takes in this and creates designated data accordingly. Then, a predetermined counting section of the counting circuit 3 is specified, and a high-speed pulse signal from the high-speed pulse input terminal 8 is applied thereto to test the counting section.

As is clear from the above description, there are no data input terminals for creating specified data, and the device area can be reduced. Furthermore, since each counting section of the counting circuit 3 is also tested using high-speed pulses, the testing time is also shortened.

In this embodiment, the high-speed pulse is controlled by the control circuit 5.
Although it is supplied via the counter circuit 3, it may be supplied directly to the counting circuit 3.

As described above, according to the present invention, it is possible to provide an integrated circuit in which the number of external terminals is reduced and the element area is reduced without increasing the test time, thereby achieving improved yield and reduced cost.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional watch IC, Figure 2 is a block diagram of a conventional watch IC.
The figure is a block diagram of a watch IC showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Oscillation circuit, 2... Frequency division circuit, 3... Counting circuit, 4... Display drive circuit, 5... Control circuit, 6
...Input terminal, 7...Input terminal for creating designated data, 8...High-speed pulse input terminal, 9...Gate circuit, 10...Test mode switching signal terminal.

Claims (1)

[Claims] 1. Generates a time display signal consisting of a frequency divider circuit consisting of multiple frequency dividers that divides the frequency of the input signal, and multiple counters that receive the output of the frequency divider circuit via a gate circuit. a control terminal, an external pulse input terminal, means for closing the gate circuit when a control signal is applied to the control terminal, and the frequency divider that configures the frequency dividing circuit in response to the control signal. Take each output from multiple as input,
and a control circuit that applies the pulse input to the external pulse terminal to a predetermined counter of the counting circuit based on the input data, and outputs the output of the frequency dividing circuit when the control signal is not applied. The counting circuit counts and sends a signal to the external pulse terminal to a designated counter according to designated data created according to the outputs of a plurality of frequency dividers in the frequency dividing circuit when the control signal is applied. An integrated circuit characterized by applying an input pulse.