EP0192456A2 - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
- Publication number
- EP0192456A2 EP0192456A2 EP86301107A EP86301107A EP0192456A2 EP 0192456 A2 EP0192456 A2 EP 0192456A2 EP 86301107 A EP86301107 A EP 86301107A EP 86301107 A EP86301107 A EP 86301107A EP 0192456 A2 EP0192456 A2 EP 0192456A2
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- EP
- European Patent Office
- Prior art keywords
- circuit
- internal circuit
- clock signal
- internal
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/24—Arrangements for testing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/26—Devices for calling a subscriber
- H04M1/30—Devices which can set up and transmit only one digit at a time
- H04M1/31—Devices which can set up and transmit only one digit at a time by interrupting current to generate trains of pulses; by periodically opening and closing contacts to generate trains of pulses
- H04M1/312—Devices which can set up and transmit only one digit at a time by interrupting current to generate trains of pulses; by periodically opening and closing contacts to generate trains of pulses pulses produced by electronic circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M1/00—Substation equipment, e.g. for use by subscribers
- H04M1/26—Devices for calling a subscriber
- H04M1/30—Devices which can set up and transmit only one digit at a time
- H04M1/50—Devices which can set up and transmit only one digit at a time by generating or selecting currents of predetermined frequencies or combinations of frequencies
Definitions
- a semiconductor integrated circuit used as a DTMF/pulse dialer comprises an internal circuit having a circuit for a DTMF dialer and a circuit for a pulse dialer, and an or basic oscillating circuit generating a fundamental(clock signal for operating the internal circuit when the internal circuit is operated in a usual mode. Further, the semiconductor integrated circuit has a predetermined number of pins (for example, eighteen) each of which functions as a terminal.
- the pins are provided for several purposes: i.e., input pins for or keypad supplying input signals from a keyboard/to the internal circuit in accordance with the operation of the keys provided on the keyboard; output pins for transmitting output signals from the internal circuit to a switching system; a pair of pins for the oscillating circuit which are connected to the input side and output side of the oscillating circuit respectively; a pin for supplying an external reset signal to the internal circuit; and a pair of pins for supplying power from power source to the semiconductor integrated circuit.
- the internal circuit operates as a DTMF dialer or as a pulse dialer selectively, in accordance with a control signal input to one of the input pins.
- the signal output from the internal circuit is an analog signal including frequency components corresponding to the operated key.
- the frequency components are determined in accordance with the position or keypad (i.e., the row and the column) on the keyboardLwhere the operated key is arranged.
- an analog signal sequentially including the frequency components in accordance with the sequentially operated keys is output from one of the output pins and transmitted to the switching system.
- the operational speed of the DTMF dialer is high, and the circuit for the DTMF dialer provided in the internal circuit is operated by receiving the fundamental clock signal, the frequency of which is a high value of, for example, 3.58 m.c. (megacycles) (3.58 MHz), from the above-mentioned oscillating circuit.
- the signal output from the internal circuit is a digital signal including a number of pulses which corresponds to the number indicated on the operated key.
- a digital signal as shown in Fig. 4 is output from one of the output pins and transmitted to the switching system.
- the operational speed of the pulse dialer is low compared to the operational speed of the DTMF dialer.
- each of the time lengths of the predigital pause t l and the interdigital pause t 2 is set to about 1 s.
- the cycle time of one pulse t 3 is set to about 100 ms. (milli-sec). Therefore, it is necessary to operate the circuit for the pulse dialer provided in the internal circuit by using the clock signal, the frequency of (2 kHz) which is a low value of, for example, 2 kc (kilocycles)t
- the frequency of the fundamental clock signal generated from the oscillating circuit is set to the high value of, for example, 3.58 MH z, in order to operate the circuit for the DTMF dialer in the internal circuit. Therefore, it is necessary to supply the clock signal to the circuit for the pulse dialer in the internal circuit by dividing the frequency of the fudamental clock signal, generated from the oscillating circuit, through a frequency divider.
- the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal generated from the oscillating circuit is also used as the clock signal for testing.
- it is also necessary to test the function of a redial key by determining whether or not the correct signal is output again when the redial key is operated.
- a semiconductor integrated circuit comprising:
- An embodiment of the present invention may allow testing of the functions of an internal circuit in a semiconductor integrated circuit at a high speed and thereby shorten the time for testing, without providing an additional terminal for testing but by using only generally existing terminals (namely, a reset terminal and a pair of terminals for the oscillating circuit).
- a semiconductor integrated circuit comprising an internal circuit; an oscillating circuit generating a fundamental clock signal for operating the internal circuit when the internal circuit is operated in a usual mode; a pair of terminals connected to the input side and output side of the oscillating circuit respectively, an oscillator connected between the above pair of terminals when the internal circuit is operated in the usual mode; a reset terminal through which a reset signal for resetting the internal circuit is supplied from outside of a chip to the internal circuit; and a test circuit for operating the internal circuit in a test mode, the test circuit supplying a clock signal for testing from outside of the chip to the internal circuit through one of the above pair of terminals when signals having a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals and the reset terminal.
- An embodiment of the present invention may provide a semiconductor integrated circuit having a test circuit for testing an internal circuit; more particularly, a semiconductor integrated circuit having a test circuit for a high-speed testing of the functions of the internal circuit.
- DTMF dual tone multi frequency
- pulse dialer provided in a telephone circuit
- the dialer having two circuits, namely, a circuit for the DTMF dialer and a circuit for the pulse dialer, on one chip, and performing two functions selectively, namely, the functions of a DTMF dialer and the functions of a pulse dialer.
- FIG. 1 An example of a known semiconductor integrated circuit . such as the above-mentioned DTMF/pulse dialer, is shown in Fig. 1.
- reference numeral 1 is an oscillating or basic circuit which generates a fundamental L clock signal having a frequency of, for example, 3.58 MHz.
- Reference numeral 2 is a frequency divider which divides the frequency of the fundamental clock signal generated from the oscillating circuit 1, and this frequency-divided clock signal is supplied through the signal path P to the internal circuit 9 to operate the circuit such as the pulse dialer provided in the internal circuit 9.
- the fundamental clock signal generated from the oscillating circuit 1 also is directly supplied through the signal path Q to the internal circuit 9 to operate the circuit such as the DTMF dialer provided in the internal circuit 9.
- Reference numeral 10' designates a chip on which the semiconductor integrated circuit comprising the.
- oscillating circuit 1 frequency divider 2, a feedback resister 63, and internal circuit 9 are provided.
- a predetermined number of pin terminals are provided on the chip 10', and only three pin terminals (i.e., a reset terminal Treset and a pair of terminals Toscin and Toscout each of which is connected to the input side and the output side of the oscillating circuit 1) are shown in Fig. 1.
- the reset terminal Treset is set to a low level
- the oscillating circuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of the chip 10' between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1.
- a feedback resistor 63 is connected between the input side and output side of the oscillating circuit 1, and the oscillating circuit 1 operates as, for example, a NOR gate.
- the fundamental clock signal generated from the oscillating circuit 1 is supplied through the frequency divider 2 and the signal path P to the circuit for the pulse dialer provided in the internal circuit 9.
- the fundamental clock signal generated from the oscillating circuit 1 also is directly supplied through the signal path Q to the circuit for the DTMF dialer provided in the internal circuit 9.
- the power-down signal PD for the internal circuit 9 is set to a low level by setting the reset terminal Treset to a low level, and as a result, the internal circuit 9 is released from the power-down state.
- a predetermined high level signal is supplied from outside to the reset terminal Treset.
- the level of both the output side and input side of the oscillating circuit 1 becomes low, and as a result, the oscillating circuit 1 is brought to a reset state.
- the power-down signal PD is set to a high ' level, and as a result, all parts of the internal circuit 9 are also reset to the initial state (non-operating state).
- the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal, generated from the oscillating circuit 1, through the frequency divider 2 is also used as the clock signal for testing, especially when tests of the functions of the circuit for the pulse dialer provided in the internal circuit 9 are carried out.
- Fig. 2 shows a circuit diagram illustrating one embodiment of the semiconductor integrated circuit according to the present invention.
- the semiconductor integrated circuit according to this embodiment comprises an oscillating circuit 1 generating the fundamental clock signal, having a frequency of, for example, 3.58 MHz the frequency divider 2; a switching-circuit 3, a NAND gate 4,/an AND gate 5 forming parts of a test circuit; feed back resistors 61 and 62, respectively connected to the input side and output side of the oscillating circuit 1; an N channel type MOS transistor 7; and the internal circuit 9 such as the above-mentioned DTMF/pulse dialer; all of which are provided on the same chip 10.
- a predetermined number of pin terminals are provided on the chip 10, but only three pin terminals (namely, a reset terminal Treset and a pair of terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1) are shown in Fig. 2.
- the switching circuit 3 switches two signal paths A and B selectively in accordance with the level of a control signal CNT output from the NAND gate 4 for testing.
- the reset terminal Treset is set to a low level, and the oscillating circuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of the chip 10 between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1.
- the oscillator 8 a crystal oscillator, for example
- the level of the NAND gatel (namely, the level of the control signal for testing CNT) becomes high.
- the switching circuit 3 closes the signal path A in accordance with the high level of the above control signal CNT.
- the fundamental clock signal generated from the oscillating circuit 1 is supplied through the frequency divider 2 and the signal path A to the circuit for the pulse dialer provided in the internal circuit 9.
- the fundamental clock signal generated from the oscillating circuit 1 is directly supplied through the signal path C to the circuit for the DTMF dialer provided in the internal circuit 9.
- the circuit for the pulse dialer in the internal circuit 9 is operated by the clock signal obtained by dividing the frequency of the fundamental clock signal, generated from the oscillating circuit 1, through the frequency divider 2, the frequency of which clock signal is, for example, 2 k H z.
- the internal circuit 9 operates as the DTMF dialer or as the pulse dialer selectively, in accordance with the control signal input from one of the input pin terminals not shown in the drawings.
- the oscillator 8 is disconnected from the terminals Toscin and Toscout, and the reset terminal Treset and the terminal Toscin connected to the input side of the oscillating circuit 1 are set to a high level. Then a clock signal for testing, the frequency of which clock signal for testing is set to 1/2 x. 3.58MHz ' , for example, is supplied from outside of the chip to the internal circuit 9 through the terminal Toscout connected to the output side of the oscillating circuit 1.
- the output level of the NAND gate 4 (namely, the level of the control signal for testing CNT) is set to.a low level by setting the terminals Treset and Toscin to a high level, and therefore, the switching circuit 3 closes the signal path B in accordance with the low level of the above control signal CNT.
- the clock signal input from the terminal Toscout for testing is directly supplied to the circuit for the pulse dialer provided in the internal circuit 9 through the signal path B, without passing through the frequency divider 2. Therefore, the tests of the functions for the pulse dialer can be carried out at a high speed by using the clock signal for testing having the frequency value of, for example, 1/2 x 3.58 MHz , as above-mentioned.
- the above clock signal for testing is directly supplied to the circuit for the DTMF dialer provided in the internal circuit 9, through the signal path C, and therefore, the tests of the functions for the DTMF dialer also can be carried out at a high speed.
- the tests for a part of the internal circuit 9 are carried out by the clock signal passing through the signal path B, even when the tests for the DTMF dialer are carried out.
- the oscillating _circuit 1 is brought to a non-operating state, and further, as the output level of the AND cate 5 is set to a low level, the internal circuit 9 is released from the power-down state.
- the reset terminal Treset is set to a high level, and thereby, the N channel type transistor 7 is turned ON. Therefore, both the input side and output side of the oscillating circuit 1 are set to a low ,by connection to ground via feedback resistors 61,62 level, and the oscillating circuit 1 is brought to a non-operating state. Further, as the output level of the NAND gate 4 becomes high, the output level of the AND gate 5, namely, the level of the power-down signal PD, becomes high, and as a result, the internal circuit 9 is brought to the reset state by the above power-down signal PD having a high level.
- Figure 3 is a circuit diagram illustrating an example of the switching circuit 3 shown in Fig. 2. As shown in Fig. 3, the switching circuit 3 comprises OR gates 31, 33, a NAND gate 34, and inverters 32 and 35.
- the output level of OR gate 31 is maintained at a high level, and thus, the fundamental clock signal supplied from the oscillating circuit 1 through the frequency divider 2 and the signal path A is transmitted to the internal circuit 9 through the OR gate 33 and the NAND gate 34.
- the clock signal output from the switching circuit 3 is brought into phase with the clock signal input to the switching circuit 3 by providing the inverter 35 connected to the output side of the NAND gate 34.
- the output level of OR gate 33 is maintained at a high level and, thus, the clock signal.for testing supplied from outside of the chip through the terminal Toscout and the signal path B is transmitted to the internal circuit 9 through the OR gate 31 and the NAND gate 34. -- .
- the clock signal output from the switching circuit 3 in the test mode also is brought into phase with the clock signal input to the switching circuit 3 by providing the inverter 35 connected to the output side of the NAND gate 34.
- the present invention it is possible to test the functions of the internal circuit provided in the miconductor integrated circuit at a high speed during the process of production and to raise the efficiency of the production line without providing an additional and exclusive terminal for testing, thus avoiding an increase in the size of the device.
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- Signal Processing (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
- Generally, a semiconductor integrated circuit used as a DTMF/pulse dialer comprises an internal circuit having a circuit for a DTMF dialer and a circuit for a pulse dialer, and an or basic oscillating circuit generating a fundamental(clock signal for operating the internal circuit when the internal circuit is operated in a usual mode. Further, the semiconductor integrated circuit has a predetermined number of pins (for example, eighteen) each of which functions as a terminal. In this connection, the pins are provided for several purposes: i.e., input pins for or keypad supplying input signals from a keyboard/to the internal circuit in accordance with the operation of the keys provided on the keyboard; output pins for transmitting output signals from the internal circuit to a switching system; a pair of pins for the oscillating circuit which are connected to the input side and output side of the oscillating circuit respectively; a pin for supplying an external reset signal to the internal circuit; and a pair of pins for supplying power from power source to the semiconductor integrated circuit. The internal circuit operates as a DTMF dialer or as a pulse dialer selectively, in accordance with a control signal input to one of the input pins.
- When the internal circuit operates as the DTMF dialer, the signal output from the internal circuit is an analog signal including frequency components corresponding to the operated key. Namely, the frequency components are determined in accordance with the position or keypad (i.e., the row and the column) on the keyboardLwhere the operated key is arranged. Thus, an analog signal sequentially including the frequency components in accordance with the sequentially operated keys is output from one of the output pins and transmitted to the switching system. In this connection, the operational speed of the DTMF dialer is high, and the circuit for the DTMF dialer provided in the internal circuit is operated by receiving the fundamental clock signal, the frequency of which is a high value of, for example, 3.58 m.c. (megacycles) (3.58 MHz), from the above-mentioned oscillating circuit.
- Contrary to this, when the internal circuit operates as the pulse dialer, the signal output from the internal circuit is a digital signal including a number of pulses which corresponds to the number indicated on the operated key. Thus, if three keys; numbered "1", "2", and "0", are sequentially operated, for example, a digital signal as shown in Fig. 4 is output from one of the output pins and transmitted to the switching system. In this connection, the operational speed of the pulse dialer is low compared to the operational speed of the DTMF dialer. As an explanation of this phenomenon regarding the signal shown in Fig. 4, each of the time lengths of the predigital pause tl and the interdigital pause t2 is set to about 1 s. (sec), and the cycle time of one pulse t3 is set to about 100 ms. (milli-sec). Therefore, it is necessary to operate the circuit for the pulse dialer provided in the internal circuit by using the clock signal, the frequency of (2 kHz) which is a low value of, for example, 2 kc (kilocycles)t
- However, as described above, the frequency of the fundamental clock signal generated from the oscillating circuit is set to the high value of, for example, 3.58 MHz, in order to operate the circuit for the DTMF dialer in the internal circuit. Therefore, it is necessary to supply the clock signal to the circuit for the pulse dialer in the internal circuit by dividing the frequency of the fudamental clock signal, generated from the oscillating circuit, through a frequency divider.
- Under the above-mentioned background, for known circuits, when the tests of the functions of the internal circuit (especially the functions of the circuit for the pulse dialer in the internal circuit) are carried out, the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal generated from the oscillating circuit is also used as the clock signal for testing. In this connection, it is necessary to perform several kinds of tests in order to test the functions of the internal circuit. Namely, it is necessary to test the function of each key in the DTMF dialer mode and in the pulse dialer mode by testing each key to determine whether or not the correct signal corresponding to the operated key is output from the predetermined output pin. In addition, it is also necessary to test the function of a redial key by determining whether or not the correct signal is output again when the redial key is operated.
- However, in a known circuit,as the internal circuit (especially the circuit for the pulse dialer) is operated by the above-mentioned clock signal, the frequency of which is divided through the frequency divider, in the test mode as well as in the usual mode, a problem arises in that a long time is needed to perform the several tests as above-mentioned, and as a result, the efficiency of the production is remarkably lowered, especially when the tests of the functions of the internal circuit are carried out during the process of mass production*.
- To solve this problem, consideration has been given to providing an exclusive terminal for testing besides the above-mentioned generally existing pin terminals and to supplying a clock signal for testing to the internal circuit through that exclusive terminal. However, in this case, it becomes necessary to provide an additional pin terminal for testing on each chip, and as a result, the size of the device is increased.
- According to the present invention, there is provided a semiconductor integrated circuit comprising:
- an internal circuit;
- an oscillating circuit for generating a basic clock signal for operating said internal circuit when said internal circuit is operated in a usual mode;
- a pair of terminals respectively connected to an input side and an output side of said oscillating circuit, an external oscillator being connected between said pair of terminals when said internal circuit is operated in the usual mode;
- a test circuit for operating said internal circuit, said test circuit comprising a switching circuit which selectively closes a first signal path supplying said basic clock signal to said internal circuit through said frequency divider in a usual mode or a second signal path supplying an external clock signal, for testing, to said internal circuit directly in a test mode.
- An embodiment of the present invention may allow testing of the functions of an internal circuit in a semiconductor integrated circuit at a high speed and thereby shorten the time for testing, without providing an additional terminal for testing but by using only generally existing terminals (namely, a reset terminal and a pair of terminals for the oscillating circuit).
- According to an embodiment of the present invention, there is provided a semiconductor integrated circuit comprising an internal circuit; an oscillating circuit generating a fundamental clock signal for operating the internal circuit when the internal circuit is operated in a usual mode; a pair of terminals connected to the input side and output side of the oscillating circuit respectively, an oscillator connected between the above pair of terminals when the internal circuit is operated in the usual mode; a reset terminal through which a reset signal for resetting the internal circuit is supplied from outside of a chip to the internal circuit; and a test circuit for operating the internal circuit in a test mode, the test circuit supplying a clock signal for testing from outside of the chip to the internal circuit through one of the above pair of terminals when signals having a predetermined level are supplied from outside of the chip to the test circuit through each of the other one of the above pair of terminals and the reset terminal.
- An embodiment of the present invention may provide a semiconductor integrated circuit having a test circuit for testing an internal circuit; more particularly, a semiconductor integrated circuit having a test circuit for a high-speed testing of the functions of the internal circuit.
- One of the uses to which such a semiconductor integrated circuit may be put is as a DTMF (dual tone multi frequency)/pulse dialer provided in a telephone circuit; the dialer having two circuits, namely, a circuit for the DTMF dialer and a circuit for the pulse dialer, on one chip, and performing two functions selectively, namely, the functions of a DTMF dialer and the functions of a pulse dialer.
- According to the above construction of the present invention, it is possible to carry out the test for the internal circuit at a high speed by directly supplying the clock signal having the predetermined frequency from outside of the chip to the internal circuit through one of a pair of terminals for the oscillating circuit (a terminal connected to the output side of the oscillating circuit, for example), when signals having a predetermined level are supplied from outside the chip to the test circuit through each of the other one of the above pair of terminals (a terminal connected to the input side of the oscillating circuit, for example) and the reset terminal.
Reference is made, by way of exanple, to the accompanying drawings, in which: - Figure 1 is a circuit diagram illustrating an example of a known semiconductor integrated circuit;
- Fig. 2 is a circuit diagram illustrating one embodiment of the semiconductor integrated circuit according to the present invention;
- Fig. 3 is a circuit diagram illustrating an example of the switching circuit provided in the semiconductor integrated circuit shown in Fig. 2; and
- Fig. 4 is a diagram illustrating an example of the wave form of the output signal output from the internal circuit provided in the semiconductor integrated circuit shown in Fig. 2.
- In order to clarify the background of the present invention, an example of a known semiconductor integrated circuit . such as the above-mentioned DTMF/pulse dialer, is shown in Fig. 1.
- In Fig. 1,
reference numeral 1 is an oscillating or basic circuit which generates a fundamentalLclock signal having a frequency of, for example, 3.58 MHz.Reference numeral 2 is a frequency divider which divides the frequency of the fundamental clock signal generated from the oscillatingcircuit 1, and this frequency-divided clock signal is supplied through the signal path P to theinternal circuit 9 to operate the circuit such as the pulse dialer provided in theinternal circuit 9. The fundamental clock signal generated from the oscillatingcircuit 1 also is directly supplied through the signal path Q to theinternal circuit 9 to operate the circuit such as the DTMF dialer provided in theinternal circuit 9. Reference numeral 10' designates a chip on which the semiconductor integrated circuit comprising the. above-mentioned oscillatingcircuit 1,frequency divider 2, a feedback resister 63, andinternal circuit 9 are provided. A predetermined number of pin terminals are provided on the chip 10', and only three pin terminals (i.e., a reset terminal Treset and a pair of terminals Toscin and Toscout each of which is connected to the input side and the output side of the oscillating circuit 1) are shown in Fig. 1. - When the
internal circuit 9 is operated in the usual mode, the reset terminal Treset is set to a low level, and the oscillatingcircuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of the chip 10' between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillatingcircuit 1. In this connection, afeedback resistor 63 is connected between the input side and output side of the oscillatingcircuit 1, and the oscillatingcircuit 1 operates as, for example, a NOR gate. - When the oscillating
circuit 1 operates, the fundamental clock signal generated from the oscillatingcircuit 1 is supplied through thefrequency divider 2 and the signal path P to the circuit for the pulse dialer provided in theinternal circuit 9. The fundamental clock signal generated from the oscillatingcircuit 1 also is directly supplied through the signal path Q to the circuit for the DTMF dialer provided in theinternal circuit 9. During this period, the power-down signal PD for theinternal circuit 9 is set to a low level by setting the reset terminal Treset to a low level, and as a result, theinternal circuit 9 is released from the power-down state. - When it is desired to set the
internal circuit 9 to a power-down mode, a predetermined high level signal is supplied from outside to the reset terminal Treset. Thereby, the level of both the output side and input side of the oscillatingcircuit 1 becomes low, and as a result, the oscillatingcircuit 1 is brought to a reset state. Simultaneously, the power-down signal PD is set to a high 'level, and as a result, all parts of theinternal circuit 9 are also reset to the initial state (non-operating state). - In such a prior art semiconductor integrated circuit, the above-mentioned clock signal obtained by dividing the frequency of the fundamental clock signal, generated from the
oscillating circuit 1, through thefrequency divider 2 is also used as the clock signal for testing, especially when tests of the functions of the circuit for the pulse dialer provided in theinternal circuit 9 are carried out. Thus, as described above, a problem arises in that a long time is needed to perform the several kinds of tests, and as a result, the efficiency of the production is remarkably lowered, especially when the tests of the functions of theinternal circuit 9 are carried out during the process of mass production. - The present invention is intended to solve such a problem, and Fig. 2 shows a circuit diagram illustrating one embodiment of the semiconductor integrated circuit according to the present invention. As shown in Fig. 2, the semiconductor integrated circuit according to this embodiment comprises an
oscillating circuit 1 generating the fundamental clock signal, having a frequency of, for example, 3.58 MHz thefrequency divider 2; a switching-circuit 3, a NAND gate 4,/an AND gate 5 forming parts of a test circuit; feedback resistors circuit 1; an N channel type MOS transistor 7; and theinternal circuit 9 such as the above-mentioned DTMF/pulse dialer; all of which are provided on thesame chip 10. A predetermined number of pin terminals are provided on thechip 10, but only three pin terminals (namely, a reset terminal Treset and a pair of terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillating circuit 1) are shown in Fig. 2. Theswitching circuit 3 switches two signal paths A and B selectively in accordance with the level of a control signal CNT output from the NAND gate 4 for testing. - When the
internal circuit 9 is operated in the usual mode, the reset terminal Treset is set to a low level, and the oscillatingcircuit 1 is operated by connecting the oscillator 8 (a crystal oscillator, for example) from outside of thechip 10 between the terminals Toscin and Toscout, each of which is connected to the input side and output side of the oscillatingcircuit 1. - In this period, as the reset terminal Treset is set to a low level, the level of the NAND gatel(namely, the level of the control signal for testing CNT) becomes high. Then, the
switching circuit 3 closes the signal path A in accordance with the high level of the above control signal CNT. Thus, the fundamental clock signal generated from theoscillating circuit 1 is supplied through thefrequency divider 2 and the signal path A to the circuit for the pulse dialer provided in theinternal circuit 9. Also, the fundamental clock signal generated from theoscillating circuit 1 is directly supplied through the signal path C to the circuit for the DTMF dialer provided in theinternal circuit 9. Accordingly, as described above, the circuit for the pulse dialer in theinternal circuit 9 is operated by the clock signal obtained by dividing the frequency of the fundamental clock signal, generated from theoscillating circuit 1, through thefrequency divider 2, the frequency of which clock signal is, for example, 2 kHz. In this connection, theinternal circuit 9 operates as the DTMF dialer or as the pulse dialer selectively, in accordance with the control signal input from one of the input pin terminals not shown in the drawings. - Next, when the
internal circuit 9 is set to the test mode in order to test the functions of the.internal circuit 9, theoscillator 8 is disconnected from the terminals Toscin and Toscout, and the reset terminal Treset and the terminal Toscin connected to the input side of theoscillating circuit 1 are set to a high level. Then a clock signal for testing, the frequency of which clock signal for testing is set to 1/2 x. 3.58MHz' , for example, is supplied from outside of the chip to theinternal circuit 9 through the terminal Toscout connected to the output side of theoscillating circuit 1. - In this case, namely, in the test mode, the output level of the NAND gate 4 (namely, the level of the control signal for testing CNT) is set to.a low level by setting the terminals Treset and Toscin to a high level, and therefore, the switching
circuit 3 closes the signal path B in accordance with the low level of the above control signal CNT. As a result, the clock signal input from the terminal Toscout for testing is directly supplied to the circuit for the pulse dialer provided in theinternal circuit 9 through the signal path B, without passing through thefrequency divider 2. Therefore, the tests of the functions for the pulse dialer can be carried out at a high speed by using the clock signal for testing having the frequency value of, for example, 1/2 x 3.58 MHz , as above-mentioned. Also, the above clock signal for testing is directly supplied to the circuit for the DTMF dialer provided in theinternal circuit 9, through the signal path C, and therefore, the tests of the functions for the DTMF dialer also can be carried out at a high speed. In this connection, the tests for a part of the internal circuit 9 (a receiving circuit for a key input signal, for example) are carried out by the clock signal passing through the signal path B, even when the tests for the DTMF dialer are carried out. Also, in the test mode, as the input side of the oscillating circuit is maintained at a high level as described above, theoscillating _circuit 1 is brought to a non-operating state, and further, as the output level of the AND cate 5 is set to a low level, theinternal circuit 9 is released from the power-down state. - Next, when the
internal circuit 9 is set to the power-down state, the reset terminal Treset is set to a high level, and thereby, the N channel type transistor 7 is turned ON. Therefore, both the input side and output side of theoscillating circuit 1 are set to a low ,by connection to ground viafeedback resistors oscillating circuit 1 is brought to a non-operating state. Further, as the output level of the NAND gate 4 becomes high, the output level of the AND gate 5, namely, the level of the power-down signal PD, becomes high, and as a result, theinternal circuit 9 is brought to the reset state by the above power-down signal PD having a high level. - Figure 3 is a circuit diagram illustrating an example of the
switching circuit 3 shown in Fig. 2. As shown in Fig. 3, the switchingcircuit 3 comprises ORgates NAND gate 34, andinverters - When the level of the control signal CNT output from the NAND gate 4 becomes high in the usual mode, the output level of
OR gate 31 is maintained at a high level, and thus, the fundamental clock signal supplied from theoscillating circuit 1 through thefrequency divider 2 and the signal path A is transmitted to theinternal circuit 9 through theOR gate 33 and theNAND gate 34. In this connection, the clock signal output from the switchingcircuit 3 is brought into phase with the clock signal input to theswitching circuit 3 by providing theinverter 35 connected to the output side of theNAND gate 34. - Contrary to this, when the level of the control signal CNT output from the NAND gate 4 becomes low in the test mode, the output level of
OR gate 33 is maintained at a high level and, thus, the clock signal.for testing supplied from outside of the chip through the terminal Toscout and the signal path B is transmitted to theinternal circuit 9 through theOR gate 31 and theNAND gate 34. -- . The clock signal output from the switchingcircuit 3 in the test mode also is brought into phase with the clock signal input to theswitching circuit 3 by providing theinverter 35 connected to the output side of theNAND gate 34. - As described above, according to the present invention, it is possible to test the functions of the internal circuit provided in the miconductor integrated circuit at a high speed during the process of production and to raise the efficiency of the production line without providing an additional and exclusive terminal for testing, thus avoiding an increase in the size of the device.
Claims (7)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60030190A JPS61191973A (en) | 1985-02-20 | 1985-02-20 | Semiconductor integrated circuit with testing circuit |
JP30190/85 | 1985-02-20 |
Publications (3)
Publication Number | Publication Date |
---|---|
EP0192456A2 true EP0192456A2 (en) | 1986-08-27 |
EP0192456A3 EP0192456A3 (en) | 1989-04-05 |
EP0192456B1 EP0192456B1 (en) | 1992-06-24 |
Family
ID=12296832
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP86301107A Expired - Lifetime EP0192456B1 (en) | 1985-02-20 | 1986-02-18 | Semiconductor integrated circuit |
Country Status (5)
Country | Link |
---|---|
US (1) | US4697140A (en) |
EP (1) | EP0192456B1 (en) |
JP (1) | JPS61191973A (en) |
KR (1) | KR900001242B1 (en) |
DE (1) | DE3685759T2 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6337270A (en) * | 1986-07-31 | 1988-02-17 | Fujitsu Ltd | Semiconductor device |
US4777619A (en) * | 1987-03-30 | 1988-10-11 | Honeywell Bull, Inc. | Method of assuring a proper computer subsystem configuration |
US4975641A (en) * | 1988-07-14 | 1990-12-04 | Sharp Kabushiki Kaisha | Integrated circuit and method for testing the integrated circuit |
JPH02181677A (en) * | 1989-01-06 | 1990-07-16 | Sharp Corp | Test mode switching system for lsi |
US5019772A (en) * | 1989-05-23 | 1991-05-28 | International Business Machines Corporation | Test selection techniques |
JPH02309818A (en) * | 1989-05-25 | 1990-12-25 | Yokogawa Electric Corp | A/d converter |
US5299203A (en) * | 1990-08-17 | 1994-03-29 | Sgs-Thomson Microelectronics, Inc. | Semiconductor memory with a flag for indicating test mode |
JP2803499B2 (en) * | 1992-11-26 | 1998-09-24 | 日本電気株式会社 | Analog / digital CMOS integrated circuit |
JP3193810B2 (en) * | 1993-08-31 | 2001-07-30 | 富士通株式会社 | Nonvolatile semiconductor memory device and test method therefor |
US5623687A (en) * | 1995-06-26 | 1997-04-22 | Motorola | Reset configuration in a data processing system and method therefor |
US5606715A (en) * | 1995-06-26 | 1997-02-25 | Motorola Inc. | Flexible reset configuration of a data processing system and method therefor |
US5818250A (en) * | 1996-07-03 | 1998-10-06 | Silicon Graphics, Inc. | Apparatus and method for determining the speed of a semiconductor chip |
US6076175A (en) * | 1997-03-31 | 2000-06-13 | Sun Microsystems, Inc. | Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits |
US6657504B1 (en) * | 2002-04-30 | 2003-12-02 | Unisys Corporation | System and method of determining ring oscillator speed |
US6815971B2 (en) * | 2002-11-06 | 2004-11-09 | Taiwan Semiconductor Manufacturing Co., Ltd | Method and apparatus for stress testing integrated circuits using an adjustable AC hot carrier injection source |
US20060248417A1 (en) * | 2005-04-28 | 2006-11-02 | International Business Machines Corporation | Clock control circuit for test that facilitates an at speed structural test |
US7187599B2 (en) * | 2005-05-25 | 2007-03-06 | Infineon Technologies North America Corp. | Integrated circuit chip having a first delay circuit trimmed via a second delay circuit |
JP2007157944A (en) * | 2005-12-02 | 2007-06-21 | Matsushita Electric Ind Co Ltd | Semiconductor integrated circuit device |
JP4940798B2 (en) * | 2006-07-11 | 2012-05-30 | トヨタ自動車株式会社 | Shock absorption structure |
JP6358840B2 (en) * | 2014-04-24 | 2018-07-18 | シャープ株式会社 | Electric grinder |
CN113533942B (en) * | 2021-09-15 | 2021-11-30 | 上海矽久微电子有限公司 | Chip testing system and method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3979681A (en) * | 1974-11-27 | 1976-09-07 | Solid State Scientific, Inc. | System and method for decoding reset signals of a timepiece for providing internal control |
GB2060958A (en) * | 1979-10-27 | 1981-05-07 | Itt | Monolithic integrated circuit for timepieces |
US4422038A (en) * | 1979-06-19 | 1983-12-20 | Fujitsu Limited | Integrated circuit with frequency-dividing circuits capable of being tested at a high speed |
JPS6012843A (en) * | 1983-07-02 | 1985-01-23 | Rohm Co Ltd | Dial conforming tone generating circuit of subscriber's telephone set |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2156863A1 (en) * | 1971-11-16 | 1973-05-24 | Heinz Schwerdtfeger | TEST DEVICE |
AU530415B2 (en) * | 1978-06-02 | 1983-07-14 | International Standard Electric Corp. | Integrated circuits |
JPS58196469A (en) * | 1982-05-12 | 1983-11-15 | Toshiba Corp | Testing of integrated circuit |
JPS58215047A (en) * | 1982-06-07 | 1983-12-14 | Toshiba Corp | Integrated circuit device |
JPS58222534A (en) * | 1982-06-18 | 1983-12-24 | Toshiba Corp | Integrated circuit |
-
1985
- 1985-02-20 JP JP60030190A patent/JPS61191973A/en active Granted
-
1986
- 1986-02-11 US US06/828,188 patent/US4697140A/en not_active Expired - Lifetime
- 1986-02-17 KR KR1019860001083A patent/KR900001242B1/en not_active IP Right Cessation
- 1986-02-18 DE DE8686301107T patent/DE3685759T2/en not_active Expired - Fee Related
- 1986-02-18 EP EP86301107A patent/EP0192456B1/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3979681A (en) * | 1974-11-27 | 1976-09-07 | Solid State Scientific, Inc. | System and method for decoding reset signals of a timepiece for providing internal control |
US4422038A (en) * | 1979-06-19 | 1983-12-20 | Fujitsu Limited | Integrated circuit with frequency-dividing circuits capable of being tested at a high speed |
GB2060958A (en) * | 1979-10-27 | 1981-05-07 | Itt | Monolithic integrated circuit for timepieces |
JPS6012843A (en) * | 1983-07-02 | 1985-01-23 | Rohm Co Ltd | Dial conforming tone generating circuit of subscriber's telephone set |
Non-Patent Citations (1)
Title |
---|
PATENT ABSTRACTS OF JAPAN, vol. 9, no. 126 (E-318)[1849], 31st May 1985; & JP-A-60 12 843 (ROOMU K.K.) 23-01-1985 * |
Also Published As
Publication number | Publication date |
---|---|
DE3685759T2 (en) | 1993-02-04 |
KR860006837A (en) | 1986-09-15 |
DE3685759D1 (en) | 1992-07-30 |
US4697140A (en) | 1987-09-29 |
EP0192456B1 (en) | 1992-06-24 |
EP0192456A3 (en) | 1989-04-05 |
JPS61191973A (en) | 1986-08-26 |
JPH0562705B2 (en) | 1993-09-09 |
KR900001242B1 (en) | 1990-03-05 |
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