CN113533942B

CN113533942B - Chip testing system and method

Info

Publication number: CN113533942B
Application number: CN202111077426.3A
Authority: CN
Inventors: 姜一舟; 黄戈; 王白羽; 李超; 荣念辰; 郑言龙; 陈成舜; 杨洁雨
Original assignee: Shanghai Xijiu Microelectronics Co ltd
Current assignee: Shanghai Sijiu Microelectronics Co.,Ltd.
Priority date: 2021-09-15
Filing date: 2021-09-15
Publication date: 2021-11-30
Anticipated expiration: 2041-09-15
Also published as: CN113533942A

Abstract

The invention discloses a chip testing system and a method, wherein a first testing module, a testing control module and a testing judgment module of the chip testing system are electrically connected with a functional circuit, the functional circuit comprises at least one functional unit, the first testing module comprises sampling units which are electrically connected with the functional units in a one-to-one correspondence manner, and each sampling unit comprises a sampling register, a first AND gate and a first OR gate; the test control module is electrically connected with each first test module respectively and used for enabling the first test modules according to the enabling sequence; the first test module is used for outputting a test result signal according to the test signal sent by the test judgment module; the test judgment module is used for determining whether the functional circuit is normal according to the test result signal. The first test module provided by the embodiment of the invention has the advantages of fewer devices, simple structure and convenience in operation. Meanwhile, compared with expensive test machine experimental equipment, the device in the embodiment of the invention is common and low in price, and the test cost is reduced.

Description

Chip testing system and method

Technical Field

The embodiment of the invention relates to the technical field of chip testing, in particular to a chip testing system and a chip testing method.

Background

The gated clock, the reset circuit and each pin of the chip are basic components of the chip, and whether the functions of the gated clock, the reset circuit and each pin determine whether the chip can work stably or not, so that the chip needs to be tested before the chip leaves a factory.

When the existing chip is tested, a professional test machine experimental device is mostly used for carrying out function test on the chip, the use cost of the test machine experimental device is expensive, the test cost of the chip can be increased, and when the chip is tested in the prior art, a test circuit is complex.

Disclosure of Invention

The invention provides a chip testing system and a method thereof, which aim to reduce the complexity and the testing cost of the chip testing system.

In a first aspect, an embodiment of the present invention provides a chip test system, where the chip includes an input/output pin and at least one functional circuit, where the at least one functional circuit includes a clock gating circuit and/or a reset circuit; the chip test system includes: the first test module, the test control module and the test judgment module are electrically connected with the functional circuits in a one-to-one correspondence manner; the functional circuit comprises at least one functional unit, the first test module comprises sampling units which are electrically connected with the functional units in a one-to-one correspondence mode, each sampling unit comprises a sampling register, a first AND gate and a first OR gate, and the first test module further comprises a first output end and a second output end;

the test judgment module is respectively electrically connected with the input/output pin and the test control module and is used for sending an enabling sequence to the test control module;

the test control module is respectively electrically connected with each first test module and used for enabling the first test modules according to the enabling sequence; the test judgment module is also used for sending a test signal corresponding to the enabling sequence to an input pin in the input and output pins;

the input end of the functional unit is electrically connected with the test control module, the signal input end of the sampling register is electrically connected with the input pin of the input/output pin, the function test input end of the sampling register is electrically connected with the corresponding output end of the functional unit, and the output end of the sampling register is electrically connected with the first input end of the first OR gate and the first input end of the first AND gate respectively;

a second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and an output end of the first OR gate is electrically connected with a first output end of the first test module;

the second input end of the first AND gate is connected to the bypass end of the test control module through a NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module;

the first test module is used for outputting a test result signal to an output pin in the input/output pins which are correspondingly and electrically connected through the first output end and the second output end according to the test signal input by the test signal input end of the sampling register and the circuit signal input by the functional test input end of the sampling register;

the test judgment module is further used for determining whether the functional circuit connected with the enabled first test module is normal according to the test result signal.

In a second aspect, an embodiment of the present invention further provides a chip testing method, where a first testing module includes a sampling unit, the sampling unit includes a sampling register, a first and gate and a first or gate, a signal input end of the sampling register is electrically connected to an input pin of an input/output pin, a function test input end of the sampling register is electrically connected to an output end of a function unit of a corresponding function circuit, and output ends of the sampling register are electrically connected to a first input end of the first or gate and a first input end of the first and gate, respectively; a second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and an output end of the first OR gate is electrically connected with a first output end of the first test module; the second input end of the first AND gate is connected to the bypass end of the test control module through a NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module; the first test module further comprises a first output end and a second output end;

the chip testing method comprises the following steps:

the test judgment module sends an enabling sequence to the test control module;

the test control module enables the first test module according to the enabling sequence; the test judgment module sends a test signal corresponding to the enabling sequence to an input pin in input and output pins;

the first test module outputs a test result signal to an output pin of the input/output pins through a first output end of the first test module and a second output end of the first test module according to the test signal input by the test signal input end of the sampling register and the circuit signal input by the functional test input end of the sampling register;

and the test judgment module determines whether the functional circuit connected with the enabled first test module is normal according to the test result signal.

The embodiment of the invention provides a chip test system and a method, wherein a chip comprises an input/output pin and at least one functional circuit; at least one functional circuit comprises a clock gating circuit and/or a reset circuit; the chip test system includes: the first test module, the test control module and the test judgment module are electrically connected with the functional circuit in a one-to-one correspondence manner; the functional circuit comprises at least one functional unit, the first test module comprises sampling units which are electrically connected with the functional units in a one-to-one correspondence mode, each sampling unit comprises a sampling register, a first AND gate and a first OR gate, and the first test module further comprises a first output end and a second output end; the test judgment module is respectively electrically connected with the input/output pin and the test control module and is used for sending an enabling sequence to the test control module; the test control module is used for enabling the first test module according to the enabling sequence; the test judgment module is also used for sending a test signal corresponding to the enabling sequence to an input pin in the input and output pins; the input end of the functional unit is electrically connected with the test control module, the signal input end of the sampling register is electrically connected with the input pin of the input/output pin, the function test input end of the sampling register is electrically connected with the output end of the corresponding functional unit, and the output end of the sampling register is electrically connected with the first input end of the first OR gate and the first input end of the first AND gate respectively; the second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and the output end of the first OR gate is electrically connected with the first output end of the first test module; the second input end of the first AND gate is connected to the bypass end of the test control module through the NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module; the first test module is used for outputting a test result signal to an output pin in the corresponding electrically connected input and output pins through the first output end and the second output end according to a test signal input by the test signal input end of the sampling register and a circuit signal input by the functional test input end of the sampling register; the test judgment module is also used for determining whether the functional circuit connected with the enabled first test module is normal according to the test result signal. The embodiment of the invention realizes the test of the chip performance through the test judgment module, the test control module and the first test module, and the first test module comprises the sampling register, the first AND gate, the first OR gate, the first output end and the second output end, so the structure is simple and the operation is convenient. Meanwhile, compared with expensive test machine experimental equipment, the device in the first test module is common and low in price, and the test cost is reduced.

Drawings

Fig. 1 is a schematic structural diagram of a chip testing system according to an embodiment of the present invention.

Fig. 2 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention.

Fig. 3 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention.

Fig. 4 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention.

Fig. 5 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention.

Fig. 6 is a flowchart of a chip testing method according to an embodiment of the present invention.

Fig. 7 is a flowchart of another chip testing method according to an embodiment of the present invention.

Fig. 8 is a flowchart of another chip testing method according to an embodiment of the present invention.

Fig. 9 is a flowchart of another chip testing method according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.

Fig. 1 is a schematic structural diagram of a chip testing system according to an embodiment of the present invention, and referring to fig. 1, a chip includes an input/output pin 100 and at least one functional circuit; at least one functional circuit comprises a clock gating circuit and/or a reset circuit; the chip test system includes: the first test module 300, the test control module 400 and the test judgment module 500 are electrically connected with the functional circuits in a one-to-one correspondence manner; the functional circuit comprises at least one functional unit 200, the first test module 300 comprises sampling units 321 electrically connected with the functional units 200 in a one-to-one correspondence manner, each sampling unit 321 comprises a sampling register 3211, a first and gate 3213 and a first or gate 3212, and the first test module 300 further comprises a first output terminal U1 and a second output terminal U2;

the test judgment module 500 is electrically connected to the input/output pin 100 and the test control module 400, respectively, and is configured to send an enable sequence to the test control module 400;

the test control module 400 is electrically connected to each of the first test modules 300, and is configured to enable the first test modules 300 according to an enable sequence;

the test judgment module 500 is further configured to send a test signal corresponding to the enable sequence to the input pin 110 of the input and output pins 100;

the input end of the functional unit 200 is electrically connected with the test control module 400, the signal input end of the sampling register 3211 is electrically connected with the input pin 110 of the input/output pin 100, the function test input end of the sampling register 3211 is electrically connected with the output end of the corresponding functional unit 200, and the output end of the sampling register 3211 is electrically connected with the first input end of the first or gate 3212 and the first input end of the first and gate 3213, respectively;

a second input terminal of the first or gate 3212 serves as a bypass terminal of the sampling unit 321 and is electrically connected to the test control module 400, and an output terminal of the first or gate 3212 is electrically connected to the first output terminal U1 of the first test module 300;

a second input end of the first and gate 3213 is connected to the bypass end of the test control module 400 through the not gate 3214, and an output end of the first and gate 3213 is electrically connected to a second output end U2 of the first test module 300;

the first testing module 300 is configured to output a testing result signal to the output pin 120 of the corresponding electrically connected input/output pin 100 through the first output terminal U1 and the second output terminal U2 according to a testing signal input from the testing signal input terminal of the sampling register 3211 and a circuit signal input from the functional testing input terminal of the sampling register 3211;

the test judgment module 500 is further configured to determine whether the functional circuit connected to the enabled first test module 300 is normal according to the test result signal.

Specifically, the functional circuit is a circuit that needs to be tested in a chip to ensure normal operation, and illustratively, the functional circuit includes at least a clock gating circuit or a reset circuit or both the clock gating circuit and the reset circuit. The test judgment module 500 may be a single chip microcomputer, and the test control module 400 may be a logic circuit. The enable sequence is a sequence transmitted from the test judging module 500 to the test control module 400 when it is determined to test a certain functional unit 200, and the test control module 400 transmits a signal to the functional unit 200 according to the sequence to enable the functional unit 200 and the first test module 300 connected to the functional unit 200. The enable module 300 may receive the test signal sent by the test judgment module 500 through the test signal input terminal, and the first test module 300 that is not enabled may not receive the test signal sent by the test judgment module 500. When it is required to test whether the functional unit 200 is working normally, the bypass terminal of the sampling unit 321 inputs a low level signal.

The input/output pins 100 may include all pins in the chip, or may include some pins in the chip.

Specifically, in this embodiment, the exemplary first test module includes two sampling units, and the exemplary functional circuit is a clock gating circuit, and the functional unit is a clock gating unit. Illustratively, a logic unit is included between the sampling unit 321 and the first output terminal U1, a logic unit is included between the sampling unit 321 and the second output terminal U2, and the logic unit between the sampling unit 321 and the first output terminal U1 is configured to connect the output terminal of each first or gate 3212 with the first output terminal U1, and to output a high level when each first or gate 3212 outputs a high level and output a low level when the output terminal of at least one first or gate 3212 outputs a low level. The logic unit between the sampling unit 321 and the second output terminal U2 is configured to connect the output terminal of each first and gate 3213 to the second output terminal U2, and is configured to output a high level when the output terminal of at least one first and gate 3213 outputs a high level, and output a low level when the output terminal of each first and gate 3213 outputs a low level. When testing whether the gated clock unit can be normally opened, the test judgment module 500 continues to send test signals to the test signal input end of the sampling register 3211 after sending the enable sequence to enable the first test module 300, where the test signals include high level signals and low level signals, and the test judgment module 500 sends the high level signals and the low level signals to the test signal input end in sequence. When the test determining module 500 sends a high level to the test signal input terminal of the sampling register 3211, and when the functional unit 200 works normally, the output terminal of the sampling register 3211 outputs a high level, the first input terminal of the first or gate 3212 inputs a high level, and the second input terminal of the first or gate 3212 inputs a low level, then the output terminal of the first or gate 3212 outputs a high level. A low level signal sent by a bypass terminal of the sampling unit 321 inputs a high level to a second input terminal of the first and gate 3213 after passing through the not gate 3214, and a high level is input to a first input terminal of the first and gate 3213 and a high level is input to a second input terminal of the first and gate 3213, so that a high level is output from an output terminal of the first and gate 3213. When all the functional units 200 can be normally turned on, the first output terminal U1 and the second output terminal U2 of the first test module 300 both output high signals. After the first output terminal U1 and the second output terminal U2 of the first testing module 300 output results, the testing and determining module 500 sends a low level to the testing signal input terminal of the sampling register 3211. When the gated clock unit is normally turned on, the output terminal of the sampling register 3211 outputs a low level, the first input terminal of the first or gate 3212 inputs a low level, and the second input terminal of the first or gate 3212 inputs a low level, so the output terminal of the first or gate 3212 outputs a low level. The low level input to the bypass terminal of the sampling unit 321 is input to the second input terminal of the first and gate 3213 through the not gate 3214, the low level is input to the first input terminal of the first and gate 3213, and the high level is input to the second input terminal of the first and gate 3213, so the low level is output from the output terminal of the first and gate 3213. When all the functional units 200 can be normally turned on, the first output terminal U1 and the second output terminal U2 of the first test module 300 both output low signals. Therefore, when the test judge module 500 sends a high level, the first output terminal U1 of the first test module 300 and the second output terminal U2 of the first test module 300 both output a high level and when the test judge module 500 sends a low level, the first output terminal U1 of the first test module 300 and the second output terminal U2 of the first test module 300 both output a low level, and each gated clock unit can be normally turned on. Otherwise, at least one gated clock unit cannot be normally opened.

When the functional circuit comprises one functional unit 200, the first test module comprises one sampling unit 321. in an alternative embodiment, logic units are included between the sampling unit 321 and the first output terminal U1 and the second output terminal U2, respectively, and the logic units function as in the case where the functional circuit comprises two functional units. In another alternative embodiment, the output end of the sampling unit 321 is directly connected to the first output end U1 and the second output end U2, and the test process and the result determination process are the same as above, and are not described herein again.

The embodiment provides a chip test system and a method thereof, wherein a chip comprises an input/output pin and at least one functional circuit; at least one functional circuit comprises a clock gating circuit and/or a reset circuit; the chip test system includes: the first test module, the test control module and the test judgment module are electrically connected with the functional circuit in a one-to-one correspondence manner; the functional circuit comprises at least one functional unit, the first test module comprises sampling units which are electrically connected with the functional units in a one-to-one correspondence mode, each sampling unit comprises a sampling register, a first AND gate and a first OR gate, and the first test module further comprises a first output end and a second output end; the test judgment module is respectively electrically connected with the input/output pin and the test control module and is used for sending an enabling sequence to the test control module; the test control module is used for enabling the first test module according to the enabling sequence; the test judgment module is also used for sending a test signal corresponding to the enabling sequence to an input pin in the input and output pins; the input end of the functional unit is electrically connected with the test control module, the signal input end of the sampling register is electrically connected with the input pin of the input/output pin, the function test input end of the sampling register is electrically connected with the output end of the corresponding functional unit, and the output end of the sampling register is electrically connected with the first input end of the first OR gate and the first input end of the first AND gate respectively; the second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and the output end of the first OR gate is electrically connected with the first output end of the first test module; the second input end of the first AND gate is connected to the bypass end of the test control module through the NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module; the first test module is used for outputting a test result signal to an output pin in the corresponding electrically connected input and output pins through the first output end and the second output end according to a test signal input by the test signal input end of the sampling register and a circuit signal input by the functional test input end of the sampling register; the test judgment module is also used for determining whether the functional circuit connected with the enabled first test module is normal according to the test result signal. The test to the chip performance is realized through the test judgment module, the test control module and the first test module in the embodiment, and the first test module comprises a sampling register, a first AND gate, a first OR gate, a first output end and a second output end, and the test device is simple in structure and convenient to operate. Meanwhile, compared with expensive test machine experimental equipment, the device in the first test module is common and low in price, and the test cost is reduced.

Fig. 2 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention, referring to fig. 2, optionally, the first testing module 300 further includes a result processing unit 322, and the result processing unit 322 includes a second and gate 3222 and a second or gate 3221;

the output end of the first or gate 3212 is electrically connected to the input end of the second and gate 3222, and the output end of the second and gate 3222 serves as the first output end U1 of the first testing module 300;

the output terminal of the first and gate 3213 is electrically connected to the input terminal of the second or gate 3221, and the output terminal of the second or gate 3221 serves as the second output terminal U2 of the first testing module 300.

Specifically, the sampling unit 321 is electrically connected to the first output terminal U1 of the first testing module 300 through the second and gate 3222, and the sampling unit 321 is electrically connected to the second output terminal U2 of the first testing module 300 through the second or gate 3221.

Illustratively, the functional unit 200 is a gated clock unit, and in conjunction with the operation procedure of testing whether the gated clock unit is normally turned on in the above embodiment, when a high level is input to the test signal input terminal of the sampling register 3211, and when all the gated clock units under test can be normally turned on, the output terminal of the first or gate 3212 connected to each gated clock unit outputs a high level signal, the output terminal of each and gate 3213 outputs a high level signal, then the inputs of the respective input terminals of the second and gate 3222 are all high levels, and the output terminal of the second and gate 3222 outputs a high level. The input of each input terminal of the second or gate 3221 is a high level, and the output terminal of the second or gate 3221 outputs a high level. After the first output terminal U1 and the second output terminal U2 of the first testing module 300 output results, the testing and determining module 500 sends a low level to the testing signal input terminal of the sampling register 3211. When all the gated clock units to be tested can be normally opened, the output end of the first or gate 3212 connected to each gated clock unit outputs a low level signal, the output end of each and gate 3213 outputs a low level signal, the inputs of the respective input ends of the second and gate 3222 are all low levels, and the output end of the second and gate 3222 outputs a low level. Each input terminal of the second or gate 3221 is input with a low level, and an output terminal of the second or gate 3221 outputs a low level. Therefore, when the test judge module 500 sends a high level, the first output terminal U1 of the first test module 300 and the second output terminal U2 of the first test module 300 both output a high level and when the test judge module 500 sends a low level, the first output terminal U1 of the first test module 300 and the second output terminal U2 of the first test module 300 both output a low level, and each gated clock unit can be normally turned on. Otherwise, at least one gated clock unit cannot be normally opened.

Illustratively, when the functional circuit comprises one functional unit 200, in an alternative embodiment the first test module comprises one sampling unit 321. The second and gate 3222 includes a plurality of input terminals, one input terminal of the second and gate 3222 is connected to the output terminal of the first or gate 3212, and the remaining input terminals of the second and gate 3222 are connected to the high-level signal. The second or gate 3221 includes a plurality of input terminals, one input terminal of the second or gate 3221 is connected to the output terminal of the first and gate 3213, and the remaining input terminals of the second or gate 3221 are connected to the low-level signal.

With continued reference to fig. 2, optionally, the test control module 400 is configured to output a setting signal to a bypass terminal of the sampling unit 321 according to the test signal, where the setting signal includes a bypass signal and a working signal, and the sampling unit 321 is configured to output a first intermediate result signal according to the bypass signal, so that the test result signal output by the result processing unit 322 is unrelated to the working state of the functional unit 200 connected to the sampling unit 321; the sampling unit 321 is further configured to output a second intermediate result signal according to the working signal and the test signal, so that the test result signal output by the result processing unit is related to the working state of the functional unit 200 connected to the sampling unit 321.

Illustratively, the bypass signal is a high level signal and the operating signal is a low level signal. When the functional units 200 are clock gating units, taking the example of inputting a high level to the test signal input end of the sampling register 3211 as an example, when all the functional units 200 in the functional circuit are tested, the test control module 400 outputs a low level signal to the bypass ends of all the sampling units 321, the signal output by the output end of the first or gate 3212 is the same as the signal output by the sampling register 3211, and the signal output by the output end of the first and gate 3213 is the same as the signal output by the sampling register 3211, that is, the first intermediate result signal is two high level signals at this time. When a certain functional unit 200 needs to be shielded, the test control module 400 outputs a high level signal to the bypass terminal of the sampling unit 321 connected to the functional unit 200, then the signal output by the output terminal of the first or gate 3212 is always high level, the signal output by the output terminal of the first and gate 3213 is always low level, that is, at this time, the first intermediate result signal includes a high level signal and a low level signal, and the high level signal output by the output terminal of the first or gate 3212 is input to the input terminal of the second and gate 3222 without affecting the signal output by the second and gate 3222, and the low level signal output by the output terminal of the first and gate 3212 is input to the input terminal of the second or gate 3221 without affecting the signal output by the output terminal of the second or gate 3212, and further, when the bypass signal is input to the bypass terminal of the sampling unit 321 connected to the functional unit 200, the test result signal output by the result processing unit 322 is unrelated to the working state of the functional unit 200 connected to the sampling unit 321 .

When it is determined through the test that at least one functional unit 200 has a fault, the functional unit may be masked by setting a bypass end of the sampling unit 321 connected to the functional unit 200 to output a bypass signal, and then testing the unmasked functional unit 200 again to see whether an abnormal functional unit exists in the unmasked functional unit 200, and if the abnormal functional unit does not exist, continuing to mask one functional unit 200 until the functional unit with the fault is checked.

Fig. 3 is a schematic structural diagram of another chip test system according to an embodiment of the present invention, referring to fig. 3, optionally, at least one of the first test modules includes a clock test module 320, the functional test input end of the sampling register 3211 includes a clock signal input end I1, the functional unit includes a gated clock unit 211, and the clock signal input end I1 is electrically connected to the output end of the gated clock unit 211;

the test control module 400 is configured to send an enable signal to the clock gating unit 211 after receiving the first enable sequence corresponding to the enable clock test module 320, so that the clock gating unit 211 outputs a clock signal to the correspondingly connected sampling unit 321;

the test judgment module 500 is configured to send a first test signal and a second test signal corresponding to a first enable sequence to the input pin 110 connected to the clock test module 320 after sending the first enable sequence, where potentials of the first test signal and the second test signal are opposite; the sampling unit 321 is configured to output a first sampling result according to the first test signal, and the result processing unit 322 is configured to output a first test result signal according to the first sampling result through the output pin 120 connected to the first output terminal U1 and the output pin 120 connected to the second output terminal U2; the sampling unit 321 is configured to output a second sampling result according to the second test signal, and the result processing unit 322 is configured to output a second test result signal according to the second sampling result through the output pin 120 connected to the first output terminal U1 and the output pin 120 connected to the second output terminal U2;

the test determining module 500 is further configured to determine whether the clock gating unit 211 is normally turned on according to the first test result signal and the second test result signal.

Specifically, the clock gating unit 211 is a clock gating component in the chip, and is used for sending a clock signal. The clock sampling unit 321 may include a logic gate circuit for outputting a sampling result according to the operating state of the clock gating unit 211 and the test signal sent by the test judging module 500, and the first result processing unit 322 may be a logic gate circuit for outputting a test result signal according to the sampling result. The sampling register 3211 further includes a reset signal input terminal, and when the gated clock unit 211 is tested, the reset signal input terminal may access a set level signal, which may be, for example, a high level, to enable the sampling register 3211 to be in a non-reset state.

The first enabling sequence is a sequence with the clock test module 320 as the current test module. The exemplary functional circuit shown in this embodiment includes two clock gating cells 211. Illustratively, the first test signal is high and the second test signal is low. The sampling unit 321 is electrically connected to the test judgment module 500 through the input pin 110, and the first test signal and the second test signal sent by the test judgment module 500 are transmitted to the sampling unit 321 through the input pin 110. Each sampling unit 321 is also electrically connected to the test control module 400.

When the clock gating unit 211 connected to the sampling unit 321 normally outputs a clock signal to the sampling unit 321, the sampling result output by the sampling unit 321 is the same as the test signal input by the sampling unit 321; when the clock gating unit 211 is turned off, i.e., the output of the clock signal to the sampling unit 321 is stopped, and the sampling result output by the sampling unit 321 is the latest test signal sent by the test judgment module 500 before the clock gating unit 211 is turned off, the output end of the sampling unit 321 keeps the signal unchanged until the clock gating unit 211 is turned on again.

When testing whether the gated clock unit 211 can be normally turned on, the test determining module 500 sends a first test signal, i.e., a high level, to the test signal input terminal of the sampling register 3211, and a bypass terminal of the sampling unit 321, i.e., a second input terminal of the first or gate 3212, inputs a low level. When the gate control clock unit 211 works normally, the output terminal of the sampling register 3211 outputs a high level, the first input terminal of the first or gate 3212 inputs a high level, and the second input terminal of the first or gate 3212 inputs a low level, so the output terminal of the first or gate 3212 outputs a high level. A low level sent by the shielding end of the sampling unit 321 is input to the second input end of the first and gate 3213 through the not gate 3214, and a high level is input to the first input end of the first and gate 3213, so that the output end of the first and gate 3213 outputs a high level, that is, the first sampling result output by the sampling unit 321 is two high level signals. The input end of the second and gate 3222 is the high level output by each first or gate 3212, and the output end of the second and gate 3222 outputs the high level; the input end of the second or gate 3221 is at a high level output by each first and gate 3213, and the output end of the second or gate 3221 outputs a high level, so the first test result signal is also two high level signals. After the second and gate 3222 and the second or gate 3221 output the first test result signal, the test determining module 500 sends a second test signal, i.e., a low level, to the test signal input end of the sampling register 3211. When the gate control clock unit 211 works normally, the output terminal of the sampling register 3211 outputs a low level, the first input terminal of the first or gate 3212 inputs a low level, and the second input terminal of the first or gate 3212 inputs a low level, so the output terminal of the first or gate 3212 outputs a low level. The low level input to the shielding end of the sampling unit 321 is input to the second input end of the first and gate 3213 through the not gate 3214, and the low level is input to the first input end of the first and gate 3213, so that the output end of the first and gate 3213 outputs the low level, that is, the second sampling result is two low level signals. The input end of the second and gate 3222 is the low level output by each first or gate 3212, and the output end of the second and gate 3222 outputs the low level; the input end of the second or gate 3221 is the low level output by each first and gate 3213, and the output end of the second or gate 3221 outputs the low level, that is, the second test result signal is two low level signals. Therefore, when the test judgment module 500 sends a high level, both the first output terminal U1 of the result processing unit 322 and the second output terminal U2 of the result processing unit 322 output a high level, and when the test judgment module 500 sends a low level, both the first output terminal U1 of the result processing unit 322 and the second output terminal U2 of the result processing unit 322 output a low level, each clock gating unit 211 can be normally turned on. Otherwise, there is at least one gated clock unit 211 that cannot be normally turned on.

With continued reference to fig. 3, optionally, the test control module 400 is configured to send a shutdown signal to the clock gating unit 211 after receiving the second enable sequence corresponding to the shutdown clock test module 320, so that the clock gating unit 211 stops outputting the clock signal to the corresponding connected sampling unit 321;

the test judgment module 500 is configured to send a third test signal corresponding to the second enable sequence to the input pin 110 connected to the clock test module 320 after sending the second enable sequence, where the third test signal has the same potential as the first test signal; the sampling unit 321 is configured to output a third sampling result according to the third test signal, and the result processing unit 322 is configured to output a third test result signal according to the third sampling result through the output pin 120 connected to the first output terminal U1 and the output pin connected to the second output terminal U2;

the test determining module 500 is further configured to determine whether the gated clock unit 211 is normally turned off according to the third test result signal.

Illustratively, the first test signal is high, the second test signal is low, and the third test signal is high. After the test judge module 500 sends the high and low level test gated clock units 211 to be normally turned on, the test judge module 500 sends the second enable sequence, so that the clock gating unit 211 stops outputting the clock signal to the sampling register 3211, and at this time, the output terminal of the sampling register 3211 outputs a low level, the test and determination module 500 sends a third test signal, i.e., a high level, to the sampling register 3211, when the sampling registers 3211 are normally closed, the output terminal of the sampling register 3211 is not affected by the signal input from the test signal input terminal, and the output is maintained at a low level, at this time, the output terminal of the first or gate 3212 outputs a low level, the output terminal of the first and gate 3213 outputs a low level, that is, the third sampling result is two low level signals, the output terminal of the second and gate 3222 outputs a low level, and the output terminal of the second or gate 3221 outputs a low level, that is, the third test result signal is two low level signals. Therefore, when the test and judgment module 500 sends a high level to the sampling register 3211, if both the output end of the second and gate 3222 and the output end of the second or gate 3221 output a low level, both the gated clock units 211 can be normally turned off, otherwise, at least one gated clock unit 211 cannot be turned off.

Fig. 4 is a schematic structural diagram of another chip test system according to an embodiment of the present invention, and referring to fig. 4, optionally, at least one of the first test modules includes a reset test module 330, the functional test input terminal of the sampling register 3211 includes a reset signal input terminal I2, and the functional unit includes a reset unit 221; the reset signal input terminal I2 is electrically connected with the output terminal of the reset unit 221;

the test control module 400 is configured to send an enable signal to the reset unit 221 after receiving a third enable sequence corresponding to the enable reset test module 330, so that the reset unit 221 outputs a reset signal to the correspondingly connected sampling unit 321;

the test judgment module 500 is configured to send a fourth test signal corresponding to the third enable sequence to the input pin 110 connected to the reset test module 330 after sending the third enable sequence; the sampling unit 321 is configured to output a fourth sampling result according to the fourth test signal, and the result processing unit 322 is configured to output a fourth test result signal according to the fourth sampling result through the output pin 120 connected to the first output terminal U1 and the output pin 120 connected to the second output terminal U2;

the test judgment module 500 is further configured to judge whether the reset unit 221 is normally reset according to the fourth test result signal.

Specifically, the sampling register 3211 further includes a clock signal input terminal, and when the reset unit 221 is tested, the clock signal input terminal is connected to a stable clock signal. The sampling register 3211 may be a register that outputs a high level all the time after receiving the reset signal, or a register that outputs a low level all the time after receiving the reset signal may be used as the output terminal of the sampling register 3211, which shows that the output terminal of the sampling register 3211 outputs a high level all the time after receiving the reset signal in this embodiment. On the premise that it is determined that the sampling unit 321 and the result processing unit 322 are functioning normally, the test control module 400 controls the reset unit 221 to input a reset signal to the reset signal input end I2 of the sampling register 3211, the bypass end of the sampling unit 321 inputs a low level, after the sampling register 3211 receives the reset signal, the output end of the sampling register 3211 always maintains a high level, at this time, the test judgment module 500 inputs a low level to the test signal input end of the sampling register 3211, the output end of the sampling register 3211 outputs a high level to the first input end of the first or gate 3212 and the first input end of the first and gate 3213, the output end of the first or gate 3212 outputs a high level, and the output end of the first and gate 3213 outputs a high level, that is, the fourth sampling result is two high level signals. The input terminal of the second or gate 3221 is the high level output by the output terminal of each first and gate 3213, so the output terminal of the second or gate 3221 outputs the high level, and the input terminal of the second and gate 3222 is the high level output by each first or gate 3212, so the output terminal of the second and gate 3222 outputs the high level, that is, the fourth test result signal is two high levels. Therefore, when the test signal input end of the sampling register 3211 inputs a low level, if the output end of the second and gate 3222 and the output end of the second or gate 3221 both output a high level, the reset units 221 may both be reset normally, otherwise, at least one reset unit 221 may not be reset normally.

With continued reference to fig. 4, optionally, the test control module 400 is configured to send a release reset signal to the reset unit 221 after receiving the fourth enable sequence of releasing the reset test module 330, so that the reset unit 221 releases the reset;

the test judgment module 500 is configured to send a fifth test signal and a sixth test signal corresponding to the fourth enable sequence to the input pin 110 connected to the reset test module 330 after sending the fourth enable sequence, where potentials of the fifth test signal and the sixth test signal are opposite; the sampling unit 321 is configured to output a fifth sampling result according to the fifth test signal, and the result processing unit 322 is configured to output a fifth test result signal according to the fifth sampling result through the output pin 120 connected to the first output terminal U1 and the output pin 120 connected to the second output terminal U2; the sampling unit 321 is configured to output a sixth sampling result according to the sixth test signal, and the result processing unit 322 is configured to output a sixth test result signal according to the sixth sampling result through the output pin 120 connected to the first output terminal U1 and the output pin 120 connected to the second output terminal U2;

the test judgment module 500 is further configured to judge whether the reset unit 221 normally releases the reset according to the fifth test result signal and the sixth test result signal.

Illustratively, the fifth test signal is at a high level, the sixth test signal is at a low level, and the operation principle of the chip test system in this embodiment is as follows: the test determining module 500 sends a high level to the test signal input end of the sampling register 3211 through the input pin 110, when all the reset units 221 to be tested can normally release reset, a signal output by the output end of the sampling register 3211 is the same as a signal input by the test signal input end, that is, the output end of the sampling register 3211 outputs a high level to the first input end of the first and gate 3213 and the first input end of the first or gate 3212, the bypass end of the sampling unit 321 inputs a low level, the second input end of the first or gate 3212 inputs a low level, the low level input by the first or gate 3212 outputs a high level to the first and gate 3213 through the not gate 3214, and the first and gate 3212 outputs a high level and the first and gate 3213 outputs a high level, that is, the fifth sampling result is two high levels. The input of each input terminal of the second and gate 3222 is a high level, and the output terminal of the second and gate 3222 outputs a high level. The inputs of the respective input terminals of the second or gate 3221 are all high levels, and the output terminal of the second or gate 3221 outputs a high level, so that the fifth test result signal is two high levels. After the first output terminal U1 and the second output terminal U2 of the reset test module 330 output the fifth test result signal, the test judgment module 500 sends a low level to the test signal input terminal of the sampling register 3211. The output end of the sampling register 3211 outputs a low level to the first input end of the first and gate 3213 and the first input end of the first or gate 3212, and the bypass end of the sampling unit 321 inputs a low level, then the second input end of the first or gate 3212 inputs a low level, the low level input by the first or gate 3212 outputs a high level to the first and gate 3213 through the not gate 3214, then the output end of the first or gate 3212 outputs a low level, and the output end of the first and gate 3213 outputs a high level, that is, the sixth sampling result is two low levels. The input of each input terminal of the second and gate 3222 is low level, and the output terminal of the second and gate 3222 outputs low level. The input of each input end of the second or gate 3221 is a low level, and the output end of the second or gate 3221 outputs a low level, so that the sixth test result signal is two high levels. Therefore, when the test judgment module 500 sends a high level, the first output terminal U1 of the reset test module 330 and the second output terminal U2 of the reset test module 330 both output a high level, and when the test judgment module 500 sends a low level, the first output terminal U1 of the reset test module 330 and the second output terminal U2 of the reset test module 330 both output a low level, then each reset unit 221 can normally release the reset. Otherwise, there is at least one reset unit 221 that cannot normally release the reset.

Fig. 5 is a schematic structural diagram of another chip testing system according to an embodiment of the present invention, referring to fig. 5, optionally, the chip testing system further includes a second testing module 600, where the second testing module 600 is electrically connected to at least a portion of the input/output pins 100;

the test determining module 500 is configured to send a fifth enabling sequence corresponding to enabling the second test module to the test control module 400, and then send a seventh test signal corresponding to the fifth enabling sequence to the first partial input/output pin 130;

and is further used for determining whether the input/output pins 100 are normal according to the seventh test result signal output by the second partial input/output pins 140;

wherein the first portion input output pin 130 and the second portion input output pin 140 are different.

Specifically, the fifth enabling sequence is a sequence that enables the second test module 600. The seventh test signal is a signal for testing the input/output pin 100, and the seventh test signal may be a sequence combination of high and low signals of each of the first partial input/output pins. The second testing module 600 is used to test whether each pin of the chip is normal, and the second testing module 600 may be a circuit structure of the chip corresponding to each pin. All pins of the chip are divided into two parts, one part is used as a pin for receiving the test signal sent by the test judgment module 500, namely, a first part input/output pin 130, and the other part is used as a pin for outputting a seventh test result signal, namely, a second part input/output pin 140. The second partial input/output pin 140 outputs a corresponding potential signal according to the high/low level signal of the first partial input/output pin 130. The test determination module 500 stores a set pin potential signal (when the set pin potential signal is a signal output by the second part input/output pin 140 when the first part input/output pin 130 and the second part input/output pin 140 are both normal and a seventh test signal is input into the first part input/output pin 130), and when the seventh test signal is input into the first part input/output pin 130 and the signal output by the second part input/output pin 140 is the set pin potential signal, the input/output pin 100 functions normally.

Optionally, the test judgment module is independent of the outside of the chip, and the first test module and the test control module are integrated on the chip.

Fig. 6 is a flowchart of a chip testing method according to an embodiment of the present invention, where the first testing module includes a sampling unit, the sampling unit includes a sampling register, a first and gate and a first or gate, a signal input end of the sampling register is electrically connected to an input pin of the input/output pin, a function testing input end of the sampling register is electrically connected to an output end of a corresponding function unit of the function circuit, and output ends of the sampling register are electrically connected to a first input end of the first or gate and a first input end of the first and gate, respectively; the second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and the output end of the first OR gate is electrically connected with the first output end of the first test module; the second input end of the first AND gate is connected to the bypass end of the test control module through the NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module; the first test module further comprises a first output end and a second output end; referring to fig. 6, the chip testing method includes:

s10: the test judgment module sends an enabling sequence to the test control module;

s20: enabling the first test module by the test control module according to the enabling sequence;

s30: the test judgment module sends a test signal corresponding to the enabling sequence to an input pin in the input/output pins;

s40: the first test module outputs a test result signal to an output pin of the input/output pins through a first output end of the first test module and a second output end of the first test module according to a test signal input by a test signal input end of the sampling register and a circuit signal input by a function test input end of the sampling register;

s50: and the test judgment module determines whether the functional circuit connected with the enabled first test module is normal or not according to the test result signal.

The embodiment provides a chip testing method, wherein a testing control module enables a first testing module according to an enabling sequence sent by a testing judgment module; the first test module outputs a test result signal to an output pin in the input and output pins according to a test signal sent by the test judgment module through the input pin; and the test judgment module determines whether the functional circuit connected with the first test module is normal according to the test result signal. The embodiment realizes the test of the chip performance, has simple method and improves the efficiency of the chip test.

Fig. 7 is a flowchart of another chip testing method according to an embodiment of the present invention, where at least one first testing module includes a clock testing module, a function testing input end of a sampling register includes a clock signal input end, the first testing module further includes a result processing unit, the result processing unit includes a second and gate and a second or gate, an output end of the first or gate is electrically connected to an input end of the second and gate, an output end of the second and gate serves as a first output end of the first testing module, an output end of the first and gate is electrically connected to an input end of the second or gate, and an output end of the second or gate serves as a second output end of the first testing module; the functional unit comprises a gate control clock unit, and the clock signal input end is electrically connected with the output end of the gate control clock unit; referring to fig. 7, optionally, the chip testing method includes:

s11: the test judgment module sends a first enabling sequence corresponding to the enabling clock test module to the test control module;

s21: enabling the clock test module by the test control module according to the first enabling sequence;

s31: after receiving a first enabling sequence corresponding to an enabling clock testing module, a testing control module sends an enabling signal to a gating clock unit so that the gating clock unit outputs a clock signal to a sampling unit which is correspondingly connected;

s41: after sending the first enabling sequence, the test judgment module sends a first test signal and a second test signal corresponding to the first enabling sequence to an input pin connected with the clock test module in sequence, and the potentials of the first test signal and the second test signal are opposite; the sampling unit outputs a first sampling result according to the first test signal, and the result processing unit outputs a first test result signal according to the first sampling result through an output pin connected with a first output end and an output pin connected with a second output end; the sampling unit outputs a second sampling result according to a second test signal, and the result processing unit outputs a second test result signal according to the second sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

s51: the test judgment module judges whether the gating clock unit is normally opened according to the first test result signal and the second test result signal.

Optionally, after the test determining module determines whether the gated clock unit is normally turned on according to the first test result signal and the second test result signal, the method includes:

after receiving a second enabling sequence corresponding to the clock-off test module, the test control module sends a closing signal to the gated clock unit so that the gated clock unit stops outputting clock signals to the sampling units which are correspondingly connected;

after sending the second enabling sequence, the test judgment module sends a third test signal corresponding to the second enabling sequence to an input pin connected with the clock test module, and the third test signal has the same potential as the first test signal; the sampling unit outputs a third sampling result according to a third test signal, and the result processing unit outputs a third test result signal according to the third sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

and the test judgment module judges whether the gating clock unit is normally closed or not according to the third test result signal.

Fig. 8 is a flowchart of another chip testing method according to an embodiment of the present invention, where at least one first testing module includes a reset testing module, a function testing input end of a sampling register includes a reset signal input end, the first testing module further includes a result processing unit, the result processing unit includes a second and gate and a second or gate, an output end of the first or gate is electrically connected to an input end of the second and gate, an output end of the second and gate serves as a first output end of the first testing module, an output end of the first and gate is electrically connected to an input end of the second or gate, and an output end of the second or gate serves as a second output end of the first testing module; the functional unit comprises a reset unit, and a reset signal input end is electrically connected with an output end of the reset unit; referring to fig. 8, optionally, the chip testing method includes:

s12: the test judgment module sends a third enabling sequence corresponding to the enabling reset test module to the test control module;

s22: enabling the reset test module by the test control module according to the third enabling sequence;

s32: after receiving a third enabling sequence corresponding to the enabling reset testing module, the testing control module sends an enabling signal to the reset unit so that the reset unit outputs a reset signal to the sampling unit which is correspondingly connected;

s42: after sending the third enabling sequence, the test judgment module sends a fourth test signal corresponding to the third enabling sequence to an input pin connected with the reset test module; the sampling unit outputs a fourth sampling result according to a fourth test signal, and the result processing unit outputs a fourth test result signal according to the fourth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

s52: and the test judgment module judges whether the reset unit is normally reset according to the fourth test result signal.

Optionally, the test determining module further includes, after determining whether the reset unit is normally reset according to the fourth test result signal:

after receiving the fourth enabling sequence of the releasing reset test module, the test control module sends a releasing reset signal to the reset unit so as to enable the reset unit to release reset;

after sending the fourth enabling sequence, the test judgment module sends a fifth test signal and a sixth test signal corresponding to the fourth enabling sequence to an input pin connected with the reset test module in sequence, and the potentials of the fifth test signal and the sixth test signal are opposite; the sampling unit outputs a fifth sampling result according to the fifth test signal, and the result processing unit outputs a fifth test result signal according to the fifth sampling result through an output pin connected with the first output end and an output pin connected with the second output end; the sampling unit outputs a sixth sampling result according to the sixth test signal, and the result processing unit outputs a sixth test result signal according to the sixth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

and the test judgment module judges whether the reset unit normally releases reset according to the fifth test result signal and the sixth test result signal.

Fig. 9 is a flowchart of another chip testing method according to an embodiment of the present invention, and referring to fig. 9, the chip testing method includes:

s13: the test judgment module sends a fifth enabling sequence corresponding to the second testing module to the test control module;

s23: enabling the second test module by the test control module according to the fifth enabling sequence;

s33: the test judgment module sends a seventh test signal corresponding to the fifth enabling sequence to the first part input/output pin;

s43: the test judgment module determines whether the input/output pins are normal according to a seventh test result signal output by the second part of input/output pins;

wherein the input and output pins of the first part are different from the input and output pins of the second part.

It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A chip test system is characterized in that the chip comprises an input/output pin and at least one functional circuit, wherein the at least one functional circuit comprises a gate clock circuit and/or a reset circuit; the chip test system includes: the first test module, the test control module and the test judgment module are electrically connected with the functional circuits in a one-to-one correspondence manner; the functional circuit comprises at least one functional unit, the first test module comprises sampling units which are electrically connected with the functional units in a one-to-one correspondence mode, each sampling unit comprises a sampling register, a first AND gate and a first OR gate, and the first test module further comprises a first output end and a second output end;

the input end of the functional unit is electrically connected with the test control module, the test signal input end of the sampling register is electrically connected with the input pin of the input/output pin, the function test input end of the sampling register is electrically connected with the corresponding output end of the functional unit, and the output end of the sampling register is electrically connected with the first input end of the first OR gate and the first input end of the first AND gate respectively;

2. The chip test system according to claim 1, wherein the first test module further comprises a result processing unit, the result processing unit comprising a second and gate and a second or gate;

the output end of the first OR gate is electrically connected with the input end of the second AND gate, and the output end of the second AND gate is used as the first output end of the first test module;

the output end of the first AND gate is electrically connected with the input end of the second OR gate, and the output end of the second OR gate is used as the second output end of the first test module.

3. The chip test system according to claim 2, wherein the test control module is configured to output a setting signal to a bypass terminal of the sampling unit according to the test signal, wherein the setting signal includes a bypass signal and a working signal, and the sampling unit is configured to output a first intermediate result signal according to the bypass signal, so that the test result signal output by the result processing unit is independent of a working state of a functional unit connected to the sampling unit; the sampling unit is further used for outputting a second intermediate result signal according to the working signal and the test signal, so that the test result signal output by the result processing unit is related to the working state of the functional unit connected with the sampling unit.

4. The chip test system according to claim 2, wherein at least one of the first test modules comprises a clock test module, the functional test input of the sampling register comprises a clock signal input, the functional unit comprises a clock gating unit, and the clock signal input is electrically connected with an output of the clock gating unit;

the test control module is used for sending an enabling signal to the gated clock unit after receiving a first enabling sequence corresponding to the enabled clock test module so as to enable the gated clock unit to output a clock signal to the sampling unit which is correspondingly connected;

the test judgment module is used for sequentially sending a first test signal and a second test signal corresponding to the first enable sequence to the input pin connected with the clock test module after sending the first enable sequence, and the potentials of the first test signal and the second test signal are opposite; the sampling unit is used for outputting a first sampling result according to the first test signal, and the result processing unit is used for outputting a first test result signal according to the first sampling result through an output pin connected with the first output end and an output pin connected with the second output end; the sampling unit is used for outputting a second sampling result according to the second test signal, and the result processing unit is used for outputting a second test result signal according to the second sampling result through an output pin connected with a first output end and an output pin connected with a second output end;

the test judgment module is further configured to judge whether the gated clock unit is normally turned on according to the first test result signal and the second test result signal.

5. The chip test system according to claim 4, wherein the test control module is configured to send a shutdown signal to the clock gating unit after receiving a second enable sequence corresponding to shutting down the clock test module, so that the clock gating unit stops outputting the clock signal to the correspondingly connected sampling unit;

the test judgment module is used for sending a third test signal corresponding to the second enabling sequence to the input pin connected with the clock test module after sending the second enabling sequence, and the third test signal has the same potential as the first test signal; the sampling unit is used for outputting a third sampling result according to the third test signal, and the result processing unit is used for outputting a third test result signal according to the third sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

the test judgment module is further used for judging whether the gating clock unit is normally closed according to the third test result signal.

6. The chip test system according to claim 2, wherein the at least one first test module comprises a reset test module, the functional test input of the sampling register comprises a reset signal input, and the functional unit comprises a reset unit; the reset signal input end is electrically connected with the output end of the reset unit;

the test control module is used for sending an enabling signal to the resetting unit after receiving a third enabling sequence corresponding to enabling the resetting test module so as to enable the resetting unit to output a resetting signal to the sampling unit which is correspondingly connected;

the test judgment module is used for sending a fourth test signal corresponding to the third enabling sequence to the input pin connected with the reset test module after sending the third enabling sequence; the sampling unit is used for outputting a fourth sampling result according to the fourth test signal, and the result processing unit is used for outputting a fourth test result signal according to the fourth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

the test judgment module is further used for judging whether the reset unit is normally reset according to the fourth test result signal.

7. The chip test system according to claim 6, wherein the test control module is configured to send a release reset signal to the reset unit to cause the reset unit to release the reset after receiving a fourth enable sequence for releasing the reset test module;

the test judgment module is used for sending a fifth test signal and a sixth test signal corresponding to the fourth enable sequence to the input pin connected with the reset test module after sending the fourth enable sequence, and the potentials of the fifth test signal and the sixth test signal are opposite; the sampling unit is used for outputting a fifth sampling result according to the fifth test signal, and the result processing unit is used for outputting a fifth test result signal according to the fifth sampling result through an output pin connected with the first output end and an output pin connected with the second output end; the sampling unit is used for outputting a sixth sampling result according to the sixth test signal, and the result processing unit is used for outputting a sixth test result signal according to the sixth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

the test judgment module is further configured to judge whether the reset unit normally releases the reset according to the fifth test result signal and the sixth test result signal.

8. The chip test system according to claim 1, further comprising a second test module electrically connected to at least a portion of the input-output pins;

the test judging module is used for sending a fifth enabling sequence corresponding to enabling the second test module to the test control module and then sending a seventh test signal corresponding to the fifth enabling sequence to the first part of the input/output pins;

and the second part of the input/output pins are used for outputting a seventh test result signal;

9. The chip testing system of claim 1, wherein the testing judgment module is independent of the chip, and the first testing module and the testing control module are integrated on the chip.

10. The chip testing method is characterized in that a first testing module comprises a sampling unit, the sampling unit comprises a sampling register, a first AND gate and a first OR gate, a signal input end of the sampling register is electrically connected with an input pin in an input-output pin, a function testing input end of the sampling register is electrically connected with an output end of a corresponding function unit of a function circuit, and an output end of the sampling register is electrically connected with a first input end of the first OR gate and a first input end of the first AND gate respectively; a second input end of the first OR gate is used as a bypass end of the sampling unit and is electrically connected with the test control module, and an output end of the first OR gate is electrically connected with a first output end of the first test module; the second input end of the first AND gate is connected to the bypass end of the test control module through a NOT gate, and the output end of the first AND gate is electrically connected with the second output end of the first test module; the first test module further comprises a first output end and a second output end;

the chip testing method comprises the following steps:

the test judgment module sends an enabling sequence to the test control module;

the test control module enables the first test module according to the enabling sequence;

the test judgment module sends a test signal corresponding to the enabling sequence to an input pin in input and output pins;

11. The chip testing method according to claim 10, wherein at least one of the first test modules comprises a clock test module, the functional test input terminal of the sampling register comprises a clock signal input terminal, the first test module further comprises a result processing unit, the result processing unit comprises a second and gate and a second or gate, the output terminal of the first or gate is electrically connected to the input terminal of the second and gate, the output terminal of the second and gate serves as the first output terminal of the first test module, the output terminal of the first and gate is electrically connected to the input terminal of the second or gate, and the output terminal of the second or gate serves as the second output terminal of the first test module; the functional unit comprises a gate control clock unit, and the clock signal input end is electrically connected with the output end of the gate control clock unit;

the test judgment module sends an enabling sequence to the test control module, and the enabling sequence comprises the following steps:

the test judging module sends a first enabling sequence corresponding to an enabling clock test module to the test control module;

the enabling, by the test control module, the first test module according to the enabling sequence includes:

the test control module enables the clock test module according to the first enabling sequence;

the test judging module sends a test signal corresponding to the enabling sequence to an input pin in input and output pins, and the test judging module comprises:

the test control module sends an enabling signal to a gated clock unit after receiving a first enabling sequence corresponding to enabling the clock test module, so that the gated clock unit outputs a clock signal to the sampling unit which is correspondingly connected;

the first test module outputs a test result signal to an output pin of the input/output pins through a first output terminal of the first test module and a second output terminal of the first test module according to the test signal input by the test signal input terminal of the sampling register and a circuit signal input by the functional test input terminal of the sampling register, and the test result signal includes:

after sending the first enabling sequence, the test judgment module sends a first test signal and a second test signal corresponding to the first enabling sequence to the input pin connected with the clock test module in sequence, and the potentials of the first test signal and the second test signal are opposite; the sampling unit outputs a first sampling result according to the first test signal, and the result processing unit outputs a first test result signal according to the first sampling result through an output pin connected with the first output end and an output pin connected with the second output end; the sampling unit outputs a second sampling result according to the second test signal, and the result processing unit outputs a second test result signal according to the second sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

the step of determining whether the functional circuit connected with the enabled first test module is normal by the test judgment module according to the test result signal comprises:

the test judging module judges whether the gated clock unit is normally opened according to the first test result signal and the second test result signal.

12. The chip testing method according to claim 11, wherein after the test determining module determines whether the clock gating unit is normally turned on according to the first test result signal and the second test result signal, the method comprises:

after receiving a second enabling sequence corresponding to the clock test module, the test control module sends a closing signal to the gated clock unit so that the gated clock unit stops outputting clock signals to the sampling units which are correspondingly connected;

after sending the second enabling sequence, the test judgment module sends a third test signal corresponding to the second enabling sequence to the input pin connected with the clock test module, and the third test signal has the same potential as the first test signal; the sampling unit outputs a third sampling result according to the third test signal, and the result processing unit outputs a third test result signal according to the third sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

and the test judgment module judges whether the gated clock unit is normally closed according to the third test result signal.

13. The chip testing method according to claim 10, wherein at least one of the first test modules comprises a reset test module, the functional test input terminal of the sampling register comprises a reset signal input terminal, the first test module further comprises a result processing unit, the result processing unit comprises a second and gate and a second or gate, the output terminal of the first or gate is electrically connected to the input terminal of the second and gate, the output terminal of the second and gate serves as the first output terminal of the first test module, the output terminal of the first and gate is electrically connected to the input terminal of the second or gate, and the output terminal of the second or gate serves as the second output terminal of the first test module; the functional unit comprises a reset unit, and the reset signal input end is electrically connected with the output end of the reset unit;

the test judgment module sends a third enabling sequence corresponding to the enabling reset test module to the test control module;

the test control module enables the reset test module according to the third enabling sequence;

after receiving a third enabling sequence corresponding to enabling the reset testing module, the testing control module sends an enabling signal to a reset unit so that the reset unit outputs a reset signal to a sampling unit which is correspondingly connected;

the first test module outputs a test result signal to an output pin of the input/output pins through a first output terminal of the first test module and a second output terminal of the first test module according to the test signal input by the test signal input terminal of the sampling register and the circuit signal input by the functional test input terminal of the sampling register, and the test result signal includes:

after sending the third enabling sequence, the test judgment module sends a fourth test signal corresponding to the third enabling sequence to the input pin connected with the reset test module; the sampling unit outputs a fourth sampling result according to the fourth test signal, and the result processing unit outputs a fourth test result signal according to the fourth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;

and the test judgment module judges whether the reset unit is normally reset according to the fourth test result signal.

14. The chip testing method according to claim 13, wherein the step of judging whether the reset unit is normally reset according to the fourth test result signal by the test judging module comprises:

after receiving a fourth enabling sequence for releasing the reset test module, the test control module sends a release reset signal to the reset unit so as to enable the reset unit to release reset;

after sending the fourth enabling sequence, the test judgment module sends a fifth test signal and a sixth test signal corresponding to the fourth enabling sequence to the input pin connected with the reset test module in sequence, and the potentials of the fifth test signal and the sixth test signal are opposite; the sampling unit outputs a fifth sampling result according to the fifth test signal, and the result processing unit outputs a fifth test result signal according to the fifth sampling result through an output pin connected with the first output end and an output pin connected with the second output end; the sampling unit outputs a sixth sampling result according to the sixth test signal, and the result processing unit outputs a sixth test result signal according to the sixth sampling result through an output pin connected with the first output end and an output pin connected with the second output end;