JPS58129274A - Testing method of large scale integrated circuit - Google Patents

Abstract

PURPOSE:To test plural LSIs simultaneously by providing an auxiliary circuit, controlling the number of clocks to be applied to the LSIs to be measured, and synchronizing the plural LSIs. CONSTITUTION:An auxiliary circuit is provided to a DUT port in which the tester terminals of a test head and the measuring pins of the LSIs to be measured are made correspondent by wirings. When a match mode is selected and a 10-pin driver side turns to a high level, an AND gate 31 opens. The clocks from a 4-pin driver through the gate 31 and OR gate 32 thereof are applied to the LSI which is the device to be measured. When the counter, etc. having no reset terminals of the LSI attain prescribed value, the gate 31 is closed by the high level output from the LSI and the LSI is held in an initial state. On the other hand, the clocks are continuously supplied to the other LSI to be measured by which said LSI is initialized and is synchronized with the already initialized LSI to be measured. As a result, the plural LSIs are tested simultaneously by the same program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an improvement in a L8I measurement method, and particularly relates to an improved method for simultaneously measuring a plurality of L8Is.

[Technical background of the invention]

First, a test device that can perform functional tests on a plurality of L8Is at the same time will be described. In order to simplify the explanation, an apparatus having a test head 1 and a test head 2 and measuring two devices at the same time will be described here, but the same applies even if there are more test heads.

Figure 1 shows an outline of the test equipment. First, the control staff manages processes such as storing the test program, distributing it to the device under test L8I, managing pattern addresses, generating various timings, and importing judgment information such as the output state of the device under test L8I. The test pattern issuing section I receives the test data stored in the control section member through the signal line (c), and here it receives test data such as NRZ (non-return/zero), aZ (return zero), and RC (return combination). This test pattern is converted into a test waveform and sent as data to a test head driver (FIG. 4), which will be described later, via a signal line αe. Chest head (1'rI and (II) apply the test 7 soturn formed by the pattern discharging section Q4 to the device under test LSI at a programmed voltage value, and take in the data of the output pin of this device under test L8I. The data received by the head aη, 08 is input to the device output comparison section (2) via the signal line QIJ.
A comparison is made here. The determination information from this comparison S (to) is received by the control section 03 through the signal line (21).

Next, a detailed circuit example of the test 7-turn payout section I is shown in FIG. Here, the output timing and waveform format are determined for the data of test 7, turn 1, and O. At this time, the signal rails are still at logic levels 1''1'' and θ''. The driver (27) shown in the test head of FIG. 4 applies the logic levels "1" and "O" to the device under test at programmed voltage values. This driver (2
7), the LSI under test outputs an output commensurate with the input signal given by the high level comparator (28) in Figure 4.
) and is converted into a signal having logic levels "1" and "0" again by passing through the low level comparator (29). FIG. 3 is a detailed circuit example of the device output comparison section (support) of FIG. 1. The current expected value pattern is stored in the comparison pattern holding register (22), and the contents of this comparison pattern holding register and test heads 1 and 2 are converted to logic levels via high level and low level comparators, respectively. L
SI output and first judgment section (23) sSecond judgment section (24)
It is judged by.

If the device output fails as a result of this determination, it is stored in the first fail register (25) and the 27th fail register (26), respectively, and sent to the control section. Based on this result, the control section notifies the test equipment user whether the device under test is a good product or a defective product.

A typical example of a paper test process in which multiple L8Is are measured simultaneously is an IC memory test. However, in many LSI devices, it is not easy to initialize the L8I, so the L8I is initialized using the aforementioned MATCH mode, and then an actual test is performed.

Here, the ``rMAYCH mode'' will be explained in more detail. For example, an IC like a counter without a reset terminal
In this case, the internal state at the time of power-on is completely undefined, so the expected value/model cannot be known until a certain state is reached, so input signals are continued to be applied until a certain state is reached. After that, the actual test is carried out after reaching a ``certain state''. The mode for detecting this "certain state" is called "rMA'rCH mode". Actually, program M as shown in Table 1 below.
Detect ATCH.

(R/Margin) Table 1 The test 7 turn description consists of an instruction part and a pin description part, and the pin description is pin 1, pin 2 from the left, etc.
...means the data.

In the above test/turn, specify that the MATCH pin is the 1 pin at address 0, and repeat the MATCH pin up to 100 times at address 1 until the output of that l pin becomes "1".
Repeat the street number pattern. The output data of pin 1 is “1”
” then move to number 2.

If repeating 100 times does not result in 4 “1”, MAT
A CH error occurs.

[Problems with the background technology] According to the background technology on paper, if there are two L8I devices to be measured on the test head 1 side and the test head 2 side, the number of times MATCH is applied is the same for device 1 and device 2. Therefore, simultaneous measurements are not possible.

[Purpose of the invention]

This enables simultaneous measurement of multiple L8Is requiring MATCH mode, which was not possible in the background art.

[Embodiments of the invention]

Assuming that the l pin is the MATCH pin and the clock is being supplied from pin 4 to the device under test in the test nomiturn described above, the attached circuit as shown in Figure 5 is connected to the DUT.
Wire it on the board and test it with the test pattern shown in Table 2 below.In the test turn, the instruction at address θ is the command to repeat the turn 100 times at the location O1i, and the instruction at pin 10 is to repeat the turn 100 times. , (turn is an empty bin unrelated to the test. This 1o pin pattern controls the gate (30) and gate (31) in Figure 5). At address O, the clock enters the 6R gate (32) via the gate (31) and supplies the clock to the device under test. Repeat this operation and expect the output pattern of the l pin to be pattern 1.
(31) is closed and the clock supply is stopped. This operation puts the device under test into a hold state. On the other hand, since the output of pin 1 of device 2 has not yet become 1', the clock continues to be supplied. In this way, in the case of this program, the output state of pin 1 becomes "1" while repeating a maximum of 100 steps, which means that MATCH has been equivalently detected for devices under test 1 and 2.

After that, since the two devices under test perform exactly the same operation, it becomes possible to continuously apply test patterns starting from address 1 and perform simultaneous measurements. If the device under test is defective and the output state of pin 1 does not become "L", the clock will continue to be supplied for 100 steps.
Then, the process advances to the next address 1, after which a fail is detected.Next, an application example of the test method according to the present invention will be explained.

In the circuit example of this patent shown in FIG. 5, the clock supplied to the device under test is the output of the forward gate (32), and its electrical level is determined by the i-gate (32). In order to solve this problem and enable the test program to determine the high and low levels of the clock, the test equipment should be equipped with a driver as shown in Figure 7.
Just add comparator logic.

Next, in Fig. 7, (34) is a comparator ξ which determines the output level of the attached circuit on the DUT board.
35) is the level l determined by the comparator
and a driver that converts level 0 to a predetermined voltage level.

In addition, Fig. 8 (36) shows the input waveform to the comparator, (
37) is the comparator output (38) determined by the comparator determination level VTH.
This is the driver output waveform converted to H level.

〔Effect of the invention〕

This invention has the remarkable effect of making it possible to simultaneously measure a plurality of L8Is that require the MATCH mode.

[Brief explanation of drawings]

Fig. 1 is a block diagram schematically showing the L8I test equipment having two test heads, Fig. 2 is a block diagram schematically showing one pin of the test pattern dispensing section in Fig. 4 is a block diagram showing the outline of one pin of the device output comparison section of FIG.
Fig. 5 is a circuit diagram of the test method of one embodiment, Fig. 6 is a timing chart until detecting 21161 MATCH in one embodiment, Fig. 7 is a diagram showing one example of test equipment, and Fig. 8 The figure is a diagram showing voltage waveforms at various parts in FIG. 7. 13 Control unit 14 Test pattern payout unit 17.18
Test head 20 Device output comparator 30, 31' I-to 32, 33 OR gate 34 Con/signer 35 Driver 36 Input waveform 37 to the comparator
Comparator output 38 Driver output waveform agent Patent attorney I 1- Male No. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 17 (I8)

Claims (1)

[Claims] a control unit for controlling the execution of a test program; a test/signature turn output unit that converts the test/signature turn sent from the control unit into a waveform in a predetermined format and sends it out; and a test/signature turn output unit that outputs the test data turn from the output unit. A plurality of test heads convert the output from the output pin of the L8I device to a predetermined level and send it to a predetermined voltage value, and the LSI device output from the test head is compared with a reference comparison pattern. A device output comparison section that makes a judgment and sends the judgment information to the control section, and an auxiliary circuit is installed on the DUT board that associates the tester terminal of the test head with the measurement pin of the L8I to be measured by wiring.
An LSI testing method characterized in that a plurality of L8Is under test are synchronized by controlling the number of clocks applied to the L8IK under test using a match detection pin of the SI.