JPH02309818A - A/d converter - Google Patents

Abstract

PURPOSE:To ensure automatic calibration of the converter in timewise stable state by selecting a clock from an external clock generating circuit during the measuring period, selecting the clock of an internal clock generating circuit during non measuring period, frequency-dividing the clock and distributing the result to each section of the converter. CONSTITUTION:A clock control circuit 7 selects a clock ECK of an external clock generating circuit 4 during the measuring period and selects a clock ICK from an internal clock generating circuit 4 during the non measuring period, each clock is frequency-divided and distributed to an A/D converter 1 and a data memory control circuit 9 as a sample clock SCK. The A/D converter 1 converts an analog signal input A into a digital signal D according to the sample clock SCK and an output data B is stored in a data memory 8. After a prescribed quantity of data is stored, a data memory control circuit 9 controlling the data storage of the data memory 8 outputs a data storage end signal RC to the clock control circuit 7. Then an arithmetic control section (CPU) 10 controls totally each section of the converter. Thus, automatic calibration is implemented in the timewise stable state.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to an A/D conversion device, and more specifically, to an A/D conversion device to which an external clock and an internal clock are selectively applied.
The present invention relates to an improvement in automatic calibration operation of an A/D conversion device using a converter.

<Prior Art> FIG. 4 is a block diagram showing an example of a conventional A/D conversion device. In the figure, reference numeral 1 denotes an A/D converter that converts an analog signal input A into a digital signal, and the clock ECK of the external clock generation circuit 3 or the clock ECK of the internal clock generation circuit 4 is selectively applied via the changeover switch 2. Operates according to clock ICK. The output data D of the A/D converter 1 is stored in a data memory device 5. 6 is A
/D converter 1. Changeover switch 2. This is a signal processing section that centrally controls the operations of the data memory device 5 and the like, and also performs arithmetic processing and display processing.

Such a conventional A/D converter is connected to an external clock IEC.
In the case of operation at K, automatic calibration of the device is also performed according to the external clock ECK. That is, the time required for automatic calibration depends on the external clock ECK.

<Problems to be Solved by the Invention> As a result, a problem arises in that automatic calibration takes too much time if the speed of the external clock ECK is slow.

In addition, the external clock E may be interrupted for some reason during automatic calibration.
If CK stops, the device will stop in the state of automatic calibration operation.

The present invention has been made with attention to these points,
The purpose is to provide an A/D conversion device that can reliably perform automatic calibration of the device in a temporally stable state.

Means for Solving the Problems> The present invention for solving the above problems comprises: an A/D converter that converts an analog signal into a digital signal; a data memory that stores output data of the A/D converter; a data memory control circuit that controls a data memory, an internal clock generation circuit, an external clock generation circuit, and selects the clock of the external clock generation circuit during a measurement period and selects the clock of the internal clock generation circuit during a non-measurement period. The device is characterized in that it is comprised of a clock control circuit that selects, divides and distributes the frequency to each part of the device, and an arithmetic control section that centrally controls each part of the device.

Effect> As the clock of the A/D converter of the present invention, the external clock is selected only when measuring, and the internal clock is selected when not measuring.

That is, since automatic calibration is always performed using the internal clock, it can be performed reliably at a stable time.

<Example> Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and parts common to those in FIG. 4 are designated by the same reference numerals, and redundant explanation thereof will be omitted. In the figure, 7 is a clock control circuit;
During the measurement period, the clock ECK of external clock generation circuit 3
, selects the clock ICK of the internal clock generation circuit 4 during the non-measurement period, and divides each of these clocks to generate A
/D converter 1 and data memory control circuit 9 as sample clock SCK. The A/D converter 1 converts the analog signal input A into a digital signal according to the sample clock SCK. Output data D of the A/D converter 1
is stored in the data memory 8. The data storage operation of the data memory 8 is controlled by a data memory control circuit 9. When the data memory control circuit 9 stores a predetermined amount of data, it outputs a data storage completion signal RC to the clock control circuit 7. An arithmetic control unit (CPU) 10 is a unit that centrally controls each part of the device, and is connected to the A/
D converter 1. Clock control circuit 7. It is connected to the data memory 8 and the data memory control circuit 9.

FIG. 2 is a block diagram showing an example of the configuration of the clock control circuit 7. As shown in FIG. A start signal and a stop signal are applied to the clock switching unit 12 from the arithmetic unit 11 control unit 10, and a data storage end signal RC is applied from the data memory control circuit 9, so that the switch 13 is switched and driven based on these signals. A clock switching signal ECKCG is generated. The clock switching signal ECKCG is enabled when a start signal is applied from the calculation control section 10, and when a stop signal is applied from the calculation control section 10 or a data storage end signal RC is applied from the data memory control circuit 9. Disabled by The switch 13 selects the clock ECK of the external clock generation circuit 3 and applies it to the frequency divider 14 only while the clock switching signal ECKCG is enabled, and selects the clock ICK of the internal clock generation circuit 4 when it is otherwise disabled. and is added to the frequency divider 14.

The frequency divider 14 divides the clock applied via the switch 13 into a set value and outputs the divided value to each section. Note that it is assumed that the frequency division ratio of the frequency divider 14 includes l/1.

In the device configured as described above, the analog signal input A is output based on the clock ECK of the external clock generation circuit 3.
The operation when measuring will be explained with reference to the timing chart in FIG.

By applying the measurement start signal 5TART (a) from the arithmetic control unit 10 to the clock control circuit 7, the clock switching signal ECKCG (b) is enabled, and the clock applied to the frequency divider 14 is changed as shown in (d). The clock IcK of the internal clock generation circuit 4 is switched to the clock ECK of the external clock generation circuit 3.

The A/D converter 1 converts the analog signal A (
Continue A/D conversion for c). A write address (f) for writing output data D(e) of the A/D converter 1 into the data memory 8 is managed by the data memory control circuit 9. (g) is write data. The write address is set in advance from the calculation control unit 10, and the start signal 5T
After ART is input, it is counted sequentially at each falling edge of the sample clock SCK. Then, when the number of data reaches a preset number, a data storage end signal RC(h) is output from the data memory control circuit 9 to the clock control circuit 7.

As a result, the clock switching signal IECKCG is disabled, and the clock applied to the frequency divider 14 is switched from the clock ECK of the external clock generation circuit 3 to the clock IcK of the internal clock generation circuit 4. Thereafter, this state is maintained until a new Jl determination of the analog signal A is started. That is, the clock ECK of the external clock generation circuit 3 is selected only during the measurement operation.

When measuring the analog signal A based on the clock ICK of the internal clock generation circuit 4, the clock switching signal ECKCG is masked by the settings from the arithmetic control unit 10, and the clock IcK of the internal clock generation circuit 4 is always used.
remains selected.

During automatic calibration, there are some changes such as grounding the input of the A/D converter 1, but basically the analog signal A is based on the clock IcK of the internal clock generation circuit 4.
The measurements are carried out in the same sequence as the previous measurements.

<Effect of the invention> With this configuration, n of analog signal input
Since the clock of the external clock generation circuit is selected only at one fixed time and the clock of the internal clock generation circuit is selected in other states including automatic calibration, automatic calibration is performed at a fixed time determined by the internal clock. Compared to the conventional case where an external clock is selected for automatic calibration, automatic calibration can be performed in a more stable state both in terms of time and in terms of time.

Furthermore, the internal clock transmission system has fewer factors that can cause interruptions than the external clock transmission system, and the risk of the operation stopping during automatic calibration is greatly reduced.

As described in detail above, according to the present invention, it is possible to provide an A/D conversion device that can reliably perform automatic calibration of the device in a temporally stable state.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
Block diagram illustrating a specific example of the clock control circuit shown in Figure 3.
The figure is a timing chart explaining the operation of figure 1, and figure 4.
The figure is a block diagram showing an example of a conventional device. 1...-A/D converter 3...External clock generation circuit 4...Internal clock generation circuit 7...Clock control circuit 8...Data memory 9...Data memory control circuit 1o... Arithmetic control unit, 11... System bus 12... Clock switching unit 13... Switch 1
4... Frequency divider Figure 2

Claims (1)

[Claims] An A/D converter that converts an analog signal into a digital signal; a data memory that stores output data of the A/D converter; a data memory control circuit that controls the data memory; a clock generation circuit; and an external clock generation circuit; during a measurement period, the clock of the external clock generation circuit is selected, and during a non-measurement period, the clock of the internal clock generation circuit is selected, frequency-divided, and distributed to each part of the device. 1. An A/D conversion device comprising: a clock control circuit that controls various parts of the device; and an arithmetic control section that centrally controls each part of the device.