JP3057538B2 - LSI tester - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI in which an analog circuit and a digital circuit are mixed (a device under test: a DUT).
More specifically, the present invention relates to an LSI tester that measures the effective use of a pattern memory of each module that outputs a digital signal and an analog signal in synchronization with a module that outputs a digital pattern.

[0002]

2. Description of the Related Art A test of a DUT in which an analog circuit and a digital circuit are mixed is required to be performed in an actual operation state of the DUT, that is, a test in which an analog unit and a digital unit are integrated and the whole is handled as a system. It is. For this purpose, a digital function module (hereinafter abbreviated as DFC module) for outputting a digital pattern to the DUT and a mixed signal unit (hereinafter abbreviated as MS unit) for outputting a digital signal and an analog signal are synchronized. You need to control. In a general LSI tester, since different modules are distributedly controlled by different controllers so that a DUT test can be performed at a high speed, the DFC module and the MS unit are synchronized based on a code signal.

[0003]

SUMMARY OF THE INVENTION Such a conventional LS
Since the I tester cannot control the modules operating synchronously in association with each test rate, for example, even if the digital pattern and the analog signal are output alternately, the pattern memory of each module is always In the used state, a large storage capacity is required for the pattern memory, and the effective use of the memory has not been attempted.

[0004] The present invention has been made in view of the above points, and is intended to control each module synchronized by a code signal in association with each test rate, thereby reducing the consumption of pattern memory. It is an object of the present invention to provide an LSI tester capable of reducing the number of test waveforms arbitrarily by using a memory having a small storage capacity.

[0005]

According to the present invention, an analog signal and a digital signal to be output to an object to be measured are generated for each module and input from the object to be measured. It has a mixed signal unit that analyzes analog and digital signals for each module, and a digital function module that sends and receives digital pattern signals to and from the device under test. In the LSI tester for inspecting an object to be measured, a code signal synchronized with a signal generation side of the mixed signal unit is sequenced based on an address output from an address generation sequencer of the digital function module. Code memory to output to the generator A state in which the sequence generation circuit performs count control of an address output to an address counter based on the code signal, and outputs a status signal for controlling data output from a pattern memory based on an address specified by the address counter. A memory is provided to synchronize the modules by the code signal, and controls the digital function module and the mixed signal unit in association with each other at each test rate by the status signal.

[0006]

The components of the present invention have the following functions. The code memory outputs a code for synchronization to the sequence generation circuit of the MS unit based on the address specified by the address generation sequencer of the DFC module.
The state memory controls the count of the address output to the address counter by the sequence generation circuit of the MS unit, and controls the data output from the pattern memory based on the address specified by the address counter.

[0007]

An embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a configuration block diagram of an LSI tester showing one embodiment of the present invention. Note that the module that outputs an analog signal in the MS unit is configured by simply adding a DA converter to a digital signal source module (hereinafter abbreviated as a DSS module) that outputs a digital signal. Will be described as a representative. In the figure, 1 is a test system controller that controls the entire system, 2 is a module controller that controls a digital function module 20 (hereinafter, DFC module 20), and 3 is a D
A module controller that controls the SS module 30.

The test system controller 1 loads the object file obtained by compiling the test program into the module controllers 2 and 3, specifies the loaded object file in accordance with the sequence number, and sets the DFC through the module controllers 2 and 3.
The module 20 and the DSS module 30 are controlled.

In the DFC module 20, a microcode memory 21 stores, for example, microcodes which are instructions for operation processes such as no operation (hereinafter, NOP) and jump (hereinafter, JUMP). 22 is a digital pattern memory, be stored digital patterns for testing the DUT 40, and outputs a digital pattern D _i a (i = 1 to n) in the DUT 40 based on the address of the address generation sequencer 23 has specified.

Reference numeral 24 denotes a code memory which outputs a code signal S ₁ synchronized with the DFC module 20 to the DSS module 30 based on the address output from the address generation sequencer 23. Reference numeral 25 denotes a state memory, which has a DF based on the address output from the address generation sequencer 23.
The status signal S ₂ for controlling the operation of the C module 20 for each test rate is output to the DSS module 30.

In the DSS module 30, reference numeral 31 denotes a sequence generation circuit which outputs a start address to an address generation counter 32 based on a code signal S ₁ output from a code memory 24. Address generation counter 32
Is the clock CK ₂ input from the AND gate 32 ₁ and the start address input from the sequence generation circuit 31.
And outputs it to the pattern memory 33.

The AND gate 32 ₁ has one input terminal to which the clock CK ₁ is input and the other input terminal to which the status ST ₀ is input from the state memory, and opens the gate when the status ST ₀ becomes high level. .

The pattern memory 33 outputs the stored digital data DA _i (i = 1 to n) to the D-type flip-flop 34 based on the address specified by the address generation counter 32. D-type flip-flop 3
4 holds based on the clock signal CK ₃ inputted digital data DA _i to be inputted to the D terminal to the clock terminal, from the Q terminal as a digital signal DA _i DUT 40
Output to

Reference numeral 34 ₁ denotes an AND gate. The clock CK ₃ is input to one input terminal, and the status ST ₁ is input from the state memory 25 to the other input terminal.
Status ST ₁ the gate is opened and becomes a high level. When the reset signal S ₃ from the AND gate 34 ₁ is input, D flip-flop 34 is reset, D
The data of the type flip-flop 34 is not output to the DUT 40.

The clock signals CK _{1 and} CK ₃ are signals obtained by delaying the clock signal CK ₀ and taking into account the time from the output of the microcode to the operation of the address generation counter 32 and the D-type flip-flop. Is set.

FIGS. 2A and 2B are time charts for explaining the operation of the LSI tester of the present invention. FIG. 2A shows the microcode output from the microcode memory, FIG. 2B shows the address output from the address generation sequencer, and FIG. code signals S ₁ code memory is output, (D) the status ST ₀ the state memory is output, (E) the status ST ₁ the state memory is output, (F) is a digital pattern D _i to the digital pattern memory outputs , (G) is DFC
Clocks CK ₀ and (H) for synchronizing modules are AN
The clock CK ₁ input to the D gate, (I) is the clock CK ₂ input to the address generation counter, (J) is the address output from the address counter, and (K) is DSS.
Digital data DA _i output from the pattern memory of
(L) is a clock CK _3, (M) is a reset signal S ₃ which is input to the D-type flip-flop, (N) is a digital signal DA _i outputted from the D-type flip-flop.

(1) The microcode memory 21
CK signal₀NOP instruction at the first rising edge of
Output to the sequence generator 23. (2) The address generation sequencer 23
The address “1” is decoded based on the NOP instruction of the memory 21.
Output to the digital pattern memory 22 and code
Output to the memory 24 and the state memory 25. (3) The digital pattern memory 22 stores the address generation sequence.
Based on the address “1” specified by the
, Digital pattern D₁Is output to the DUT 40. one
On the other hand, the code memory 24 stores a synchronization signal at address "1".
Is a code signal S ₁Not output to DSS module
Therefore, the DSS module 20 is not synchronized.

[0018] (4) microcode memory 21, in the second rising edge of the clock signal CK _0, and outputs a NOP instruction address generation sequencer 23 again. (5) The address generation sequencer 23 outputs the address “2” to the digital pattern memory 22 and the code memory 24 and the state memory 25 based on the NOP instruction of the microcode memory 21. (6) The digital pattern memory 22 outputs the digital pattern D ₂ based on the address “2” specified by the address generation sequencer 23 to the DUT 40, and
4 outputs the code # 1 based on the address specified by the address generation sequencer 23 to the sequence generation circuit 31 of the DSS module 30. The state memory 25 outputs a status signal S ₂ based on the specified address of the address generation sequencer 23. In this case, the status ST ₀ “1” is output to the AND gate 32 ₁ , and the status ST ₁ “0” is output to the AND gate 34 ₁ .

(7) Status ST₀"1" is an AND gate
32₁Is output to the AND gate 32₁Is the gate
Is opened and the clock terminal of the address generation counter 32 is closed.
Lock CK_TwoIs output. (8) The address generation counter 32 is an AND gate 32₁Or
Clock CK input from _TwoThe sequencer generation circuit
31 is the start address output based on code # 1
Is output to the pattern memory 33. In this case, the star
The address "10" is output. (9) The pattern memory 33 stores the address generation counter 32
When the address "10" is specified by
DA₁To the D-type flip-flop 34. (10) The D-type flip-flop 34 is connected to the clock terminal
Clock CK input to_ThreeBased on the digital signal D
A₁Is output to the DUT 40.

[0020] (11) Next, the microcode 21 outputs a NOP instruction to the address generation sequencer 23 in the third rising edge of the clock CK _0, to start the next cycle. (12) Address generation sequencer 23, based on the NOP instructions in microcode memory 21, and outputs an address "3" in the digital pattern memory 22, a digital pattern memory 22 outputs a digital pattern D ₃ to DUT 40. (13) On the other hand, the address generation counter 32 outputs the address “11” counted up by the clock of the AND gate 32 ₁ to the pattern memory 33.

(14) The pattern memory 33 outputs the digital data DA ₂ at the address “11” designated by the address generation counter 32 to the D flip-flop 34. (15) The D-type flip-flop 34 is
The digital data DA ₂ input and output to the DUT40 based on the clock CK ₃ inputted to the clock terminal from. (16) Output address of the address generation sequencer 23 becomes "4", the status ST ₀ is "0", the address generating counter 32 stops counting up, the pattern memory 34 while the address "11" Is no longer incremented.

[0022] (17) output address of the address generation sequencer 23 becomes "5", when the status ST ₁ becomes "1", D-type flip-flop 34, the AND
Reset by the reset signal S ₃ of the gate 34 ₁ ,
Data is no longer output to the DUT 40. (18) As described above, the DSS module 30 is controlled by the status signal S of the state memory 25 in relation to the DFC module 20 for each test rate, and outputs a digital signal from the D-type flip-flop 34 to the DUT 40. FIG. 3 is a diagram showing the contents of the pattern memory 33 when the operation described in FIG. 2 is performed. Conventional LSI
The tester needs data for each test rate, and needs to write digital data to the pattern memory in the order of addresses as shown in FIG.

[0023]

As described in detail above, the LS of the present invention
The I tester controls the DSS module synchronized with the code signal at each test rate by the status signal, so that the consumption of the pattern memory can be reduced. Can be obtained arbitrarily.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an LSI tester showing an embodiment of the present invention.

FIG. 2 is a time chart for explaining the operation of the LSI tester of the present invention.

FIG. 3 is a diagram showing the contents of a pattern memory when the operation described in FIG. 2 is performed.

FIG. 4 is a diagram showing the contents of a pattern memory of a conventional LSI tester.

[Explanation of symbols]

20 DFC module 24 Code memory 25 State memory 32 ₁ , 34 ₁ AND gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (1)

(57) [Claims] 1. A mixed signal unit for generating an analog signal and a digital signal to be output to an object to be measured for each module and analyzing an analog signal and a digital signal input from the object to be measured for each module. A digital function module for transmitting and receiving a digital pattern signal to and from the object to be measured; and A code memory for outputting a code signal synchronized with a signal generation side of the mixed signal unit to a sequence generation circuit of the mixed signal unit based on an address output from the generation sequencer; and generating the sequence based on the code signal. Circuit is address A state memory for controlling the count of the address output to the counter and outputting a status signal for controlling data output from the pattern memory based on the address specified by the address counter; and An LSI tester which synchronizes the digital function module and the mixed signal unit with each other at each test rate according to the status signal.