JPH01248219A - Bus timing control circuit - Google Patents

Abstract

PURPOSE:To allow an input/output card operated by an input/output clock being different from a CPU clock to coexist by the same system by synchronizing a selected clock and the CPU clock. CONSTITUTION:When it is recognized that a card of an extended slot is brought to access, one of READY input signals A-C becomes inactive, and by which clock it is operated is informed to a system board. By a fall of its READY input signals A-C, the clock which is selected through a gate is outputted as an input/output clock to an extended bus. Also, the READY signal sets an MPU to WAIT state, the card of the extended slot secures a set-up time and makes the READY signal active, and the selected clock and a CPU clock are synchronized. That is, flip-flops 60, 70 contrive the synchronization of an input/output clock (I/O CLK) and the CPUCLK. In such a way, the card which is designed by a flow or quick input/output clock can be allowed to coexist on the same system.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention provides an expansion connector to optionally mount a card for a specific purpose. The present invention relates to a bus timing control circuit.

(Prior art) The basic timing of the pass cycle of a microprocessor (MPU) is determined by the MPU, and in order to extend this pass cycle, the READY signal is
It is often caused by setting it to Actlve. This is called a wait state, and depending on the MPU, the WAIT signal is activated.
There are also expressions such as "to do". This READY
In principle, the (or WAIT) signal must be input in synchronization with the MPU's basic clock, and normally control is performed such that it is active for n clock times 1n with respect to the MPU clock and the pass cycle is extended by n clocks and 22 minutes. conduct.

(Problems to be Solved by the Invention) By the way, the above control causes the following problems along with the performance improvement (speeding up) of the MPH. That is, personal computers (PCs), workstations (W
In case of S), an expansion connector may be prepared and a card for special use may be prepared as an option. For example, if a card is designed with an MPU clock of 6 MHz (megahertz), then the MPU of a PC or ws' is designed with 10 MHz.
MHz, this card will support these new P
This means that it cannot be used with C or Ws. Conventionally, in order to operate these cards, the MPU clock was adjusted to the speed of the card (6 MHz in this case).
) is controlled so that it can be dropped. However, this method has the drawback of slowing down speeds other than pass cycles. Furthermore, in order to operate a slower card, a card that can operate at the MPU speed (10 MHz) also has to operate at a slower timing.

The present invention has been made in view of the above drawbacks.
An object of the present invention is to provide a path timing control circuit that allows input/output cards that operate with an input/output clock different from the clock to coexist in the same system.

[Structure of the Invention] (Measures to Solve the Problem) In order to achieve the above object, the present invention assigns a plurality of READY input bins to an expansion connector, and
By assigning different clocks to the DY input, it is possible to operate at different timings depending on whether the optional input/output card selects the READY signal. For this purpose, the path timing control circuit has multiple R
An expansion slot to which an EADY input terminal is assigned and a different clock assigned to each, and the above-mentioned READ
A first flip-flop 70 that is set by a signal being supplied to the Y input terminal, a gate circuit that selectively outputs any one of the plurality of clocks selected by this flip-flop, and the above-mentioned selection. The above RE with the clock
It consists of a second flip-flop that detects the end of the ADY input, and a third flip-flop that synchronizes the selected clock with the CPU clock.

(Operation) In the above configuration, when it is recognized that the card in the expansion slot is being accessed, one of the READY input signals is made inactive, and the system board is notified of which clock to operate on.

At the falling edge of the READY input signal, the clock selected via the gate is output to the expansion path as an input/output clock. Also, the READY signal sets MP[J to the WAIT state. The card in the expansion slot secures setup time and activates the READY signal to synchronize the selected card and the CPU clock.

This allows cards designed with slow or fast input/output clocks to coexist on the same system.

(Example) Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 11 to 13 are flip-flops.

Flip 70 input signals 11 to 13 are input signals RDY-A,
It is set by each rising edge of RDY-B and RDY-C, and supplies its Q output to one input terminal of AND gates 21, 22, and 23.

8 MHz T 6 MHz r 4 M to the other input terminals of y'-to 2x, 22, and 23, respectively.
A Hz clock is supplied. ANDGATE 21.22
．． The output of 23 becomes an input clock via an OR gate 30. A clock is selected by these gate groups 21, 22, 23, and 30. 50, 60.70 are flip-flops. Flip 70 knob 5° is input signal RDY
- Detects the end of A, RDY-B, RDY-C, and sends the Q output to Nando y-to 8o, flip-flora fe
o's D input terminal. flip flop 60 and 7
0 is input/output clock (Ilo CLK) and CPUCL
Try to synchronize K. NOR gate 80 is a gate that generates the RDY signal input to the CPU.

Ilo CLK is a clock that generates extended path timing.

FIG. 2 is a timing chart showing the operation of the embodiment of the present invention, and (a) is a timing chart showing the operation of the embodiment of the present invention.
(b) shows a timing chart showing a command cycle when no RDY-B signal is input.

Hereinafter, the operation of the embodiment of the present invention will be explained in detail. In this example, the CPU is a 32-bit microprocessor 180386 manufactured by Intel Corporation in the United States.
3 pins (RDY-A) as ADY input.

RDY-B, RDY-C) are assigned to the expansion connector. When an address signal (not shown) is output to the expansion bus together with ADS÷, the card in the expansion slot decodes the address and recognizes that it is being accessed. For this reason, RDY-A.

By making either RDY-B or RDY-C inactive (Low level), the system board is notified of which clock to operate on.

The timing chart shown in FIG. 2(b) is an example of operation with RDY-B inactive. When 9RDY-B becomes inactive, the clip-flop 12 is set at the falling edge. With this, 9ANIll” -12
2,0Rr-to 30F) 6 MHz R ay R I
It is output to the expansion bus as lo CLK. RDY-B
The signal is also NAND gate 4 o, N0Rf -)
The RDY signal input to the CPU through 80 is made inactive to maintain the CPU f walt state.

Note that the ADS+ signal sets the clip-flop 70 to make the RDY signal inactive first.

The card in the expansion slot is determined at the rising edge of Ilo CLK, secures the next setup time, and makes RDY-B active (H1gh level). Now Nantes Gate 4
When the output of the clip flop 5Q becomes a low level, the output of the clip flop 5Q becomes a low level at the rising edge of I10 CLK.

Slip flops 6o and 70 are for synchronizing with the CPU clock, and are flip flops fs.

When the output becomes Low level, the output of the clip-flop 7Q becomes "Low" level due to the two CPU CLKs. If the RDY signal of N0Rr-to80 is not at "Low" level, the 9 CPU's wa
The it state is released. The output of the clip flop 7o also resets the flip flop 2,50.60. Similarly, if the card in the expansion slot makes RDY-A inactive, Ilo CLK is output to the expansion bus at 8 MHz, and if all RDY-C is inactive, Ilo CLK is output to the expansion bus and operates as a clock for releasing RDY.

The timing chart shown in Figure 2 (,) is for RDY-A.
.

This shows the timing when neither RDY-B nor RDY-C is made inactive. At this time, the output of the NAND date 40 and the output of the flip-flop 50 remain "Low", so the flip-flops feo and 70 are set at ADS+ and the output of the clip-flop 7 is set.
When the RD and signal are inactive due to the output of 0, C
The PU is put in a wait state, but the flip-flop 7 is reset by the two CPU clocks, so the CPUCL
The RDY output is determined only by the timing of K. Only a wait for one step is inserted for the CPH.

[Effects of the Invention] As explained above, according to the present invention, the following effects can be obtained.

(1) An optional expansion card can select the clock that it can operate on.

(2) Even if the CPU speed of the system date becomes faster, the optional expansion card can operate with the old slower clock.

(3) Systems that can accommodate multiple expansion cards do not need to operate in accordance with a slow clock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the embodiment of the present invention. 11.12,13,50.60.70...Flip 7
0 Tsubu, 21, 22. 23... and date, 30.
...Orgate, 4o...Nando date, 80...
Orgate. Patent attorney representing applicant Takehiko Suzue ■T11T21T21T] IT21T21(a)

Claims (1)

[Claims] an expansion slot to which a plurality of READY input terminals are assigned and different clocks are assigned to each; a first flip-flop that is set by a signal being supplied to the READY input terminal; and a first flip-flop that is selected by this flip-flop. a gate circuit that selects and outputs one of the plurality of clocks; a second flip-flop that detects the end of the READY input using the selected clock; and a gate circuit that synchronizes the selected clock and the CPU clock. A bus timing control circuit comprising: a third flip-flop that performs timing control.