GB2189890A - A unit for testing digital telecommunications exchange equipment - Google Patents

Abstract

The test unit comprises a master processor, and a slave processor SPROG for generating in accordance with instructions from the master processor, and a slave processor S PROC for generating in accordance with instructions from the master processor, a microcode pertaining to the test to be carried out. The microcode is loaded into an array of sequencer units at equipment ports. The sequencer units return a result to the slave processor for despatch to, and evaluation by the master processor. <IMAGE>

Description

SPECIFICATION A unit for testing digital telecommunications exchange equipment The present invention relates to a test unit for use with digital telecommunications exchange equipment; in particular a digital switching subsystem.

Use is made of an integrated test system for testing various modules of the digital switching subsystem. The test system consists of an array of interacting real-time processors which are configured under microcode control to handle all the different interface port characteristics required. The digital switching subsystem is of modular construction and comprises a number of equipped shelf groups. To test a group requires a pattern of signals corresponding to its interface to be sent to it and compared with signals expected to be received.

The test unit according to the invention has a wider application than just being employed in the testing of digital switching subsystems because its design permits it to be reconfigurable and is therefore, not limited to the use in testing such systems.

Accordingly, an aim of the present invention is to provide a test unit having a slave processor for generating in accordance with instructions from the master processor, the microcode necessary to test a particular interface and load it into the array of interacting real-time processors in an appropriate manner to execute the required tests. The test results are then read back from the array to the processor.

According to the present invention there is provided a test unit for testing digital telecommunications exchange equipment wherein the test unit comprises a master processor, and a slave processor for generating in accordance with instructions from the master processor, a microcode pertaining to the test to be carried out, means for loading the microcode into an array of sequencer units which operate upon the microcode to generate a test to be executed by the sequencer units at equipment ports, and to provide a result which is returned to the slave processor for despatch to, and evaluation by the master processor.

An embodiment of the present invention will now be described with reference to the accompanying drawings wherein: Figure I depicts block diagram of a test unit including a number of sequencer units connected in hierarchical form, Figures 2a and 2b, when Fig. 2b is placed to the right of Fig. 2a, depict a block diagram of a waveform sequencer, Figure 3a, 3b and 3c, when Fig. 3b is placed to the right of Fig. 3a and Fig. 3c is placed to the right of Fig. 3b, depict a block diagram of a message sequencer, Figures 4a and 4b, when Fig. 4b is placed to the right of Fig. 4a depict a block diagram of a bit sequencer, Figure 5 depicts a block diagram of an 10 microinstruction unit, Figure 6a and 6b, when Fig. 6b is placed to the right of Fig. 6b, depict a block diagram of a sequencer unit, Figure 7a, 7b, 7c and 7d when Fig. 7b is placed to the right of Fig. 7a, Fig. 7c is placed to the right of Fig. 7b and Fig. 7d is placed to the right of Fig. 7c, depict a circuit diagram of a sequencer unit, Figure 8 depicts a timing diagram relating to the changeover from the program to the run mode, Figure 9 depicts a timing diagram relating to the changeover from the run to the program mode, Figure 10 depicts a timing diagram for a program mode read operation; and, Figure 11 depicts a timing diagram for a program mode write operation.

The test unit is composed of a slave processor, S.PROC, a waveform sequencer WS, a number of message sequencers MS and a number of bit sequencers BS connected in hierarchical form to the slave processor S.PROC as shown in Fig. 1. The equipped shelf group ports ESGP are connected to bit sequencers BS which are controlled through a system of communication flags by the message sequencers MS, which can also send flags to each other.

The message sequencers MS are controlled by the slave processor S.PROC. The whole system is clocked by the waveform sequencer WS. When a test is running, (run mode) bit patterns are passed to and from the equipped shelf group ports ESGP by the bit sequencers BS.

The operation of all sequencers is placed under the control of micro-programs which are downloaded from the slave processor S.PROC and which configure the sequencers to simulate any interface desired by the programmer. When a test is not running, the system comes under the control of the slave processor S.PROC for loading microcode and reading-up results. In this state, known as program mode, the waveform and message sequencers WS, MS communicate directly with the processor through a system bus. The bit sequencers BS, however, remain under the control of their message sequencer MS, which thus has the additional function of passing input/output information between the system bus and the bit sequencers BS.

The waveform sequencer provides clock and synchronisation waveforms. The waveform sequencer is a generator in which some waveforms are programmable sequences which are downloaded and controlled by communication over a bus system interface, while other waveforms are fixed in frequency and phase. Some programmable waveforms are produced using a sequencer unit circuit which generates patterns with a time resolution of one 4096kHz period per bit.

Three RAM areas can be accessed by system bus communication.

a. The waveform sequencer selection register allows or inhibits system bus communication with the other RAM areas.

b. The control register controls the waveform sequencer's operational modes and waveforms, and stores fault indications.

c. The microprogram memory within the sequencer unit stores the waveform sequencers and sequencer unit control information (micro-instructions).

The waveform sequencer has two operational modes, PROG and RUN. In PROG mode all three RAM areas may be accessed via the system bus so that sequences and control parameters may be loaded and fault indications interrogated. In RUN mode, access to the microprogram memory via the system bus is barred because the sequencer unit during RUN mode is dependant on the program in the microprogram memory and on the state of incoming flag signals from other circuits connected to the waveform sequencer.

The waveform sequencer has its own crystal controlled clock reference which may be inhibited permitting the use of an external clock as the reference source. This allows the waveform sequencer to work as a master slave sequencer which respectively provides or accepts clock, sync and PROG/RUN signals.

Referring to Figs. 2a and 2b, the block diagram of the waveform sequencer is shown together with the distribution of signals between ports and between blocks.

Two techniques are used to generate waveforms. One method is to divide a high frequency reference into lower frequency clocks and the other method is to generate waveforms from stored data. The first method is adopted by a clock generation circuit CG which is primarily concerned with generating clocks of fixed phase and frequency to various other blocks and to port 2. The second method of waveform generation is used by the sequencer unit SU which constructs a digital waveform from data stored in the microprogram memory. The advantage of the second method is that the waveform can be altered by downloading new data into the microprogram memory via the system bus interface during PROG mode.

Clock Generation Circuit, CG.

The waveform sequencer is required to produce a 16384kHz clock which is either derived from a clock reference in the waveform sequencer or derived from an incoming 2048kHz reference clock at port 4. Frequency multiplication is required to produce a 16384kHz clock from a 2048kHz clock, so an adoption of the standard frequency synthesiser operating at 32768kHz is used with a binary counter circuit to produce several signals. For frequency stability the reference clock on the waveform sequencer uses a crystal oscillator for its source. The phase locked loop section of the frequency synthesiser indicates whether the loop is in lock or not. It is possible to force the loop out of lock in order to prove that the indication is working correctly. This also disrupts all outgoing clocks and waveforms from the waveform sequencer.

The clock signals from the counter are retimed by bistables and registers, to produce additional clock phases for other blocks and for port 2.

System Bus Interface and Control Circuit, SBI.

The main function of the system bus interface and control circuit is to interface the waveform sequencer with other circuits on the system bus and use the information supplied across the system bus to generate control signals to various circuits. The system bus interface and control circuit generates a power-on reset which puts the waveform sequencer into PROG mode, and also produces an initialisation signal to other circuits when an initialisation signal is received on the system bus.

The system bus interface and control circuit contains a waveform sequencer selection register and the control register.

Waveform Sequencer Selection Register.

Before the other registers can be accessed via the system bus the waveform sequencer selection register must be written to so that the waveform sequencer is selected.

Control Register.

The control register is made up of a single sixteen bit wide write only section and a two bit wide read only section.

The write only section controls fixed functions: a. It selects clock phases generated in the waveform triad generation circuit WTG by means of the CLOCK SELECT group of signals.

b. It enables/disables frame syncs in circuit WTG by means of the FRAME SYNC ENABLE group of signals.

c. It controls the break and restoration of the loop in the phase locked loop section of clock generation circuit CG.

d. It controls the waveform sequencers operational modes PROG and RUN.

e. It controls a PROG/RUN signal to the sequencer unit SU and to the slave tester control circuit STC.

The read only section indicates the state of the system bus interrupts INT2 and INT4.

Interrupt lNT2 is generated by the clock generation circuit CG and indicates whether the phase locked loop is in or out of lock. Interrupt INT4 is generated externally.

Sequencer Unit, SU.

This is an adoption of the standard sequencer unit which will be described in detail later.

The waveform sequencer uses four flag inputs, two of which are used with signals external to the waveform sequencer, and two are generated by circuit SBI. The way in which the flag unit signals are used is determined by the function of the sequencer unit and the program downloaded into the microprogram memory.

The sequencer unit in the waveform sequencer provides output flag signals two of which are for use at port 3. The form of these signals are determined by the function of the sequencer unit and the program downloaded into the microprogram memory.

Wave forms Triad Generation Circuit, WTG.

Using clock signals from the clock generation circuit CG seven phases of 2048kHz clocks, which may be selected or inhibited by a CLOCK SELECT from the control register in circuit SBI, are generated. There are three individually selectable transformer coupled balanced line clock outputs and three transformer coupled balanced line frame reset outputs. Each frame reset may be enabled or disabled separately using FRAME SYNC ENABLE signals from the control register in circuit SBI. The frame sync signals originate in the sequencer unit SU and depend upon the program downloaded to the microprogram memory.

Slave Tester Control Circuit, STC.

If the waveform sequencer is set up as a slave it will accept TTL balanced line clock, sync and PROG/RUN signals at port 4. Slave operation is invoked by the SLAVE SELECT signal at port 4 which causes incoming sync and PROG/RUN signals to be sent to the sequencer unit block and a reference clock to be sent to clock generation circuit CG. The slave select signal is also sent to the clock generation circuit CG to disable the waveform sequencer 2048kHz reference clock.

Regardless of whether the waveform sequencer is operating as a master or slave it provides port 4 with a 2048 kHz clock signal from the clock generation circuit CG. It also provides port 4 with a programmable waveform from the sequencer unit SU and a PROG/RUN indication from circuit SBI associated with a particular bit of the control register. All these output signals are TTL balanced lines which are high impedance during power-up initialisation and during an initialisation signal from circuit SBI.

Signal description of clock generation circuit CG.

Unless specified all signals are single TTL signals.

4MlLR Clocks.

A group of five 4096kHz TTL clock signals are provided at port 2.

16MOLT Clocks.

A group of five 16384kHz TTL clock signals are provided at port 2.

WMRNNPGH.

A PROG/RUN signal at port 2 is provided which is TTL high to indicate RUN and low to indicate PROG. This signal is similar to signal TURNIPH from circuit SBI but is retimed to a rising edge of signal 32MEG.

REF2MCKR.

A 2048kHz clock signal supplied to the slave tester control circuit, STC for subsequent transmission at port 4.

INT2.

An interrupt signal to the system bus is provided at port 1 and the control register in the circuit SBI. TTL low indicates that the phase locked loop is out of lock.

TTL high indicates that the phased locked loop is in lock.

2MOR.

A 2048kHz clock signal supplied to circuit SBI and the waveforms triad generation circuit, WTG.

CK I GMOLR.

A 16384kHz clock signal with phase 16MOLR is supplied to circuit SBI and circuit WTG.

32 MEG.

A 32768kHz clock signal with phase of 32M is supplied to circuit WTG.

CLK4MOR.

A 4096kHz clock of 4MOR phase is supplied to the sequencer unit, SU.

CLK4M 7R.

A 4096kHz clock of 4M1R phase supplied to the sequencer unit, SU.

PRGHRUNL.

A PROG/RUN signal is supplied to the sequencer unit, SU. TTL high indicates PROG, TTL low indicates RUN. This signal is similar to signal WFSRUNL from circuit SBI but is retimed to a rising edge of signal 32MEG.

Circuit description.

Clock reference and counter.

The clock reference is generated on the waveform sequencer by circuit CG, and is a 2048kHz clock of 2M4R phase. It is produced by a 4.096MHz crystal oscillator device and a D-type flipflop, which divides the clock by two. When the signal SLAVSELL is high, the signal EXTCLKR is also high and the 2048kHz clock signal passes through to a phase detector. When the signal SLAVSELL is low the D-type flip-flop is set so that its 0 output is high. This disables the clock reference and permits the signal EXTCLKR to pass to the phase detector so that the frequency synthesiser is supplied with an external clock.

When the signal BRKLOOPH is low the counter is continuously reset thus breaking the loop in the phase lock loop.

Loop detect.

When the phase lock loop is in lock the output of the phase detector is TTL high with extremely short duration low pulses which represent the error signal used to maintain lock.

When out of lock the output is a signal with equal mark and space, which is filtered and presents a d.c. component to a voltage comparator, which produces signal lNT2 for port 1 and circuit SBI. This signal is low when the loop is out of lock. Fixed phase clocks and retiming of PROG/RUN signals.

A A further D-type flip-flop is provided in circuit CG, and uses clocks 4M2R and 16MOLR generated from the counter to produce a clock signal 4MOLR which is retimed by a first octal bistable using clock signal 32MEG to produce clock signal 4M1R. This phase is retimed by a second octal bistable using signal 32MEG to produce six outputs of signal 4M1LR, five of which are at port 2, and the sixth CLK41LR is used to generate clocks for the sequencer unit, SU.

The second octal bistable retimes signal 1 6MOLR using signal 16MOR. The first octal bistable then retimes signal 16MOR using signal 32MEG tó produce six outputs of signal i6MOLR, five of which are at port 2 and the sixth is signal Cl < 16MOLR used to generate sequencer unit clocks which are supplied to circuits SBI and WGT. Signal 16MOLR is reproduced by retiming so a large fan out is achieved while skews between these clocks and other signals are minimised.

The second octal distable retimes signal WFSRUNL using signal 32MEG to produce signal PRGHRUNL for the sequencer unit SU, and the first octal bistable retimes signal TURNIPH using signal 32MEG to produce signal WMRNNPGH at port 2.

Sequencer unit clocks.

Signal CLK4M1LR and C16MOR are used by a shift register to produce two clock signals, CLK4MOR and CLK4M1R which are used by the sequencer unit, SU. This shift register is used so that the timing skews of the sequencer unit output signals matches the skews of other sequencer units in other sequencers.

System Bus Interface and Control Circuit, SBI.

Signal description.

DATA.

A group of sixteen three-state, bidirectional lines are connected to port 1 and to the sequencer unit SU.

XACK.

A three-state bus system signal is connected to port 1.

BRKLOOPH.

An output of the control register is connected to the clock generation circuit CG. TTL high indicates the phase locked loop is broken, and a low permits the loop to lock.

TURNIPH.

This signal is the PROG/RUN indication associated with the signal MESSRUNL from the sequencer unit SU and is masked by a bit of the control register. TTL high indicates PROG and low indicates RUN.

WFSRUNL.

This signal is a PROG/RUN indication associated with the masking bit of the control register that is delayed and retimed to signal 2MOR. TTL high indicates PROG, and low indicates RUN.

BINITL.

This signal is an initialisation signal to the sequencer unit, SU and the slave test control, STC to set the circuit into a known state. TTL low initialises the circuit.

MSBSRUNL.

This signal is a PROG/RUN indication to the sequencer unit, SU and the slave tester control circuit, STC associated with signal WFSRUNL, and another bit of the control register.

TBO.

This signal is a retimed version of signal TBSO from the slave tester control circuit, STC. This signal is a flag to the sequencer unit, SU.

CLOCK SELECT.

This is a group of nine signals to the waveforms triad generation circuit, WTG to select clocks.

FRAME SYNC ENABLES.

This is a group of three signals to circuit WTG to enable frame syncs. TTL high enables the frame syncs, a low disables them.

READL.

This is a read signal to the microprogram memory of the sequencer unit, SU. TTL low invokes the read operation.

INTENABH.

This is an enable signal to the sequencer unit, SU which permits the assertion of the output flag INT3 to port 1.

WRITEL.

This is a write signal to the microprogram memory of the sequencer unit, SU. TTL low invokes the write operation.

SRAMENL.

This is a signal which enables the RAM area of the microprogram memory in the sequencer unit, SU. TTL low enables the RAM.

SRAMSELL.

This is a signal which enables the output of transceivers in the microprogram memory of the sequencer unit, SU.

MADBUS.

This is a group of twelve bidirectional three-state address signals which form the microinstruction/address highway of the sequencer unit, SU.

Circuit description.

Address and control signal buffers.

The sequencer unit, SU requires that TTL low address signals represent a logical 0. The address signal on the system bus are of the opposite sense so an inversion is required between the system bus and the microinstruction/address highway, MADBUS. The address signals to the highway MADBUS must be high impedance during RUN mode, but since some of these address bits are also used for address decoding they must be rebuffered and high impedanced separately. Inverting buffers are used for all system bus address and control signals. Those address bits which are used for address decoding as well as on the highway MADBUS are rebuffered without inversion. Then signal BPROGENL controls the buffers so that their outputs are active only in PROG mode.

Waveform sequencer selection.

A NOR gate ensures that a selection register is presented with data which is TTL high only when certain system bus address bits are at logic 0. (TTL high on the system bus). The system bus write signal, IOWC only clocks the input of the selection register if bit F is logic 0 (TTL high) and bit E is logic 1 (TTL low) on the system bus. The output of the control register is TTL high when the waveform sequencer is selected and this allows address bits C and D to propagate through, so that other RAM areas may be affected by subsequent read and write operations until the waveform sequencer is de-selected.

Read and write decode.

Address bits C to F control the routing of read and write signals to a control register and to the microprogram memory in the sequencer unit, SU. For any read or write to occur address bits E and F should both be logic 0 (TTL high) on the system bus. This condition is detected by a NOR gate which permits the read and write signals to pass through respective NAND gates.

The read signal READL is supplied to the sequencer unit, SU. The write signal may be prohibited by the inverse of signal WFSRUNL if bit E of the control register indicates RUN mode. The write signal, is supplied to the sequencer unit, SU.

Signal READL is inverted, and is used to clock the read only section of the control register.

The inversion causes the leading edge of the read signal to clock the register so that data may be presented to the DATABUS early enough or recognition on the system bus. The data in the read only section is only asserted on the DATABUS if the waveform sequencer is selected and address C is logic 0 on the system bus and signal READL is low. The data is signal INT4 from port 1 and INT2 from the clock generation circuit, CG. Data bits 2 to 7 are TTL high (logic O) on the system bus while bits 8 to F are not asserted at all and are therefore indeterminate.

The write pulse is also used to permit the write only section of the control register. The trailing edge of the derived write pulse is used as the active clocking edge.

Synchronous mode controls.

Bits E and F of the control register are synchronised to the waveform sequencer clocks by using signal 2MOR at an octal bistable device. Each signal is fed back into the octal bistable device to be reclocked to avoid problems if the control register output changes while the octal bistable device is clocked. Signal WFSRUNL is the retimed output of bit E of the control register and is supplied to the clock generation circuit, CG.

An inverse of signal WFSRUNL which is TTL high in RUN mode, prohibits the write pulses and also serves to mask signal SRAMENL during RUN to produce signal SRAMSELL. This masks bit D of the system bus to prevent the transceivers of the sequencer unit, SU writing to the system bus during RUN mode. In RUN mode the inverse of signal WFSRUNL permits signal MADZ from the sequencer unit, SU to control signal INTENABH.

The signal WFSRUNL is fed back to delay it to the next edge of signal 2MOR. The retimed signal is used to mask signal MESSRUNL from the sequencer unit, SU. This prevents high impedance indeterminate data of the sequencer unit, SU being outputted to the clock generation circuit, CG during the PROG to RUN transition and forces signal TURNIPH TTL high during PROG mode.

The following table uses PROG and RUN states to summarise the relationship between the signals, PROGRUNL and MSBSRUNL.

CONTROL REGISTER PROGRUNL MSBSRUNL BIT E BIT F RUN PROG PROG PROG RUN PROG RUN RUN RUN RUN PROG RUN RUN RUN RUN RUN PROG X x PROG

RUN=TTL low, PROG=TTL high, X=RUN OR PROG Transfer acknowledgement.

Read and write signals are routed to a shift register and the reset input of the register is low in the absence of a read or write pulse, and high for the duration of a read or write pulse.

When the reset input is low the 0 outputs of the register are also low. A read or write pulse will cause each 0 output in turn to become TTL high on successive rising edges of a CK16MOLR clock signal and remain high for a period dependant on the duration of the pulse and the rate of the clock. The register therefore produces a range of delayed pulses one of which is produced at port 1, signal XACK, when the waveform sequencer is selected and the address bit F at the system bus is logic 0 (TTL high). This signal is normally TTL high but a read or write will cause signal XACK to become low.

Initialisation.

The signal BINITL is TTL low for a short period after power-up and also whenever signal INIT at port 1 is TTL low (logic 1).

Sequencer Unit, SU.

Signal description.

MSFLA G2 W.

This signal is an open collector flag output signal dependant upon the state of signal MADM and signal MADZ on the highway MADBUS. This signal is indeterminate during PROG mode because signal MADZ is high impedance and in RUN mode the signal is dependant upon the contents of the microprogram memory, launched by signal CLK4MOR. When signal MADZ is TTL high, this signal is the inverse of signal MADM, and when signal MADZ is TTL low, this signal is TTL high.

MSFLA G3 W.

This signal is the same as signal MSFLAG2W except that it relates to signals MADN and MADZ.

INT3.

This signal is the same as signal MSFLAG2W except that it relates to signals MADK and INTENABH.

TABSYNL.

This signal is a flag output to the slave tester control circuit, STC and is dependant upon the state of signals MADL and MADZ. This signal is indeterminate during PROG mode because, signal MADZ is high impedance, and in RUN mode the signal is dependant upon the contents of the microprogram memory.

When signal MADZ is TTL high, this signal is the inverse of signal MADL, and when signal MADZ is low, this signal is TTL high.

CLKFRM.

This signal is a flag output to circuit WTG, and is the inverse of signal MADJ and is indeterminate during PROG mode. During RUN mode it is dependant upon the contents of the microprogram memory launched by the rising edge of signal CLK4MOR.

MESSRUNL.

This signal is the same as signal CLKFRM except that it relates to signal MADH and is supplied to circuit SBI.

Circuit description.

Flag inputs.

Four flag input signals are used, and are MSFLAGOW, MSFLAG1W, TBO and MSBSRUNL. The first two are driven by circuits external to the waveform sequencer. The second two are supplied by circuit SBI.

Transceivers.

Two transceivers are used in the sequencer unit, SU.

The transceivers are inverting devices because the data on the system bus at port 1 uses TTL low for logic 1 and the microprogram memory requires TTL high for logic 1.

Signals SRAMSELL and SRAMENL.

On the waveform sequencer two select enable inputs are applied to the sequencer unit, SU.

This is because the signal applied to the output controls of the transceiver should be applied later than the signal used to generate the signal SRAMSELL, because the high impedance levels on the microprogram memory RAM outputs would be imposed upon the data bus at port 1 during the PROG to RUN transition. The signal SRAMSELL is derived from signal SRAMENL and the inverse of signal WFSRUNL in circuit SBI, and disables the output of the transceivers earlier in the PROG to RUN transition than signal SRAMENL would.

A detailed description of the sequencer unit will be described later.

Waveforms Triad Generation, WTG.

Signal description.

FRPAOUTA and FRPAOUTB.

These signals are A and B signals of a transformer coupled balanced line output to port 5 which are either disabled by data in bit 0 of the control register (FRAME SYNC ENABLES) or provide a waveform dependant upon signal CLKFRM from the sequencer unit, SU. A rising edge of CLKFRM causes a retimed rising edge on the FRPAOUTA output.

FRPBOUTA and FRPBOUTB.

These signals are the same a signals FRPAOUTA and FRPAOUTB except that they are enabled/disabled by bit 1 of the control register.

FRPCOUTA and FRPCOUTB.

These signals are the same as signals FRPAOUTA and FRPAOUTB except they are enabled/disabled by bit 2 of the control register.

CLKA2MRA and CLKA2MRB.

These signals are A and B signals of a transformer coupled balanced line clock output to port 95. The frequency is the same as signal C2MOR from clock generation circuit, CG and its phase with respect to signal CSMOR is dependant upon the data in bits 3 to 5 of the control register CLOCK SELECT signals from circuit SBI.

CLKB2MRA and CLKB2MRB.

These signals are the same as signals CLKA2MRA and CLKA2MRB except that the clock phase is dependant upon bits 6 to 8 of the control register CLOCK SELECT signals.

CLKC2MRA and CLK2MRB.

These signals are the same as signals CLKA2MRA and CLKA2MRB except that the clock phase is dependant upon bits 9 to 8 of the control register CLOCK SELECT signals.

Circuit description.

Clock phase generation.

Signal CK16MOLR from the clock generation circuit, CG is used to clock signal C2MOR into an octal bistable device. Seven of the bistables in this device are wired as a serial shift register with each 0 output providing a different amount of delay to the original signal C2MOR, producing seven phases of clock signals.

Clock phase selection.

The seven phases of 2048kHz clock are supplied to multiplexers for selection by the CLOCK SELECT signals from circuit SBI. Each multiplexer uses three CLOCK SELECT signals to select one of eight inputs, seven with clock phases and one wired to TTL low which is selected to inhibit the clocks. The inverting output of each multiplexer is used because the propagation delay to these outputs is less than for the non-inverting output. A quad bistable retimes and inverts the selected clocks to the rising edge of signal C32MEG after the rising edge of signal C2MOR.

Frame resets.

The sequencer unit, SU may be programmed to produce a frame reset signal CLKFRM which is launched by the rising edge of signal CLK4MOR. This signal is retimed to signal CK16MOR to the rising edge of signal 32MEG.

Output drives.

Six transformer coupled balanced line outputs provide three clock signals and three frame reset signals to port 5. The frame resets are identical when enabled but each may be disabled individually using FRAME SYNC ENABLE signals from circuit SBI.

Slave Tester Control Circuit, STC.

Signal description.

2048kHz REFERENCE OUT.

This signal is a TTL balanced line clock output to port 6 supplying a 2048kHz clock with a phase 2M7R using REF2MCKR from the clock generation circuit CG. This output is high impedance when signal BINITL is TTL low.

RUN/PROGRAM OUT.

This signal is a TTL balanced line output to port 4 derived from signal MSBSRUNL from circuit SBI. This output is high impedance when signal BINITL is TTL low.

INTER TESTBOX SYNC OUT.

This signal is a TTL balanced line output to port 4 derived from signal TABSYNL from the sequencer unit, SU.

This output is high impedance when signal BINITL is TTL low.

SLA VSELL.

This signal is a TTL logic level which indicates that the waveform sequencer is a slave when TTL low, and a master when TTL high. This signal is identical to the SLAVE SELECT signal at port 4 except that SLAVE SELECT has a 0 volt reference output.

EXTCLKR.

This signal is an unbalanced TTL signal derived from 2048kHz REFERENCE IN at port 4 with the same phase as the A signal of the balanced line input.

TBSO.

This signal is an unbalanced TTL signal corresponding to the A signal of INTER TESTBOX SYNC IN at port 4.

PROGRUNL.

This signal is an unbalanced TTL signal corresponding to the A signal of RUN/PROGRAM IN at port 4.

Circuit Description.

Slave tester inputs.

When signal SLAVSELL is TTL low, a quad line receiver terminates the 2048kHz REFERENCE IN, INTER TESTBOX SYNC IN and RUN/PROGRAM IN signals ar port 4, and respectively produces signals EXTCLKR, TBSO and PROGRUNL. When signal SLAVSELL is TTL high the receiver is disabled and the outputs are pulled to TTL high.

The SLAVE SELECT section of port 4 consists of a 0 volt reference output and an input which is pulled to a TTL high level when open circuit. A shorting link between the reference and the input forces signal SLAVSELL to TTL low.

Slave tester outputs.

When signal BINITL is high two line drivers produce the signals 2048kHz REFERENCE OUT, INTER TESTBOX SYNC OUT and RUN/PROGRAM OUT from signals REF2MCKR, TABSYNL and MSBSRUNL respectively. When signal BINITL is low the outputs of drivers are high impedance.

Referring to Figs. 3a, 3b and 3c the message sequencer will now be described.

The message sequencer is responsible for execution of the test microprogram. The microprogram is loaded into the unit from the slave processor during program mode, then executed when the sequencer is switched into run-mode. The message sequencer microinstructions provide particularly well developed facilities for handling flag communications to and from the bit sequencers and other message sequencers. By programming these flags it is possible to use the message sequencer as a high-level controller. Message sequencer microcode also make provision for raising an interrupt at the slave processor through the system bus.

Central to operation during program mode is a segmented addressing scheme. Before any input/output requests can be processed, a particular board must be selected by a special type of write operation known as a stage-1 write. All following stage-2 input/output activity will be directed to that board until another board is selected. The two stages of input/output operation are distinguished by one of the high-order bits in the associated address. Since the message sequencer is also responsible for communications between the system bus and the bit sequencers, it is the responsibility of the message sequencer to monitor all forms of system bus input/output activity, to select the appropriate board in the case of stage-1 accesses, and to channel stage-2 accesses to their correct destination. These functions are described below.

The system bus is monitored by the 10 Microinstruction Unit MU. This unit is capable of selecting input/output accesses relevant to its own Message-Bit Sequencer group. On finding such an access it generates the following sequence of input/output enables: Message Sequencer, or Message to Bit Sequencer and back to the system bus, necessary to action it. A separate sequence is generated for each type of input/output request, each one directed by a microprogram.

In the case of stage-1 writes, an input/output enable will activate stage-1 address decoder unit ST1. The will decode the group and board addresses represented on the incoming address lines from the system bus. As a result, it will generate a group of select enables indicating which board, if any, in the group is enabled. One group of selects is used by the message sequencer, another by bit sequencers; the selects are latched until another stage-1 write.

Data and addresses from the system bus are buffered through the data and address buffer units, DBU, ABU, respectively and hence to the data and address highways. The buffers also pass data and addresses between the system bus and bit sequencers. A number of different enables take part in controlling these buffers.

An initialisation unit, INIT generates a reset signal for use by other units of the message sequencer and the bit sequencers.

Decomposition.

Sequencer unit, SU.

Interfaces.

Data Highway: DO-DF; Microinstruction Address Highway: MADH-MADZ; in program mode lines MADK-MADW carry addresses in, in run mode lines MADH-MADZ carry microinstructions out; Mode Enables: Program/Run: Program/Run In: PRGHRUNL, Program/Run Out: MBRNNPGH; Modes Out, Board Program Enable: BPROGENL, Board Run Enable: BRUNENL, Sequencer Program Enable: SPROGENL, Sequencer Run Enable: SRUNENL, Select Enable: MSENL; 10 Enables, Read: READL, Write: WRITEL; Initialisation: BINITL; Clocks: 4MHz phO rising: CLK4MOR, 4MHz phl rising: CLK4MOR; Flags: Message-Message Sequencer Flags: MMFLAG0-MMFLAG3, Message Bit Sequencer Flags: MBFLAGO-MBFLAG1, Bit-Message Sequencer Flags: BMFLAGO-BMFLAG1.

Function.

This unit is an implementation of the standard Sequencer unit which will be described in detail later. 10 microinstruction unit, MU.

Interfaces.

System Bus 10 enables: IORCU (read), IOWCU (write), XACKU (transfer acknowledge); System Bus Addresses: ADRFU, ADREU, Mode enables: BRUNENL (board run enable); Select enables: MSENL (message sequencer enabled); Initialisation: BINITL; Clocks: CLK16MOR (16Hz ph 0 rising); 10 enables: READL (read), WRITEL (write), IOMS1WH (stage-1 write); Message-Bit Sequencer 1-0 enables: MBIORCL (read), MBIOWCL (write), MBXSVKL (transfer acknowledge).

It is the purpose of this unit to monitor the system bus for input/output, 10 requests, and when a request is active to generate the sequence of 10 enables to the message and bit sequencers necessary to action it. The sequence is directed by a microprogram, a detailed functional description of the unit will be described later under the heading Realisation of 10 Operations using the 10.

Microinstruction Unit.

Circuit description.

The 10 Microinstruction Unit, MU devides into three units as shown in Fig. 5. An 10 microinstruction input encoder IE, monitors the incoming addresses and enables for indications of 10 activity on the system bus, and formulates one of four signals representing no-operation, stage-1 write, stage-2 read and stage-2 write. This signal is passed to an 10 microinstruction finite-state machine, FSM where it triggers execution of the appropriate microprogram. The microprogram issues a sequence of 10 enables, most of which require further decoding or gating with input signals, and which are therefore passed to an 10 microinstruction output decoder, OD. From here the completed 10 enables are issued out of the 10 microinstruction unit, MU. The Microinstruction formats are as in Table 1 below: a. BIT DESIGNATIONS BIT SIGNAL FUNCTION 7 NOMAD4 Successor microinstruction address bit 4 6 IOMAD3 Successor microinstruction address bit 3 5 IOMAD2 Successor microinstruction address bit 2 4 IOMS1WH Stage 1 write (H) 3 IOMS2RH Stage 2 read (H) 2 IOMS2WH Stage 2 write (H) 1 IOMX 1 Transfer acknowledge code 1 O IOMXO Transfer acknowledge code 0 b. INPUT STATE CODES (forming successor microinstructions address bits 1 and 0) IOMS 1 IOMSO FUNCTION 0 O No operation 0 1 Stage 1 write 1 0 Stage 2 read 1 1 Stage 2 write c.TRANSFER ACKNOWLEDGE CODES IOMX 1 IOMXO FUNCTION 0 O XACKU disabled, 0 1 XACKU enabled, but no signal sent, 1 0 XACKU enabled, signal sent unconditionally, 1 1 XACKU enabled, signal sent conditionally, 10 Microinstruction Input Encoder Unit, IE.

Interfaces.

Multibus 1-0 enables: IORCU (read), IOWCU (write); System Bus addresses: ADRFU, ADREU; Selects: MSENL (Message Sequencer enabled); Modes: BRUNENL (board run enable); Fast read-write: FASTRWH; Microinstruction States: IOMSO, IOMSI, Functions.

Inputs representing different types of 10 activity on the system bus are monitored, and encoded to one of four states on an output. Another output merely indicates whether an 10 request is active or not.

A low level on signal lines IORCU or IOWCU indicates that a read or write respectively is active. If signal ADREU is low the access is a stage-1 write, otherwise it is stage-2.

The unit encodes these requests as shown in Format b above and in the truth table below.

If signal ADRFU is low the access is intended for the slave processor rather than the test box, and no-operation will continue to be recorded at the outputs, regardless of the inputs. The effect of signal BRUNENL is also such tha in run-mode (BRUNENL low) no activity will be indicated.

The effect of signal GROUPENL is such that if the group is not enabled, only stage-1 writes will be allowed through to the outputs; any other activity will be interpreted as no-operation.

Any type of 10 activity (ie IORCU or IOWCU low) will cause signal FASTRWH to go high. This signal responds within a short time of the transition on the system bus; used in later parts of the 10 microinstruction unit which require a fast response to the system bus.

Circuit description.

The circuit is a realisation of the following truth table, Table 2.

BRUNENL IORCU GROUPENL IOMSI ACTIVITY ADRFU IOWCU ADREU IOMSO L L L NO OPERATION L L L H H H H L L H H H L H H L L H H H L H L L L STAGE 1 WRITE H H H L L H H H STAGE 2 WRITE H H H L L L L H STAGE 1 WRITE H H L H H H L L NO OPERATION H H L H H L L L H H L H L H H L STAGE 2 READ H H L H L L L L NO OPERATION According to the system bus protocol, the address lines will stabilise 50ns before the IORCU or IOWCU command.

The signal BRUNENL will be steady throughout the 10 operation, and the signal GROUPENL can only change during a stage-1 write, to which it does not form a significant input.

10 Microinstruction Finite-State-Machine, FSM.

Interfaces.

Microinstruction State: IOMSI, IOMSO; Initialisation: BINITL; Clocks: CLK16MOR (16MO rising); Microinstructions: IOMS2RH (stage 2 read), IOMS2WH (stage 2 write), IOMS1WH (stage 1 write), IOMX1, IOMXO (transfer acknowledge codes).

Function.

Two input state-lines are monitored, and each combination of signals will trigger execution of a different microprogram. These reside in a read-only memory, and generate sequences of output signals.

Every 1 6MHz period the machine selects and enters one of thirty-one possible states, each of which is represented by an 8-bit,rnicroinstruction in a 32 x 8 read-only memory. Thus each state is defined by five address lines. The microinstruction for each state contains the five programmable signals, and the three high-order bits of the address of the next state to be entered (see Format a). The two low-order bits of this address come from the input state lines. Thus the microinstruction for each state is able to specify four potential successor microinstructions, the final choice between the four being made by the input states.

Every 16MHz period the microinstruction for the current state is executed. The output signals contained in it are issued out of the unit, and the next microinstruction is selected and accessed ready for the next period.

10 Microinstruction Output Decoder, OD.

Interfaces.

Microinstructions: IOMRH (read), IOMWH (write), IOMX1, IOMXO transfer acknowledge, Selects: MSENL (Message Sequencer enabled), GROUPENL (group enabled); Bit-Message Sequencer 10 enables: MBXACKL (transfer acknowledge) Fast read-write: FASTRWH; 10 enables: READL (read), WRITE (write); Message-Bit Sequencer 10 enables: MBIORCU (read), MBIOWCU (write); System Bus 1-0 enables: XACKU (transfer acknowledge).

Function.

Signals representing, in coded form, enables for primitive forms of 10 activity are decoded and gated with other enables.

Most of the processing within this unit is concerned with the transfer acknowledge signal. This input to the unit is encoded as shown in table 1. The signals are decoded within the unit and used to control the three state output XACKU in one of the following ways.

It may be floated, effectively isolating if from the system bus. It may be enabled but no signal sent, or it may be enabled and a signal sent either unconditionally or conditionally. In all of the latter three states the three state enable will only take effect if the group is enabled (ie GROUPENL active). If the signal is conditional, it will only become active if either the message sequencer is enabled (MSENL active) or the bit sequencer transfer acknowledge (BSXACKL) is active. Once this has taken place however, the output signal will be latched on even if the conditional input subsequently becomes inactive. The output will, however, be cleared by re moval of the microcode input directing the signal to be sent. The output is also gated with signal FASTRWH: when this signal is not active, signal XACKU will not be sent.

Input signals IOMRH and IOMWH are also gated with signal FASTRWH, before being output as READL and MBIORCU, or MBIOWCU signals respectively.

The following truth table, Table 3 pertains to the 10 microinstruction output decoder, OD.

GROUPENL IOMXO MSENL BSXACKL XACKU IOMXI FASTRWH MSENL BSXACKL t t+1 t t+l H Z L L L Z L L H H L H L L H L H L H L L H H L H L H H H H H H H H L H H H L L H H L L H H H L H H H L L H H H H H L L L L L H H H H H L H L Realisation of 10 Operations using the 10 Microinstruction Unit, MU.

On initialisation the microinstruction unit, MU will jump to an address with the three high order bits in the 000 states. After the system bus has settled, there should be no 10 requests active, thus the two low-order bits will also be in the 00 state forming an effective address of zero.

After the initialisation signal is removed, the high order three bits of address will be taken from the microinstruction, and the two low order bits from the input states. For as long as the two input states continue to be zero the microprogram will loop on address zero because the instruction of this address specifies a successor high-order address of zero.

When for example, the input encoder, IE begins to indicate that a stage-2 write is active on the system bus, the input states will change to 11. Both lines may not change at the same time, so after the next clock pulse the program may have reached an address of 00001, 00010, or 00011. None of these instructions specifies any action; they are in effect deglitching the inputs. By the next clock pulse, the input states will have settled to 11, forming a new address of 00111. This will generate a write pulse, which will be maintained as the program sequences through addresses 01011. 01111 and 10011. During instruction 10011 the system bus XACKU output will be enabled, but to an inactive signal level.Instruction 10111 will remove signal IOMS2WH, and send an active XACKU signal on condition that either the message sequencer itself is enabled or one of the bit seqeuncers has responded with its MBXACKL signal. If neither condition is satisfied, the implication is that the stage-1 address has been incorrectly specified, probably in an attempt to enable a non-existent bit sequencer. Removal of the IOMS2WH signal, and thus of signal MBIOWCU, will result in the loss of signal MBXACKL. However, if this signal persists for the indicated hold time after the transition on IOMX 1, IOMXO, the output XACKU will be latched on.

The microprogram will then loop on 11011, sending signal XACKU, until the system bus responds to this by clearing signal IOWCU. The following sequence of events will now take place. Signal FASTRWH will go inactive, clearing signal XACKU within a very short time as required by the system bus protocol. The microinstruction states will be modified by the input encoder from 11 to 00, although the 16MHz clock to the finite-state-machine, FSM may coincide with an intermediate state of 01 or 10. Whichever of the three states is captured, signal XACKU will be disabled, and when the states do reach 00 the microprogram will jump back to location zero once again. The program will loop at this location until another 10 request becomes active.

Stage Address Decoder Unit, STI.

Interfaces.

Addresses: MADT-MADW (representing the group addressed being requested), MADN-MADR (representing the group address being requested), Mode enables: BPROGENL (board program) enabled); 1-0 enables: IOMS1WH (stage 1 write); Initialisation: BINITL; Backplane straps: BPSTRPO-BPSTRP3 (representing the group address); Select enables: MSENL (Message sequencer enabled), BSENL (Bit sequencer enabled), GROUPENL (group enabled); Message-Bit Sequencer select enables: MBENO-MBEN3.

Function.

This unit is responsible for decoding a stage-1 (ie segment) address and generating and latching the appropriate select enables.

When signal IOMS1WH is active a comparison is made between the group address requested and the actual address of this group. If the comparison succeeds, then the 10 request is destined for a board within this group, and the board address requested is decoded. This is used to generate either MSENL or BSENL, the latter being accompanied by one of four MBEN signals indicating the bit sequencer concerned. In- either case, GROUPENL is also generated.

These enables will be latched until another stage-1 write.

On receipt of the initialisation signal enables will be deactivated, and in run mode they will also go inactive although the previous state will be restored on return to program mode.

Clock Unit, CKU.

Interfaces.

Waveform-Message sequencer clocks: WM16MOLR (16MHz phO late rising), WM14M1LR (4MHz ph1 late rising): Clocks: CLK 16MOR (16MHz phO rising), CLK4MOR (4MHz phO rising), CLK4M1R (4MHz phi rising); Message-Bit Sequencer clock: MBn16M (16MHz phO late rising) MBn4M (4MHz phl late rising), n=O to 3; Function.

This unit receives the clock input lines from the waveform sequencer, buffers them out to the bit sequencers and generates other clocks for use by the message sequencer.

The clocks are buffered through inverters. The output clock phases are derived from a shift register.

Initialisation unit, INIT.

Interfaces.

System Bus Initialisation: INITX; Power: +5V, OV, The power supply forms a logically significant input to this unit; Initialisation: BINITL; Message-Bit Sequencer initialisation: BINITL.

Function.

This unit generates initialisation signals for use by the message sequencer and its bit sequencers.

On power-up, a short active pulse will be generated on each of the outputs. The outputs will also go active for as long as the INITX signal input is active.

On power-up the inputs to a Schmitt NAND gate are held low for a period determined by the time constant circuit. With the valves used this holds the inputs under their threshold, for approx 15ms. A diode ensures that a capacitor in the time constant circuit discharges quickly when the voltage source is switched off.

The initialisation signal, BINITL, is produced either by the low input to the Schmitt NAND gate or a low input to an inverter received from the INITX line of the system bus.

Data and Address Buffer Units, DB, AB.

Interfaces.

Data buffer.

System Bus data: DATOU-DATFU; Message-Bit Sequencer data: MBDATOU-MBDATFU; Data highway: DO-DF; Select enable: BSENL (bit sequencer enabled), GROUPENL (group enabled); 10 enables: READL (read); Address buffer.

System Bus addresses: ADR1U-ADRDU; Message; Bit Sequencer addresses: MBADR 1 U-MBADRDU; Address Highway: MADH-MADZ Select enable: BSENL (bit sequencer enabled); Mode enable: BPROGENL (board program enable).

Function.

Data and addresses are buffered and passed between the system bus and the message sequencer, and optionally to the bit sequencers.

At all times during program mode addresses on the system bus (inverted) will be presented on the message sequencer address highway, lines MADK-MADW, in true form. Thus all message sequencers will have access to stage-1 addresses. The remaining lines on the highway will be indeterminate. The Message-Bit Sequencer Addresses will only be enabled and active if a bit sequencer is selected, otherwise they will float. In run mode the address buffer unit, ABU will disable active drivers and pull all lines MADH-MADZ high, the address highway is thus available for use by other units.

Data on the system bus are only inverted back to their true form and passed onto the data highway if the group is enabled. Otherwise active drivers will be disabled and the highway pulled up. Data is only enabled out to the bit sequencers if one is enabled, otherwise the lines float.

Power Supply Alarm Unit, PSA.

Interfaces.

Power supply alarms: PSALMENL, PSUALMH, PSUALML; at port 5.

System Bus interrupts: INT4X.

Function.

A power supply alarm from the equipped shelf group, ESG is monitored, and an interrupt raised when it becomes active. The interrupt becomes active when signal PSALMENL.

is active and signal PSUALMH is high relative to signal PSUALML.

The circuit uses an opto-isolator to separator a 50V Alarm signal from the TTL circuitry.

Interrupt Unit, RUPT.

Interfaces.

Microinstructions: MADH, MADJ, MADZ: Mode enables: SPROGENL (sequencer program enable); Clocks: CLK4MlR (4Hz ph 1 rising); System Bus interrupts: INTOX, INT1X.

Function.

The interrupt unit, RUPT raises and interrupt through the system bus when one is requested by the microcode.

An interrupt is requested by Format 1 microinstructions (MADZ low) when signal MADH or signal MADJ is high. The unit monitors the microinstruction/address highway, UI/AHWY for these combinations and the microinstructions are issued on signal CLK4MOR, interrupts are retimed by the unit to the following signal CLK4M1R to eliminate the effect of glitches on the microinstruction highway. The effect of signal SPROGENL is such that no interrupts will be sent during program mode.

Referring to Figs. 4a and 4b the bit sequencer will now be described.

The bit sequencer stoes, sequences, transmits and receives test data patterns to and from an equipped shelf group, ESG. The bit sequencer has two modes of operation namely PROGRAM (PROG) mode and RUN mode.

During PROG mode data patterns are written to, or read from the bit sequencer.

In RUN mode the sequencer unit contained in the bit sequencer and flags are used to control data patterns which are transmitted to the equipped shelf group, ESG. Also, during this mode data patterns are received from the equipped shelf group, ESG and stored.

Test data 10.

The bit sequencer has balanced line interfaces to the equipped shelf group, ESG and uses balanced line drivers and receivers.

Each bit sequencer is able to drive up to eight balanced lines and receive eight balanced lines.

The data is transmitted or received on one of the four phases of 4096kHz signal ie. 4MO, 4M1, 4M2, 4M3. Received data does not need to be on the same phase of clock as the transmitted data. The phases are selected during PROG mode.

The test data to be transmitted to the equipped shelf group, ESG is stored in an area of RAM known as the Tx byte dictionary, TBD. The RAM is addressed via the sequencer address highway enabling the required bytes of data from the RAM to be sequenced to form the total test pattern. The data received from the equipped shelf group, ESG is stored in an area of RAM known as Rx data store, RDS. This is also addressed by the sequencer address highway.

All inputs from the equipped shelf group, ESG address a compare truth table RAM, CTT. This provides a comparison with previously downloaded data. Also two inputs to this RAM are provided from the microinstruction as 'qualifiers' to the comparison. The output of the comparison is a flag.

Sequencer Unit, SU. The sequencer unit will be described later, the following flags are used: Two flags on an open collector highway provide bit sequencer flags. Any bit sequencer is able to drive the flags, the microprogramming prevents bus contention. One flag comes from the output of the compare truth table, RAM, CTT and the other direct from the microinstruction.

Two external flags are received from an external source on an open collector highway.

Two flags are sent to an external source from the bit sequencer, one from the compare truth table RAM, CTT and the other from the microinstruction RAM.

All the flags can be masked by the sequencer unit, SU, and are pulled-up externally. One bit of the microinstruction is used to control the balanced line drivers to the equipped shelf group, ESG. Two bits are used as qualifiers in the compare truth table RAM, CTT.

Clock generation, CGEN.

The bit sequencer receives two clocks, 16MOLR and 4M1LR. These clocks are used to generate all other clocks required by the bit sequencer.

Initialisation.

Initialisation is achieved by either the on board power on reset circuitry or by an external signal.

Program run control.

The mode of operation of the bit sequencer, PROG or RUN, is controlled by an external signal from port 3.5 which goes to the sequencer unit, SU. However the bit sequencer will always power-up in PROG mode irrespective of what the external signal indicates.

PROG mode.

All accesses via the MSBSIF signal line, port 3, to the Tx byte dictionary TBD, Rx data store, RDS, compare truth table RAM, CTT, clock selection register and microinstruction memory take place in PROG mode. Accesses use the following lines: a. Read b. Write c. XACK (Acknowledge) d. Board select (BSEN) e. Two RAM decode lines (RAMAD) f. 11 address lines g. 16 data lines The two RAM decode lines select the area of RAM to which the access is made, as below: RAM DECODE RAM AREA Bit 1 Bit O 0 O Microprogram memory.

0 1 Tx byte dictionary and RX data store 1 0 Compare truth table RAM and clock selection register.

1 1 Not used.

The Tx byte dictionary, TBD and RX data store, RDS occupy the same area of RAM address.

Both are eight data bits wide and share the sixteen bit data bus. The Tx byte dictionary, is on the lower eight bits (0-7) and the Rx data store, RDS on the upper eight bits (8-F).

The microprogram memory is sixteen bits wide and occupies one RAM address area.

The compare truth table RAM CTT occupies the same area of RAM address as the clock selection register. The compare RAM is 1Kx2 bits. It generates two flags, data bit 0 (the internal flag) and data bit 1 (the external flag).

The clock selection register is clocked whenever the compare truth table RAM CTT is selected. It occupies data bits two to five inclusive. Data bits two and three select the clock phase used to transmit the data equipped shelf group ESG. Data bits four and five select which clock phase is used to receive the data from the equipped shelf group, as shown below.

DATA BIT CLOCK DATA BIT CLOCK PHASE PHASE 2 3 4 5 O 0 0 4M0 0 0 4MO O 1 4M1 0 1 4M1 1 0 4M2 1 0 4M2 1 1 4M3 1 1 4M3 The address from port 3 is buffered onto the microinstruction/address bus, MADBUS. In PROG mode, the mircroprogram sequencer in the sequencer unit SU passes the contents of the microinstruction/address MADBUS directly onto the sequencer address highway. The Tx byte dictionary, Rx data store RDS and microprogram memory are addressed via the sequencer address highway. The compare truth table RAM CTT is addressed by the microinstruction/ address highway MADBUS.The data from the equipped shelf group ESG passes through buffers, the outputs of which are held in a high impedance state during PROG mode preventing data bus contention in connection with Rx data store RDS and address bus contention in connection with the compare truth table RAM, CTT.

An access to an area of RAM is achieved in the following way. The board select line is active first. Then a valid address, RAM decode and data (in write only) appears before the read or write line is active. When a read or write signal is received the bit sequencer returns an XACK signal via MSBSIF port 3.

Run mode.

During this mode data is transmitted to and received from the equipped shelf group ESG.

Sequencer unit communication is via open collector flags and controlled by each sequencer's sequencer unit, SU. Data output from the Tx byte dictionary TBD is retimed to 4MO and by circuit RTE1 transmitted to the equipped shelf group, ESG on one of the following four phases 4MO, 4M1, 4M2, 4M3. Transmitted data is driven via balanced line drivers, controlled by the microinstruction, to the equipped shelf group, ESG.

Data is received on balanced line receivers and then latched on a selectable phase of the 4096kHz clock (4MO, 4M1, 4M2 or 4M3). The latched data is then used as the address for the compare truth table RAM, CTT and retimed by circuit RTE2 to 4MO for writing into the RX data store RDS. The output of the compare truth table RAM CTT is retimed to 4MO and bit zero is sent to port 2, and bit 1 to the MSBSIF port 3.

Data transmitted and received to the equipped shelf groups ESG is controlled by the address on the sequencer address highway. This address is controlled by the microinstruction.

EXTERNAL INTERFACES.

PORT NAME NUMBER Test 1 Test data 10.

2 Bit Sequencer-Bit Sequencer I/F.

3 MSBSIF.

3.1 Message Sequencer-Bit Sequencer I/F.

3.2 Bit Sequencer-Bit Sequencer I/F.

3.3 Data Bus.

3.4 Address Bus.

3.5 Control Signals.

3.6 Clock Signals.

Circuit Descriptio,.

Control Buffer, CB.

Control signal buffering is achieved by using a transceiver.

The following signals are buffered by this device.

1 1 MBIOWCL ~WRITE.

2 MBIORCL ~READ.

3 MBENL ~SEQUENCER ENABLE.

4 MBRNNPGH-PROGRAM/RUN SELECT.

5 MBRAMOL -) RAM DECODE.

6 6 MBRAM1L '' '') The buffer is permanently enabled and all signals except for the RAM DECODE signals are pulled up. This provides a known state should the input be disconnected or removed.

Control Logic, CL.

This consists of three areas, namely, data and address control signal generation, power-on reset signal generation and acknowledge signal generation.

Data and Address control signal generation signals MBRAMOL, MBRAM1L, and BSENL are directly connected to the 32x8 PROM and together with the BRUNENL signal are used to define the following signals, as shown below.

CSCOMPL. This signal is used to select the two 1Kx 1 RAMS in the compare truth table, CTT.

CSDATAL. This signal is used to select two 2Kx8 RAMS, one of which is in the transmit byte dictionary TBD, the other in the receive data store, RDS.

CSCNTL. This signal is used via inverting and NORing circuitry to produce sequencer and RAM control signals.

MBRAM 1 L MBTRAMOL SIGNAL GENERATED 0 O CSCNTL ; 0 O CSCOMPL 0 1 CSDATAL NOT USED.

During PROG mode these signals are only active provided that the board is selected and the appropriate signals appear on the ram decode line's. In RUN mode the signals are permanently enabled to provide constant chip selection. Signals ENCMPL ENDATPGL and ENCNTL are used to control data buffers during PROG mode. The former controls the data buffers to the compare truth table CTT and the second controls the transmit byte dictionary TBD, and the later the data buffers on the sequencer control RAMS. To be active in this mode the board must be selected and the correct signals received on the RAM decode lines.

In RUN mode these signals send the data buffers into high impedance state. The ENCMPL and WRITE signals are also used in the variable clock generation circuit. The write signal of the transmit dictionary is only active during PROG mode. The write signal for the receive data store is gated with a 4096kHz clock to provide continuous writes in RUN mode. During PROG mode WRITEL controls write operations.

The compare truth table CTT is used to check input data with data already stored in the two 1Kx 1 RAMS.

In PROG mode, before any WRITE or READ operation can take place the bit sequencer must be selected, signals CSCOMPL and BRPROPGENL are active and either signal WRITEL, generated by the control logic CL is active for WRITE operations or inactive for READ operations.

In this mode the BBFLAGOX and BMFLAGOWX buffers will be disabled.

In RUN mode the RAM addresses are provided by the eight input data lines and bits M and N of the microinstruction and address highways MADBUS. The MADZ signal enables the output buffers and the state of BBFLAGOX and BMFLAGOX is dependent on the data bits DO and D1.

Data buffers, DB.

Data buffering is achieved by using two bidirectional transceivers. Data cannot pass through unless the board is enabled ie. BSENL is low. The direction of flow of data is determined by a READL signal, generated by the control logic, CL.

Transmit byte dictionary, TBD.

This area is used to store all the test data that will be used during RUN mode.

For this area to be operational in PROG mode, the board must be selected, the correct signals must be received on the RAM decode lines and the RAM enabling signal line must be active.

For a WRITE operation the READL line will be high and the RAM GW input, from the receive data store RDS, low. The sequencer address highway provides the address of the data destination. The data itself is buffered through a bidirectional transceiver and written into the RAM. For the READ operation the READL signal will be low, the input to RAM high and the data that is read from the RAM will be buffered out through the transceiver to the internal data bus.

In RUN mode the transceiver will be disabled. Data can then be read out from the address supplied from the sequence address highway and passed into the RETIME circuit RTE 2.

Retime (Transmit data) RTE1.

This circuitry is only used during RUN mode. The retime circuitry consists of two octal bistables. When the data reaches the inputs of the first bistable it is clocked through at delayed 4MO by the DCK4MOR signal. The second bistable is clocked by the VARCK1 signal. The frequency of this signal is set up during PROG mode and is either 4MO, 4M1, 4M2 or 4M3. The clock signals DCK4MOR and VARCKI are generated by the clock generation circuit C.GEN.

Balanced Line Drivers, BLD.

The line drivers can only be enabled during RUN mode. The enable signal is the result of inverting signal MADH and ORing it with signal SRUNENL. During RUN mode the drivers are switched on and off by the MADH signal which is part of the microinstruction highway. address buffers AB. The address buffers can only be enabled during PROG mode and then only when the board is selected. In RUN mode the address buffers are disabled.

Receive Data Store, RDS.

This area operates in both PROG and RUN modes. In PROG mode, the RAM enabling signal is active when the board has been selected and the correct signals received on the RAM decode lines. When the transceiver is enabled, data can pass from the data highway to the (2K x 8) RAM. The address for the data during read or write operations is provided by the sequence address highway. The READL signal controls the direction of data through the transceiver and is active during the READ operation.

Retime (receive data), RTE 2.

During PROG mode this circuitry is disabled. In RUN mode the BRUNENL signal enables both bistables. Received data is retimed in the first bistable to the rate of VARCK2, generated by the clock generation circuit C.GEN. This data is fed into the next bistable and also to the address lines of the RAMs in the compare truth table, CTT. The second bistable retimes the data to delayed CK3MOR, and it is then sent to the receiye data store RAM.

Balanced line receivers, BLR.

The balanced line receivers are permanently enabled by a pull up resistor. Data is received over eight balanced lines.

Transmit and Receive Clock Phase Selection, C. GEN.

Clock phase selection is carried out in the clock generation circuit C.GEN. During PROG mode, one of a maximum of four clock phases is chosen for transmission and receiption of data to and from the equipped shelf group ESG. These phases are CK4M0R, CK3M1R and CK4M3R. The phases used for transmission and receiption need not be the same.

The 16MHz and 4MHz clock signals, MB16MOLR and MB3M1LR are received and are immediately buffered and inverted to become CK16MOR and CK4M3LR respectively. The CK16MOR signal is then used to clock the CK4M3LR through an octal bistable.

The four clock phases mentioned above are derived from the first four outputs of this device having a time delay of a 16MHz clock pulse (61.5ns) between them. The clock phase signals are then fed into two 4 to 1 multiplexers.

Signals ENCMPL and WRITEL are ORed, via anti-glitch circuitry, to clock a Hex bistable, used to latch the information on lines D2, D3, D4 and D5 of the data bus.

This information is used to select which clock phase will be output from the two multiplexers.

Two of the multiplexer's outputs are then retimed using the bistable to provide VARCK1 and VARCK2 signals. A third output is inverted and provides the DCK4MOR signal. The fourth output is unused.

Sequencer Unit, SU.

A A Sequencer Unit, SU will now be described in detail. The sequencer unit executes the microinstructions, and one is included in the waveform sequencer WS, message sequencer MS and bit sequencer BS types, although there are slight differences arising from the fact that the microinstructions themselves are different for each sequencer. A bit sequencer microcode makes provision for the transmission of data between the bit sequencer BS and the equipped shelf group ESG, and also for sending flag communications between bit sequencers BS in the same group. On the message sequencer MS the microinstructions provide facilities for handling flag communications from the bit sequencers BS and other message sequencers MS. By programming these flags it is possible to use the message sequencer MS as a high level controller.The waveform sequencer is principally responsible for generation of clocks to the other sequencer interfaces, a function which is hardwired. Its microcode, however, carries instructions for highlevel control of the test, including the program/run state of the other sequencer interfaces, communications with message sequencers MS, and with waveform sequencers WS in other test-boxes.

The above however, are only the variations on a common core of microorders, designed to control their own sequence of execution. It is this task which the sequencer unit is responsible for carrying out, as well as issuing the microinstructions to other units within the particular sequencer for execution of non-standard portions.

The block diagram of a sequencer unit is shown in Figs. 6a, 6b. The unit is provided with a data highway 1 connected to a microprogram memory MM, and comprises sixteen lines for carrying data bidirectionally. A microinstruction/address highway 2 is provided comprising sixteen bidirectional lines for carrying microinstructions and address data. In the program mode, lines 2-12 carry microinstructions out. The microinstruction/address highway 2 is connected to an instruction interpretation unit, llU, a microprogram sequencer circuit MS, flag highway buffers B and a microinstruction register MR.

The sequencer unit is provided with a program/run control circuit PRC. Mode enable signals 3 provide program/run signals 3.1 comprising a program/run in signal 3.1.3. and an optional program run out signal 3.1.2. depending upon the application of the sequencer unit. Modes out signals 3.2 are provided, comprising a board program enable signal 3.2.1., board run enable signal 3.2.2., sequencer program enable signal 3.2.3., and a sequencer run enable signal 3.2.4.

A A select enable signal 4, and 10 enable signals representing a Read signal 5.1 and a Write signal 5.2 are provided, together with an initialisation signal 6. Clock signals 7.1 and 7.2 are applied to the program/run control circuit PRC. Clock signal 7.1 represents a 4MHz phase 0 signal, and clock signal 7.2 represents a 4MHz phase 1 signal. The program/run control circuit, PRC generates sequencer random access memory enable signals in the form of an output enable signal and a chip enable signal.

The mode enable signals 3.2.1., 3.2.2., 3.2.3. and 3.2.3, select enable signal 4, 10 enable signals 5.1, 5.2 clocks 7.1, 7.2 and sequencer random access memory enable signal are connected to various circuits shown in Figs. 6a, 6b.

The flag highway buffers B generate flag signals 8 depending upon the application of the sequencer unit. All flag signals are applied to the instruction interpretation unit, IIU.

A sequencer control highway comprising six lines connects the instruction interpretation unit, IIU with the microprogram sequencer MSR. A sequencer data highway comprising sixteen lines connects the microprogram memory MM with the microinstruction register MR. A sequencer address highway 9 comprises eleven lines and connects the microprogram sequencer MS with the microprogram memory MM. Figs. 7a, 7b, 7c and 7d show the circuit diagram of the sequencer unit SU, used in the message sequencer MS, which is basically the same as the sequencer units used in the bit sequencer BS, and waveform sequencer WS, with only minor modifications to adapt the unit for its different environments. It will be seen from the drawings that it conforms with the block diagram of Figs. 6a, 6b.

Further, it is understood that the circuit components used in the respective sequencers are state of the art components the connection and use of which will be readily appreciated by those skilled in the art.

The following description therefore, should be read in conjunction with the Figs. 6a, 6b and 7a 7b, 7c and 7d, describes the function of the sequencer unit.

Run Mode-Microinstruction cycle.

Every 4096kHz period the sequencer unit executes a microinstruction which controls the sequencer interface during that period. The sequence of events directed by the microinstruction is as follows: The microinstruction and its address are issued out of the microsequencer on the microinstruction and sequencer address highways respectively. Other units within the sequencer interface will then be able to interpret non-standard parts of the instruction. On the bit sequencer BS this will involve sending data to or from the equipped shelf group ESG, either now or later in the period, and on the message sequencer MS interrupts may be sent out on the system bus.

Flags are received from other sequencers. The current microinstruction may select any subset of these incoming flags, and OR them to produce a condition code.

On the bit sequencer a comparison may be made with incoming data from the equipped shelf group ESC. Flags may be formulated depending on the result; and those flags will comprise some of those discussed above.

Sequencing operations are carried out as a function of the microinstruction sequence code.

These may include program branches, links, (up to four may be nested), or returns, with addresses specified in the microcode or held in a register which may be loaded separately.

Some instructions may be conditional on a specified setting of the condition code.

The microinstruction field governing the sequence control comprises three bits, coded as follows; Code Mnemonic Function msb lsb O 0 0 O JMP addr Jump: Jump to address specified.

O 0 1 JSR addr Jump to subroutine: Push next sequential address into stack, then jump to address specified.

0 1 O LDR addr Load: Load address specified into register, then continue to next instruction in sequence.

0 1 1 Not used.

1 0 1 JMPCR c Jump on condition: If condition specified equals current condition code, jump to address in register, else continue to next instruction in sequence.

Code Mnemonic Function msb lsb 1 0 1 JSRCR c Jump to subroutine on condition: If condition specified equals current condition, push next sequential address onto stack, then jump to address in register, else continue to next instruction in sequence.

1 1 O RETC c Return in condition: If condition specified equals current condition code, pop address from stack and jump to it, else continue to next instruction in sequence.

1 1 1 JMPZC c Jump to zero condition: If condition specified equals current condition code jump to address zero, else continue to next instruction in sequence Where 'addr' is specified, the associated address is coded into the microinstruction as an 11bit binary number.

Where 'c' is specified the required condition code is included in the microinstruction, coded as follows: Code Mnemonic Condition O T true 1 F false The actual layouts of the microinstructions are not given since they vary between the different applications. However, all the fields referred to above are standardised in the same position for each sequencer interface.

The microinstructions also include facilities for the transmission and receipt of flags. The arrangement of the flag highways is described later. Each type of sequencer can send flags to different destinations, and the microinstructions will include fields for all the other flags concerned. Similarly each sequencer receives several flags from different sources and the microinstructions will also include a set of mask bits, one for each incoming flag. During a microinstruction cycle, all those incoming flags whose bits are set will be examined, and if any such flag is set the condition code for the current cycle will be set to true.

At the start of run mode, the unit always begins by executing the microinstruction at location zero.

Program mode, During program mode the sequencer is loaded with microcode. It is also possible, for test purposes, to read the microcode back. 10 operations require an active Select Enable, together with the appropriate 10 Enable.

Mode control.

The basic mode-definition input is the input program/ run line. The sequencer issues four mode enables: board/ sequencer program/run enable. This is to allow for the fact that the sequencer, and other units which interpret microinstructions should go into run mode one 4096kHz period later than the rest of the board. An intervening 'guard slot' is required as part of a chain of events involved in starting the sequencer unit running. Also, irrespective of the state of the program/run line, the sequencer will always power-up in program mode and respond only to a program-to-run transition.

Circuit architecture.

During the run mode a microinstruction is captured by the microinstruction register at the start of every 4096kHz period. The instruction is issued into the micro-instruction/address highway MADH-MADZ from which it is available to any unit which participates in its execution. The highway is carried out of the sequencer unit so the instructions are available to other units to interpret any non-standard portions.

Those fields in the instruction representing flags will be interpreted by the flag highway buffers. The flag highways transmit the flags to other sequencers.

Microinstruction fields representing the sequencing function, required condition code and flag masks are brought into the instruction interpretation unit, together with the incoming flags. Here the flags ar collated with their masks and the condition code formulated. If the current sequencing field represents a conditional instruction, the condition code is compared with the one specified in the microcode. The sequencing order will only be carried out if the comparison succeeds, otherwise it will be required to go on to the next sequential instruction. In either case the appropriate combination of control signals will be issued out into the sequencer control highway. These signals represent enables for low-level forms of sequencing activity.

The microprogram sequencer MSR consists of a set of addressing circuits including a stack, a register and an incrementer. It can load values into these elements, and can output an address from any of these sources or from a direct input from the microcode. It can also set its output to zeroes. The incoming enables from the control highway will indicate what action is to be taken in each period. The microprogram sequencer MSR issues the address onto the sequencer address highway SAO-SAA. From here it is fed to the microprogram memory which accesses the next microinstruction. The sequencer address highway SAO-SAA is also issued out of the sequencer for use by any non-standard, address-driven unit.

The new microinstruction is carried by the sequencer data highway SO0-S09, SDA-SDF to the microinstruction register, ready for the start of the next 4096kHz period.

During program mode the microinstruction/address highway MADH-MADZ will carry the addresses associated with each 10 request. In this mode the instruction interpretation unit IIU will generate a command to the microprogram sequencer to output address values from its address inputs. Thus, there is an effectively transparent path from the microinstruction/address highway MADH-MADZ to the microprogram memory MM address inputs. The data buffers are enabled during program mode.

The program/run controls unit PRC is responsible for generating the mode enables, which are used throughout the sequencer and outside it. This unit also controls the microprogram memory, MM.

Decomposition.

Microinstruction Register, MR.

Interfaces.

Sequencer Data Highway: SDO-SDF; Microinstruction/Address Highway: MADH-MADZ; Clock: (4MHz phase 0); Mode enables.: Signal BRUNENL (board run enable Fig. 2) Function.

In program mode the signal BRUNENL is inactive and the register is disabled and its output to the microinstruction/address highway MADH-MADZ is switched off. In run mode a 16-bit instruction is clocked into the register by the 4MO clock, from the sequencer data highway SDO SD9, SDA-SDF to the microinstruction/address highway.

Flag highway buffers, B.

Interfaces.

Microinstructions: Line MADZ, and other lines depending on the application; Flag Highways: Vary according to application.

Function.

The microinstruction/address highway MADH-MADZ is monitored continuously. If MADZ is high, indicating that the current microinstruction is of conditional format, then any microinstruction lines that are high, representing active flags will be inverted to an active-low level on the open-collector flag highway. If line MADZ is low, indicating an unconditional microinstruction, then all the flag highway lines will be tied inactive.

Instruction Interpretation Unit, IIU.

Interfaces.

Microinstructions: MADW,MADX, MADY,MADZ and masks varying according to appli cation; Flag Highway: Vary according to application Mode enables: BRUNENL (board run enable), SRUNENL (sequencer run enable), SPROGENL (sequencer program Sequencer Control Highway: RE,ZERO,SO,S 1,FE,PUP.

Function. In program mode, the signals BRUNENL and SPRUNENL are both in the inactive, high state. The unit issues signals onto the sequencer control highway which direct the microprogram sequencer MSR to output an address direct from its inputs.

At the start of the guard-slot, the signal BRUNENL goes to the active, low state, and the unit will issue a new combination of signals directing the microprogram sequencer MS to output an address of zero.

In run mode, the signal SRUNENL is in the active flow state and the signal SPROGENL is in the inactive high state. The output will be a function of the microinstruction and flag highway inputs.

If the microinstruction is unconditional, the output will represent the combination of control signals necessary to action it. If the microinstruction is conditional, the incoming flags from the flag highway will be collated with their masks from the microinstruction.

If any flags are active whose masks are also set, a condition code will be set true, otherwise will be set false. The condition code will then be compared with the conditions code specified in the microinstruction. If the comparison fails it will direct the microprogram sequencer MSR to issue the next sequential address.

Circuit architecture.

During program mode the signal SPROGENL is in the active low state and the signal SRUNENL is in the inactive high state. This has the effect of enabling the tristate buffer onto the sequencer control highway whilst disabling the multiplexers. The signal BRUNENL is in the inactive high state, thus the highway is set as follows.

SO H PUP L S1 H RE H FE H ZERO H The microprogram sequencer MSR will interpret these signals as a request to issue an address direct from its inputs.

During the guard-slot, the signals SPROGENL and SRUNENL will not change, thus the buffer remains enabled. However the signal BRUNENL will go in the active low state, thus, the sequencer control highway becomes: SO H PUP L S1 H RE H FE H ZERO L The microprogram sequencer MSR interprets this as a request to issue an address of zero.

In run mode, the signals SPROGENL and SRUNENL change state, disabling the buffer and enabling the multiplexer. During each microinstruction cycle the signals to the sequencer control highway are a function of the micro-instruction function code, the microinstruction condition code and the actual condition code existing at the time.

Conceptually the bits from the microinstruction form four address bits to a 32x8 PROM. The remaining address bit represents the actual condition code, but this value takes much longer to settle than the other because it is dependent on the propagation of signals between boards. To avoid the long PROM access time in addition to this the circuit actually utilises two such PROMS, one with the condition code input tied high, the other low, and the actual condition signal switches the multiplexer between the two.

The PROM is coded to generate a set of control signals for each combination of inputs. Each group of four consecutive locations corresponds to a function code. Conditional instructions are coded such that if the requested and actual condition codes agree, the function is executed, otherwise a 'continue' order is generated. Unconditional instructions are coded such that the condition codes are effectively ignored. The information in the PROM is held in inverted form, and is inverted back by the multiplexers.

The remainder of the instruction interpretation unit IIU is concerned with evaluating the condition code used to control the multiplexers MUX. Lines from the active-low flag highway are inverted, then paired with the corresponding mask bits from the microcode. The flag/mask pairs are NANDED and all the results NORED in gates. Applications which use more than four flags will require more than one gate, the outputs of which should then be NANDED. This will result in the conditions code being inverted; in this case the true/false lines to the PROMs should be inverted to compensate.

Microprogram Sequencer, MSR.

Interfaces.

Sequencer Control Highway: SO,S1,FE,PUP,RE,ZERO; Microinstruction/Address Highway: MADK-MADN; Sequencer Address Highway: SAO-SAA; Clock: 4MHz phase 0.

Function.

The microprogram sequencer, MSR is provided by an AM2911A developed by Advanced Micro Devices. The sequencer comprises a group of circuits for address generation. The address output to the sequencer address highway can originate from an incrementor, a holding register, a 4-deep stack or direct from the inputs from the micro-instruction/address highway. It can also be set to zero. Addresses can be loaded into the register or the stack from the direct inputs.

Inputs from the sequencer control highway direct the unit on what action to take.

Circuit architecture.

The sequencer consists of three cascaded 4-bit-slice AM2911A microprogram sequencers.

Microprogram Memory, MM.

Interfaces.

Microinstruction/Address Highway: MADH-MADZ; Sequencer Address Highway: SAO-SAF; Sequencer Data Highway: SDO-SDF; Sequencer RAM enables: SRAMCEL chip enable, SRAMOEL output enable; 10 enable: read; Select enable.

Function.

A 2k by 16-bit memory is provided. On application of the address from the sequencer address highway and the appropriate control signals, data may be written or read between the memory and the microinstruction/address highway. During a read the buffers out to the microinstruction/address highway need not be enabled, in which case the data is available on the sequencer data highway.

Program/Run Controls, PRC.

Interfaces.

Program/Run: programrun in, and program run/out if necessary; Clocks: 4MHz phase 0, 4MHz phase 1; Initialisation; IO enable: read; Select enable; Mode enable signals: BPROGENL board program enable; BRUNENL board run enable; SPROGENL sequencer program enable; SRUNENL Sequencer run enable; Sequencer RAM enables: SRAMCEL chip enable; SRAMOEL output enable.

Function.

The unit issues four mode enable signals; BRPOGENL, BRUNENL, SPROGENL and SRUNENL, representing board/sequencer program/run states. In both cases the program/run pairs are always complementary.

On application of the initialisation signal, both the board and sequencer enables are set to the program mode. The unit monitors the incoming program/run line for a program to run changeover signalled when a high to low transition is observed. This must occur between a 4MO and 4M1 clock signal, otherwise it will be ignored. On the 4M1 edge the board program/run enables will then change state, indicating that the guard slot has begun. On the following 4MO edge the sequencer program/run enables will also change, indicating full run mode.

If the initialisation signal is applied when the input program/run line indicates the run mode, the outputs will still be set to program mode. They will not begin the guard-slot/run mode sequence until a correctly timed high-low transition is observed on the program/run line.

The transition back from run mode to program mode should also be timed to fall between the 4MO and 4M1 clock pulses. On the 4M1 edge both board and sequencer mode enables will then change back to program mode (there is no guard-slot). However, the timing of this transition is not checked by the proram/run controls PRC, and faulty timing will result in the unit malfunctioning. Relying on correct input timing is acceptable because if the generation of this signal did not obey the constraints the unit could not have entered run mode.

The unit also generates the sequencer RAM enable signals: SRAMCEL and SRAMOEL. In program mode signal SRAMCEL goes active when the input sequencer select enable signal is active, whilst signal STRAMOEL goes active with input read enable. In the guard slot and run mode both enables signals are held active.

Circuit architecture.

The two flip-flops AF and BF are clocked by 4MO and 4M1 respectively. The board program/ run outputs are derived from flip-flop BF, thus when the program/run input goes from program to run between 4MO and 4M1 these outputs change on the 4M1 clock. The sequencer program/run enables are also derived from the outputs of BF, but they are ANDED, conceptually with those from AF which does not see the input transition until the following 4MO clock. The sequencer program/run outputs are derived from separate gates in order to have them switch as nearly as possible at the same time, since outputs from this unit control three-state devices.

On initialisation flip-flop BF will be reset, holding board and sequencer mode enables to program mode. The program/run line should indicate program mode, thus the circuit waits for the high to low transition between 4MO and 4M1.

If the guard-slot is to be generated properly it is imperative that the program/run line changes at the correct time. There are two ways in which this might not be so; it may change after 4M1 but before 4MO, or the board might be initialised with program/run already at run mode. In the former case the circuit will enter a state in which flip-flop BF indicates program mode, that is the Q output is low, whilst AF shows run mode, 0 output low. In the latter case, BF is reset by the initialisation signal, thus it will indicate program mode under these circumstances too. In both cases, therefore the input to BF is forced low, holding both board and sequencer mode enables in program mode.This state is maintained until the program/run line goes high to indicate program mode and a 4MO clock pulse passes, at which point flip-flop AF correctly indicates program mode and the circuit resumes it normal sequence of operation.

Fig. 8 depicts the program/run changeover, showing the relationship between the program signals BPROGENL, BRUNENL, SPROGENL, SRUNENL, the instruction interpretation unit IIU, run line, PRGHRUNL, the microprogram sequencer MS, memory MM and register MR. The relationship between the clock signals 4MO, 4M1 and the signals BPROGENL, BRUNENL, SPROGENL and SPRUNENL is shown; and the periods when quad buffers F244 and multiplexer F258 of the instruction interpretation unit, IIU are enabled and disabled, together with the period when the microinstructions register is enabled and disabled. The timings are in nano seconds.

Fig. 9 depicts the run/program changeover together with the relationship between the signals PRGHRUNL, BPROGENL, SPROGENL, SRUNENL and the enable/disable periods of the buffer F244 and the multiplexer F258 in the instruction interpretation unit IIU, and the enable/disable period of the microinstruction register. The timings are in nano seconds.

Fig. 10 depicts the program mode timing during a read operation and timing constraints, together with the relationship of the microinstruction/address highway MADK-MADW, the sequencer data highway SDO-SDF, the microprogram register MR, program/run control gate FOO and F02 and microprogram memory MM comprising buffers LS245 and RAM D607S. The timings are in nano seconds.

Fig. 11 depicts the program mode timing during a read operation, and timing constraints. It further shows the relationship between the microinstruction/address highway MADK-MADW, the sequencer data highway SDO-SDF and WRITEL signal. Also shown is the microprogram memory inputs A1-A11, outputs B1-B8 and the WRITEL signal. The timings are in nano seconds.

Claims (12)

1. A test unit for testing digital telecommunications exchange equipment wherein the test unit comprises a master processor and a slave processor for generating in accordance with instructions from the master processor, a microcode pertaining to the test to be carried out, means for loading the microcode into an array of sequencers which operate upon the microcode to generate a test to be executed by the sequencers at equipment ports, and to provide a result which is returned to the slave processor for despatch to the master processor for evaluation.

2. A test unit as claimed in claim 1, wherein the array of sequencers are arranged in hierarchical form and comprise a waveform sequencer, a plurality of message sequencers and a plurality of bit sequencers; and arranged so that the waveform sequencer communicates with the master processor and the plurality of message and bit sequencers; and the message and bit sequencers are arranged to communicate with each other; and the bit sequencers are arranged to communicate with equipment in the exchange which is to be tested.

3. A test unit as claimed in claim 2, wherein the waveform sequencer includes a waveform generator for providing clock and synchronisation waveforms of fixed frequency and phase and of programmable frequency and phase, said waveforms of programmable frequency and phase being generated with a time resolution of one particular frequency per bit period.

4. A test unit as claimed in claim 1, 2 or 3, wherein the bit sequencers, while a test is running, transmit and receive bit patterns to and from the equipment under test, and are controlled by the message sequencers through a system of flags, the operation of the sequencers being controlled by microprograms which are downloaded from the slave processor.

5. A test unit as claimed in any preceding claim, wherein, while a test is not running, the test unit is controlled by the slave processor for loading microcode into memory means provided in each sequencer, and for reading up results to the master processor.

6. A test unit as claimed in any preceding claim, wherein each sequence includes a sequencer unit comprising, a mircroprogram memory connected to a data highway, a sequencer data highway and a sequencer address highway, a microprogram sequencer connected to a microinstruction/address highway, a sequencer control highway and a sequencer address highway; a microinstruction register connected to the microinstruction/address highway and the sequencer data highway, and flag highway buffers connected to the microinstruction/address highway and an instruction interpretation unit; and control circuitry for generating control signals to be applied to the instruction interpretation unit, microprogram memory, microinstruction register and flag highway buffers so that the sequencer unit handles information on the data highway in accordance with the information presented on microinstruction/address highway.

7. A test unit as claimed in claim 6, wherein the instruction interpretation unit is provided with a plurality of input gating means for receiving incoming flag signals and in accordance therewith generates a signal used for controlling multiplexing circuits which respond to data patterns presented thereto, to provide signals upon the sequencer control highway.

8. A test unit as claimed in claim 7, wherein the data patterns are generated from memory means addressed by signals on the microinstruction/address highway.

9. A test unit as claimed in claim 8, wherein the microprogram sequencer includes a plurality of addressing circuits which respond to signals present on the sequencer control highway and microinstruction address highway, and issues an addressing signal onto the sequencer address highway for presentation to the microprogram memory, the microprogram memory issues a microinstruction on the sequencer data highway to the microinstruction register, the microinstruction register issues microinstruction/ address data onto the microinstruction/ address highway during a next clock period.

10. A test unit as claimed in claim 9, wherein flag output signals are generated from the signals presented to the microinstruction/address highway by flag highway buffers which despatch flag signals to other sequencing units and feed back flag signals to the instruction interpretation unit.

11. A test unit as claimed in claim 10, wherein a control circuit is provided which responds to input clock signals and a plurality of other input signals to generate a plurality of control signals which are used to control the test unit.

12. A test unit substantially as herein before described with reference to Figs. 1 to 11 of the accompanying drawings.