JPH05107307A - Lsi tester - Google Patents

Abstract

PURPOSE:To accurately measure an LSI on which analog circuits are mingled with digital circuits by synchronously controlling a digital module and an analog module at high speed and accurately. CONSTITUTION:In an LSI tester in which a digital module and an analog module are controlled by separate controllers, a high rank test system controller 1 for loading a test program in the controller, a module controller 2 for controlling the digital module 20, and a module controller 3 for controlling the analog module 30 are provided. Furthermore, a code memory 24 for outputting code which synchronizes the analog module 30 based on the address of an address generator in the digital module 20 and a sequence generating circuit 31 for specifying an address to an address generator in the analog module 30 on the basis of the code in a code memory 24 are provided. The digital module 20 is designed to be synchronized with the analog module 30.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI tester for measuring an LSI in which an analog circuit and a digital circuit are mounted together, and more specifically, it synchronizes a digital module and an analog module at high speed and accurately. The present invention relates to an LSI tester capable of controlling and accurately measuring an LSI in which an analog circuit and a digital circuit are mounted together.

[0002]

2. Description of the Related Art A conventional LSI tester controls a digital module and an analog module, which are connected via a common sequence address bus, by a single controller, and controls the analog circuit and the digital circuit. LSI mixed with
Is designed to measure.

[0003]

SUMMARY OF THE INVENTION Such a conventional LS
Since the I tester controls the digital module and the analog module by one controller,
It has a drawback that it cannot be processed at high speed.

The present invention has been made in view of the above points, and it is possible to separately control a digital module and an analog module by two controllers, and a digital pattern is provided. The change of the address generator sequence is transmitted to the analog module by the code memory provided in the digital module, and the digital module and the analog module are synchronized in a short time for inspection. The object is to provide an LSI tester capable of performing the above.

[0005]

In order to achieve such an object, the present invention provides an L in which a digital module and an analog module are controlled by different controllers.
In the SI tester, a higher-level test system controller that loads a test program to the controller and a caller that synchronizes with the analog module based on the address of the address generator of the digital module.
The code memory that outputs the code and the code of this code memory
A sequence generation circuit for designating an address to the address generator of the analog module based on the
It is characterized in that the digital module and the analog module are synchronized with each other.

[0006]

In the LSI tester of the present invention, the code memory provided on the digital module side outputs the analog module to the analog module, and the analog module and the digital module are controlled by two different controllers. I am trying to synchronize the modules.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration block diagram of an LSI tester showing an embodiment of the present invention. In the figure, 1 is a test system controller for controlling the entire apparatus, 2 is a module controller for controlling a digital module 20, and 3 is a module controller for controlling an analog module 30. is there.

The test system controller 1 loads an object file obtained by compiling a test program to each of the module controllers 2 and 3 and then loads each module.
The controller 2 or 3 outputs the control data from the loaded object file to the digital module 20 and the analog module 30 according to the sequence number specified by the test system controller 1. .

In the digital module 20, a microcode memory 21 stores microcodes such as no operation (hereinafter referred to as NOP) and jump (hereinafter referred to as JUMP). 22 is a DUT
A digital pattern memory in which a digital pattern for testing 40 is stored, and a test signal is output to the DUT 40 based on the address designated by the address generation sequencer 23. The code memory 24 is a digital module based on the address output from the address generation sequencer 23.
A code synchronized with the module 20 is output to the analog module 30.

In the analog module 30, 31,
A sequence generation circuit 32 outputs the stored start address and stop address to the address generation counters 33 and 34 in accordance with the code output from the code memory 24. The address generation counters 33 and 34 count up the address from the start address designated by the sequence generation circuit to the stop address one count at a time and output it to the analog pattern memories 35 and 36. The analog pattern memories 35 and 36 output the pattern data stored based on the addresses designated by the address generation counters 33 and 34.

Incidentally, the pattern of the analog pattern memory 35.
The data is output to the DUT 40 as it is, and the pattern data of the analog pattern memory 36 is the DA converter 3.
It is output to the DUT 40 via 7.

2A and 2B are time charts for explaining the operation of the LSI tester of the present invention. FIG. 2A shows the microcode output from the microcode memory 21, and FIG. 2B shows the address generation sequencer 23. The address to be output, (C) is the code output from the code memory 24, (D) is the clock signal CLK for synchronizing the digital module 20, and (E) is the digital pattern output from the digital pattern memory 22. −
And (F) are analog patterns output from the analog pattern memories 35 and 36.

(1) The microcode memory 21 outputs a NOP instruction to the address generation sequencer 23 in response to the input of the clock signal CLK. (2) The address generation sequencer 23 outputs the address "1" to the digital pattern memory 22 and the code memory 24 based on the NOP instruction of the microcode memory 21. (3) The digital pattern memory 22 has an address generation
The digital pattern D1 is output to the DUT 40 based on the address "1" designated by the counter 23.

(4) The microcode memory 21 again generates the NOP instruction with the next clock signal CLK.
It outputs to the Kensa 23. (5) The address generation sequencer 23 outputs the address "2" to the digital pattern memory 22 and the code memory 24 based on the NOP instruction of the microcode memory 21. (6) The digital pattern memory 22 uses the address generation
The digital pattern D2 based on the address "2" designated by the counter 23 is output to the DUT 40, and the code memory 2
Reference numeral 4 designates the code # 1 based on the address designated by the address generation sequencer 23 as the sequence of the analog module 30.
It outputs to the frequency generation circuits 31 and 32. (7) The analog module 30 is a sequencer generation circuit 3
An analog pattern is output from the analog pattern memory 35 based on the data 1 and 32. (8) After that, the processes of (1) to (7) are repeated for each NOP instruction and JUMP instruction.

FIG. 3 is a diagram for explaining the operation on the analog module side, and shows the relationship between the structure of the analog pattern memory and the address. The numbers in the figure correspond to the configuration shown in FIG.

When the code memory 24 designates the code # 1, the sequencer generation circuits 31 and 32 designate the start address n1 and the stop address n2 to the address generation counters 33 and 34, respectively. The address generation counters 33 and 34 generate the address sequence generation circuits 31 and 3, respectively.
It counts up by one count from the start address n1 designated by 2 to the stop address n2 and outputs it to the analog pattern memories 35 and 36.

The analog pattern memories 35 and 36, based on the addresses of the address generation counters 33 and 34,
The pattern data is output to the DUT 40. in this way,
A similar process is repeated for code # 2.

[0018]

As described above in detail, the L of the present invention
The SI tester is a cord provided on the digital module side.
Since the analog module and the digital module are synchronized by the code of the memory, even when the analog module and the digital module are controlled by the two controllers, the accuracy is high. And it can synchronize at high speed. Therefore, LSI measurement can be performed at high speed and with high accuracy.

[Brief description of drawings]

FIG. 1 is a configuration block diagram of an LSI tester showing an embodiment of the present invention.

FIG. 2 is a time chart explaining the operation of the LSI tester of the present invention.

FIG. 3 is an explanatory diagram of an operation on the analog module side.

[Explanation of symbols]

 1 Test System Controller 2, 3 Module Controller 20 Digital Module 24 Code Memory 30 Analog Module 31, 32 Sequence Generation Circuit 40 DUT

Claims (1)

[Claims] 1. An LSI tester in which a digital module and an analog module are controlled by different controllers, an upper test system controller which loads a test program to the controller, and A code memory for outputting a code synchronized with the analog module based on the address of the address generator of the digital module, and a code memory for the analog module based on the code of the code memory. A sequence test circuit for designating an address in an address generator is provided so that the digital module and the analog module are synchronized with each other.