JP3778050B2 - Semiconductor integrated circuit test equipment - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit test apparatus , and more particularly to a semiconductor integrated circuit test apparatus for testing a semiconductor integrated circuit in which analog circuits and digital circuits are mixed.
[0002]
[Prior art]
A semiconductor integrated circuit test apparatus (so-called IC tester) determines a pass / fail by comparing a signal obtained when a test pattern is applied to a semiconductor integrated circuit to be tested with a predetermined expected value. Tests whether semiconductor integrated circuits are good or bad. In recent years, semiconductor integrated circuits are often hybridized mainly due to demands for high functionality and miniaturization, and those in which analog circuits and digital circuits are mixed have been developed.
[0003]
FIG. 3 is a block diagram showing a configuration of a conventional semiconductor integrated circuit test apparatus for testing a semiconductor integrated circuit in which analog circuits and digital circuits are mixed. The conventional semiconductor integrated circuit test apparatus shown in FIG. 3 includes a control processing device 50, one digital measurement system 60, and three analog measurement systems 70a to 70c. The control processor 50, the digital measurement system 60, and the analog measurement systems 70a to 70c are connected via a control bus B. The reason why a plurality of analog measurement systems are provided as in the analog measurement systems 70a to 70c is that an analog circuit that can be divided into a plurality of parts is provided in a semiconductor integrated circuit as an object to be tested.
[0004]
The control processing device 50 sets test conditions for the digital measurement system 60 and the analog measurement systems 70a to 70c via the control bus B, transfers a test pattern, generates a trigger signal for starting a test, and Control for taking in test results from the digital measurement system 60 and the analog measurement systems 70a to 70c is performed.
[0005]
The digital measurement system 60 includes a pattern storage circuit 61 and a pattern generator 62. The pattern storage circuit 61 stores a test pattern transferred from the control processor 50 via the control bus B (this test pattern is a programmed microcode). The pattern generator 62 reads the micro code stored in the pattern storage circuit 61, and applies the digital pattern to the semiconductor integrated circuit as the object to be tested while executing the instruction included in the micro code.
[0006]
In addition to the control instructions for the digital measurement system 60, the micro code includes control instructions for the analog measurement systems 70a to 70c, and the pattern generator 62 executes the control instructions for the analog measurement systems 70a to 70c. If so, an analog measurement system control signal S50 and an interrupt signal S51 are generated. The analog measurement system control signal S50 and the interrupt signal S51 generated by the pattern generator 62 are input to the analog measurement systems 70a to 70c.
[0007]
The analog measurement systems 70a to 70c have the same configuration as each other, and include an arithmetic processor (digital signal processor) 71, a storage circuit 72, a storage circuit 73, an A / D converter 74, and a D / A converter 75. Consists of. Since the internal configurations of the analog measurement systems 70a to 70c are the same, the analog measurement system 70a will be described below.
[0008]
The arithmetic processor 71 is connected to the control processing device 50 via the control bus B. The arithmetic processor 71 is also connected to the pattern generator 62, and receives the analog measurement system control signal S50 and the interrupt signal S51 output from the pattern generator 62. Further, a signal line 75a is connected, and a digital response signal output from the semiconductor integrated circuit to be tested is input. The arithmetic processor 71 in the analog measurement system 70b is digitally output from the semiconductor integrated circuit under test via the signal line 75b, and the arithmetic processor 71 in the analog measurement system 70c is output via the signal line 75c. A response signal is input.
[0009]
The arithmetic processor 71 connected as described above sets test conditions by the control processor 50, decodes the content of the analog measurement system control signal S50 based on the interrupt signal S51 output from the pattern generator 62, Perform processing according to the content. The above processing is performed in synchronization with the digital measurement system 60 and the analog measurement system 70a by the interrupt signal S51 output from the pattern generator 62 provided in the digital measurement system 60. This is because the analog measurement systems 70a to 70c perform the simultaneous measurement of the analog circuits in the semiconductor integrated circuit divided into two.
[0010]
The storage circuits 72 and 73 are arranged on the address space of the arithmetic processor 71, the storage circuit 72 stores the digital signal output from the A / D converter 74, and the storage circuit 73 is output from the arithmetic processor 71. Store digital signals. The A / D converter 74 is connected to one analog circuit provided in the semiconductor integrated circuit, and converts an analog signal output from the analog circuit into a digital signal. The D / A converter 75 is connected to an analog circuit of the same section as the analog circuit to which the A / D converter 74 is connected, converts the digital signal stored in the storage circuit 73 into an analog signal, and outputs the analog signal. To do.
[0011]
In the above configuration, when a trigger signal for starting a test is output from the control processing device 50, the pattern generator 62 sequentially reads out the microcode from the pattern storage circuit 61 and executes the instruction written in the microcode. However, a digital pattern is applied to the semiconductor integrated circuit to be tested. Further, the control instruction for the analog measurement systems 70a to 70c included in the micro code is executed, and the analog measurement system control signal S50 and the interrupt signal 51 are generated for all the analog measurement systems 70a to 70c.
[0012]
When the interrupt signal S51 is input, the arithmetic processors 71 in the analog measurement systems 70a to 70c decode the content of the analog measurement system control signal S50 and execute processing corresponding to the content. These two signals enable the analog measurement systems 70a to 70c to synchronize between the digital measurement system 60 and the analog measurement system and to simultaneously measure a plurality of test samples.
[0013]
In the micro code for controlling the analog measurement systems 70a to 70c, for example, a command for taking a digital response from a test sample through the signal lines 75a to 75c, and the analog measurement systems 70a to 70c are prepared. A command for instructing the A / D converter 74 to start conversion, a command for causing the D / A converter 75 to generate a voltage, and the like are prepared.
[0014]
For example, in the case of an instruction for taking in a digital response from a semiconductor integrated circuit as a test target, the arithmetic processor 71 arranged in the analog measurement systems 70a to 70c receives a digital signal from the semiconductor integrated circuit as a test target. Responses are fetched via the signal lines 75a to 75c, and real-time processing such as changing the output voltage of the D / A converter 75 can be performed based on the fetched digital responses.
[0015]
[Problems to be solved by the invention]
By the way, in general, the measurement time of the analog measurement system is longer than that of the test of the digital measurement system. In the digital measurement system, a short pulse of about several nanoseconds can be sequentially applied to a semiconductor integrated circuit to be tested for testing. However, in the analog measurement system, since the response times of the A / D converter 74 and the D / A converter 75 are slow, the number of test patterns that can be given to a semiconductor integrated circuit as an object to be tested per unit time is limited. Inevitably, the test time will be longer.
[0016]
Further, the conventional semiconductor integrated circuit test apparatus shown in FIG. 3 only provides the same analog measurement system control signal S50 and interrupt signal S51 from the pattern generator 62 to the analog measurement systems 70a to 70c. Can not. Therefore, the analog measurement systems 70a to 70c can only test the same test item at the same time. On the other hand, a plurality of analog circuits provided inside a semiconductor integrated circuit to be tested are often designed so that different operations can be performed simultaneously, and the required test items are also different. There is.
[0017]
Therefore, when testing a semiconductor integrated circuit provided with a plurality of analog circuits using a semiconductor integrated circuit testing apparatus having a plurality of analog measurement systems, the same operation is simultaneously performed for all analog measurement systems. When the test is performed, the test efficiency is poor, and the test time is prolonged, which increases the cost required for the test.
[0018]
The present invention has been made in view of the above circumstances, and it is possible to efficiently test a semiconductor integrated circuit in which analog circuits and digital circuits are mixed in a short time, thereby reducing the cost required for the test. An object of the present invention is to provide a semiconductor integrated circuit testing apparatus that can be used.
[0019]
[Means for Solving the Problems]
In order to solve the above problems, a semiconductor integrated circuit test apparatus of the present invention is a semiconductor integrated circuit test apparatus for testing a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed, and is provided in the semiconductor integrated circuit. A plurality of analog measurement systems (40a to 40c) for testing the analog circuit, a digital measurement system (20) for testing the digital circuit provided in the semiconductor integrated circuit, and the plurality of analogs Control means (30) for individually controlling the operation of the measurement system (40a to 40c), and the control means (30) includes a decoding circuit for decoding the control pattern output from the digital measurement system (20). comprise configured, and wherein the supplying a signal obtained by decoding in the decoding circuit in the analog measurement system (40a to 40c), respectively To have.
According to the present invention, by separately controlling the analog measurement system by controlling the control means, different tests can be simultaneously performed on the analog circuit in the semiconductor integrated circuit. The mixed semiconductor integrated circuits can be efficiently tested in a short time, and as a result, the cost required for the test can be reduced.
In the semiconductor integrated circuit test apparatus of the present invention, the decoding circuit operates the plurality of analog measurement systems (40a to 40c) according to the control pattern (S1) output from the digital measurement system (20). Are controlled to be the same.
In the semiconductor integrated circuit test apparatus of the present invention, the digital measurement system (20) stores a micro code including a test pattern to be given to the analog circuit and the digital circuit provided in the semiconductor integrated circuit. A test pattern to be applied to the digital circuit provided in the semiconductor integrated circuit is generated according to the memory circuit (22) and the microcode read from the pattern memory circuit (22), or the analog measurement system And a pattern generator (24) for generating a control pattern (S1) for controlling at least one of (40a to 40c).
In the semiconductor integrated circuit test apparatus of the present invention, the analog measurement system (40a to 40c) is synchronized with a digital response signal output from the semiconductor integrated circuit by the test of the digital measurement system (20). It is characterized by conducting a test.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor integrated circuit test apparatus and method according to an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention. As shown in FIG. 1, the semiconductor integrated circuit test apparatus according to the present embodiment includes a control processing apparatus 10, one digital measurement system 20, a pattern decode circuit 30, and three analog measurement systems 40a to 40c. . The control processing device 10, the digital measurement system 20, the pattern decoding circuit 30, and the analog measurement systems 40a to 40c are connected via a control bus B. The reason why a plurality of analog measurement systems are provided as in the analog measurement systems 40a to 40c is that an analog circuit that can be divided into a plurality of parts is provided in a semiconductor integrated circuit as an object to be tested. Further, the number of analog measurement systems 40a to 40c is not limited to three, and an arbitrary number can be provided.
[0021]
The control processing device 10 sets test conditions for the digital measurement system 20, the pattern decode circuit 30, and the analog measurement systems 40a to 40c via the control bus B, and transfers test patterns and starts test. Generation of a trigger signal and control for capturing test results from the digital measurement system 20 and the analog measurement systems 40a to 40c are performed.
[0022]
The digital measurement system 20 includes a pattern storage circuit 22 and a pattern generator 24. The pattern storage circuit 22 controls the test pattern (this test pattern is a programmed microcode) and the analog measurement systems 40a to 40c transferred from the control processor 10 via the control bus B. The external control microcode is stored.
[0023]
The pattern generator 24 reads the microcode stored in the pattern storage circuit 22 or the microcode for external control, and executes the instruction contained in the microcode while digitally writing it to the semiconductor integrated circuit to be tested.・ Apply a pattern. When the pattern generator 24 reads the external control micro code, the pattern generator 24 outputs the external control micro code S1 for controlling the analog measurement systems 40a to 40c to the pattern decoding circuit 30. The external control microcode S1 corresponds to a control pattern according to the present invention.
[0024]
The pattern decoding circuit 30 decodes the external control microcode S1 output from the pattern generator 24, and at least one of the analog measurement system control signals S10 to S12 and the interrupt signals S20 to S22 according to the decoding result. Output at least one of the following. The analog measurement system control signal S10 and the interrupt signal S20 are input to the analog measurement system 40a, and the analog measurement system control signal S11 and the interrupt signal S21 are input to the analog measurement system 40b, and the analog measurement system control signal S12 and the interrupt signal S22. Are input to the analog measurement system 40c. Here, a specific example of the decoding result of the pattern decoding circuit 30 will be described.
[0025]
FIG. 2 is a chart showing a specific example of the decoding result of the pattern decoding circuit 30. As shown in FIG. 2, the external control micro code is composed of a 4-bit external control address, and the analog measurement system control signals S10 to S12 and the interrupt signals S20 to S22 are composed of 8-bit external control execution instructions. .
[0026]
The analog control systems 40a to 40c are assigned as different addresses to the external control address, and the external control execution command for defining the operation of the analog measurement systems 40a to 40c is assigned to each external control address. Execution instructions such as generation of analog measurement system control signals S10 to S12 and generation of interrupt signals S20 to S22 for the arithmetic processors provided in the respective analog measurement systems 40a to 40c are assigned.
[0027]
The pattern decoding circuit 30 outputs the analog measurement system control signals S10 to S12 and the interrupt signals S20 to S22 to the analog measurement systems 40a to 40c individually according to the decoding result of the micro code S1 for external control. The measurement systems 40a to 40c are individually controlled. As shown in FIG. 2, when “1001” is input as the external control address, the pattern decode circuit 30 receives analog measurement system control signals S10 to S12 and interrupts for the analog measurement systems 40a to 40c. It is also possible to output the signals S20 to S22 and control the analog measurement systems 40a to 40c to have the same operation. This makes it possible to maintain compatibility with a conventional semiconductor integrated circuit test apparatus.
[0028]
The analog measurement systems 40a to 40c have the same configuration as each other, and include an arithmetic processor (digital signal processor) 41, a storage circuit 42, a storage circuit 43, an A / D converter 44, and a D / A converter 45. Consists of. Since the internal configurations of the analog measurement systems 40a to 40c are the same, the analog measurement system 40a will be described below.
[0029]
The arithmetic processor 41 is connected to the control processing device 10 via the control bus B. The arithmetic processor 41 in the analog measurement system 40a is connected to the pattern decode circuit 30, and receives the analog measurement system control signal S10 and the interrupt signal S11 output from the pattern decode circuit 30. Further, a signal line 35a is connected, and a digital response signal output from the semiconductor integrated circuit to be tested is input. The arithmetic processor 41 in the analog measurement system 40b is digitally output from the semiconductor integrated circuit under test via the signal line 35b, and the arithmetic processor 41 in the analog measurement system 40c is output via the signal line 35c. A response signal is input.
[0030]
The arithmetic processor 41 connected as described above sets test conditions by the control processing device 10 and decodes the content of the analog measurement system control signal S10 based on the interrupt signal S20 output from the pattern generator 24. Perform processing according to the content. As described above, the digital measurement system 20 and the analog measurement are performed by the interrupt signal S20 obtained by decoding the external control microcode S1 output from the pattern generator 24 by the pattern decoding circuit 30. This is to achieve synchronization with the system 40a.
[0031]
The storage circuits 42 and 43 are arranged on the address space of the arithmetic processor 41, the storage circuit 42 stores the digital signal output from the A / D converter 44, and the storage circuit 43 is output from the arithmetic processor 41. Store digital signals. The A / D converter 44 is connected to one analog circuit provided in the semiconductor integrated circuit, and converts an analog signal output from the analog circuit into a digital signal. The D / A converter 45 is connected to an analog circuit of the same section as the analog circuit to which the A / D converter 44 is connected, converts the digital signal stored in the storage circuit 43 into an analog signal, and outputs the analog signal. To do.
[0032]
In the above configuration, when a trigger signal for starting a test is output from the control processing device 10, the pattern generator 24 sequentially reads out the microcode from the pattern storage circuit 22 and executes the instruction written in the microcode. However, a digital pattern is applied to the semiconductor integrated circuit to be tested. The pattern generator 24 performs the above processing and outputs the external control microcode S 1 stored at the same address of the pattern storage circuit 22 to the pattern decoding circuit 30.
[0033]
The pattern decode circuit 30 decodes the external control microcode S1 output from the pattern generator 24, determines an analog measurement system to be controlled according to the decoding result, and determines the determined analog measurement system. At least one of the analog measurement system control signals S10 to S12 and at least one of the interrupt signals S20 to S22 are output.
[0034]
For example, when the control address of the external control microcode is “0001” and the external control effective instruction is “00000010”, the pattern decode circuit 30 interrupts the computation dedicated processor 41 in the analog measurement system 40a. The signal S20 is output. In response to this instruction, the processor 41 dedicated to computation in the analog measurement system 40a performs processing such as taking in a digital response from a semiconductor integrated circuit to be tested through the signal line 35a.
[0035]
At this time, since the interrupt signals S21 and S22 are not output from the pattern decode circuit 30 to the other analog measurement systems 40b and 40c, only the analog measurement system 40a operates the pattern generator 24, that is, the digital measurement system. It can operate in synchronization with the 20 operations. As described above, in this embodiment, each analog measurement system 40a to 40c can be individually operated in synchronization with the operation of the digital measurement system 20, and therefore different operations are simultaneously performed on the analog measurement systems 40a to 40c. Therefore, an analog circuit provided in a semiconductor integrated circuit as an object to be tested can be measured under different operations.
[0036]
Further, the external control micro code S1 is used for the analog measurement systems 40a to 40c, the analog measurement system control signals S10 to S12, and the interrupt signal S20 to the arithmetic dedicated processor 41 arranged in each analog measurement system 40a to 40c. By outputting S22, the analog measurement systems 40a to 40c can be simultaneously made to perform the same operation.
[0037]
The semiconductor integrated circuit test apparatus and method according to the embodiment of the present invention have been described above. However, the present invention is not limited to the above embodiment, and can be freely changed within the scope of the present invention.
[0038]
【The invention's effect】
As described above, according to the present invention, by separately controlling the analog measurement system by controlling the control means, different tests can be simultaneously performed on the analog circuits in the semiconductor integrated circuit. A semiconductor integrated circuit in which a circuit and a digital circuit are mixed can be efficiently tested in a short time, and as a result, the cost required for the test can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor integrated circuit test apparatus according to an embodiment of the present invention.
FIG. 2 is a chart showing a specific example of the decoding result of the pattern decoding circuit 30;
FIG. 3 is a block diagram showing a configuration of a conventional semiconductor integrated circuit test apparatus for testing a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed.
[Explanation of symbols]
20 Digital measurement system 22 Pattern storage circuit 24 Pattern generator 30 Pattern decode circuit (control means, decode circuit)
40a-40c Analog measurement system S1 Micro code for external control (control pattern)

Claims (4)

A semiconductor integrated circuit test apparatus for testing a semiconductor integrated circuit in which an analog circuit and a digital circuit are mixed,
A plurality of analog measurement systems for testing the analog circuit provided in the semiconductor integrated circuit;
A digital measurement system for testing the digital circuit provided in the semiconductor integrated circuit;
Control means for individually controlling the operations of the plurality of analog measurement systems, and the control means includes a decoding circuit for decoding a control pattern output from the digital measurement system, and the decoding circuit decodes the control pattern. A semiconductor integrated circuit test apparatus, characterized in that the processed signal is supplied to each of the analog measurement systems . The decode circuit, in response to said control pattern output from the digital measurement system, a semiconductor integrated circuit testing apparatus of claim 1, wherein said plurality of operation of the analog measurement system and controlling so as to be identical. The digital measurement system includes a pattern storage circuit for storing a micro code including a test pattern to be applied to the analog circuit and the digital circuit provided in the semiconductor integrated circuit;
A test pattern to be applied to the digital circuit provided in the semiconductor integrated circuit is generated according to a micro code read from the pattern storage circuit, or a control pattern for controlling at least one of the analog measurement systems is provided. the semiconductor integrated circuit test apparatus according to claim 1, characterized in that it comprises a pattern generator for generating. The analog measurement system, any one of claims 1 to 3, characterized in that the test is conducted in synchronization with the digital response signal output from the semiconductor integrated circuit by the test of the digital measuring system The semiconductor integrated circuit test apparatus described in 1.

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