JPH0585875B2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to an analog LSI test device, and in particular, in a functional test of an analog LSI, data output from a device under test is compared with expected value data, and the comparison result is The present invention relates to an improvement of a fail memory device having a function of determining the quality of a device under test based on the comparison result and selecting and outputting new pattern data for the next test according to the comparison result.

(Conventional technology) Traditionally, computers have been used to
There is analog LSI testing equipment that tests for abnormalities in LSI operation. FIG. 4 is a conceptual configuration diagram showing an example of this type of analog LSI test equipment. In the figure,
A main control device 1 including a computer controls a plurality of sub-control devices 2 ₁ , 2 ₂ , , 2 _o . Each sub-control device is connected to various modules 4 ₁ , 4 ₂ , . . . 4m (modules connected to sub-control devices other than the sub-control device 2 ₁ are not shown).
A test head 5 on which a device under test is mounted is connected to this module. An operator terminal 3 through which an operator inputs necessary commands is connected to the sub-control device.

In such a configuration, it is possible to run a desired test program in the main controller 1, apply predetermined pattern data to the device under test via the sub-control device and module, and then import the data generated thereafter. The test results and the like can be displayed on the display device 7 as appropriate.

The sub-control device 2 ₁ has a fail memory device having the following functions. That is, according to the program executed by the main controller 1, predetermined pattern data is output to the device under test via the module, and then data input from the device under test is input via the module. It is compared with an expected value, and the comparison result is stored in a memory together with the pattern data and the address where the pattern data is stored. At the same time, pattern data to be output next is determined according to the comparison result.

(Problems to be Solved by the Invention) In this case, there is a non-negligible delay time between when pattern data is given to the device under test and when output data is received. The delay in the response time of the measurement target can be adjusted by adjusting the data input/output time interval on the executing program, but the delay on the test equipment side (called system delay) can be adjusted within the equipment. I needed to.

However, such system delay adjustment is generally difficult, and there is a drawback that delicate and complicated adjustment is required each time the type of sub-control device changes.

SUMMARY OF THE INVENTION An object of the present invention is to provide an analog LSI test device equipped with a fail memory device that can easily adjust the system delay with a simple and inexpensive configuration.

In order to achieve such an object, the present invention includes means for generating a multiphase clock by applying a time delay (variable) to the basic clock provided in the device, and latching pattern data and its data storage address. It is equipped with a multi-stage delay latch means, and a memory for storing comparison results (pass/fail data) between measured data and expected value data, as well as pattern data given via the delay latch means and the data storage address. The present invention is characterized in that the system delay is corrected by adjusting the phase clock, and the comparison result, pattern data, and address can be latched in the same phase and taken into the memory.

(Example) The present invention will be explained in detail below using the drawings. FIG. 1 is a block diagram showing an embodiment of a fail memory device portion of an analog LSI testing apparatus according to the present invention. In the figure, a pattern memory 21 has pattern data set in advance, and outputs pattern data at an address specified by a CPU (not shown) via a bus 20. A formatter circuit 22 converts the output data of the pattern memory 21 into a data format suitable for the module ₄₁ . The output of the formatter circuit 22 is applied to the module 4 ₁ via a driver 23 .

A memory 24 stores input/output switching data, and provides data output from this memory to the driver 23 to control its output.

Reference numeral 25 denotes an expected value memory, which stores expected values for measured data. 26 is a comparator,
The measured data obtained from the module ₄₁ is compared with the data in the expected value memory 25, and a pass/fail result is obtained: if it falls within the expected value, it is acceptable, and if it exceeds the expected value, it is defective.

Reference numeral 27 denotes a delay adjustment circuit that corrects the system delay necessary when storing the comparison results of the comparator 26, pattern addresses, pattern data, etc. in the memory. More details will be described later.

28 is a memory for storing pattern addresses and pattern data, and 29 is a memory for storing the above-mentioned comparison results. These memories are on bus 2
It is connected to 0 and can be accessed by the CPU.

FIG. 2 shows an embodiment of the delay adjustment circuit 27 and part of its peripheral circuits. In the figure, 61 is a multiphase clock generation circuit which receives the system basic clock CLK of this device, delays this clock as appropriate, and generates a multiphase clock. Here, a case of four phases (C ₁ , C ₂ , C ₃ , C ₄ ) will be exemplified. Reference numeral 62 denotes a delay latch group whose delay amount can be adjusted. For example, it is composed of a multi-stage delay latch group, which latches address data and pattern data at the timing of clock _C1 , transfers them to the next stage latch at clock _C2 , and then latches them at clock C2. ₃ latches to the final stage. In this way, the address data and pattern data can be sent and output from the time of clock _C1 to the time of clock _C3 . This final stage latch data is taken into latch 63 at the timing of clock _C4 . Also, the latch 66 has a clock.
The comparison results from the module are imported at timing _C4 .

64 is clock _C4 or strobe STRB
This is a counter that operates based on . 65 is a strobe for memory writing in response to clock _C4
This is a strobe generation circuit that creates STRB. Starting and stopping of strobe generation by this strobe generating circuit is controlled by the output of the counter 64. This strobe STRB causes the data in the register 63 to be written into the memory 28 and the data in the register 66 to be written into the memory 29.

The operation in such a configuration will be explained below with reference to the time chart of FIG. Note that only the operation related to the delay, which is a feature of the present invention, will be described here. The multiphase clock generator 61 receives the basic clock CLK shown in FIG. 3A and generates four sets of clocks shown in FIG.
The delay times DL ₁ , DL ₂ , DL ₃ , and DL ₄ can be adjusted according to the device.

The delay latch group 62 latches the pattern address and pattern data (FIG. 3) applied via the bus 20 to the first stage latch at the timing of the clock _C1 . The next clock _C2 moves to the next stage latch, and the clock _C3 sends it to the final stage latch.

At the next rising edge of clock _C4 ,
The output of delay latch group 62 is loaded into latch 63, and the comparison result is loaded into latch 66. On the other hand, the counter 64 receives the clock _C4 and sends a control signal to the strobe generation circuit 65 to start strobe generation. After receiving this control signal, the strobe generation circuit 65 lowers its output to the "L" level in synchronization with the clock CLK. This output changes the output of the counter 64 into a control signal that causes the strobe generation circuit 65 to stop strobe generation.

In this way, a strobe like the one shown in Figure 3
STRB is generated and the data of each latch 63 and 66 is stored in memories 28 and 29 by this STRB. That is, the memory 28 contains the clock C ₁
The latched pattern address and pattern data (FIG. 3) are written at the rising timing of clock C4, and the comparison result (FIG. ₃ ) latched at the rising timing of clock C4 is written into the memory 29.

With such a delay method, as shown in FIG. 3, the system delay _DLS from generation of pattern data to acquisition of comparison results is corrected.

If a fail memory device with such a configuration is used, even if the system delay changes in different devices, the system delay can be easily corrected by simply adjusting the delay amount of the multiphase clock generation circuit within the fail memory device. be able to.

(Effects of the Invention) As explained above, according to the present invention, a multi-phase clock is created from one basic clock and the phase of each clock is adjusted to correct the system delay and match the data under measurement. The result of the comparison with the expected value can be taken into the fail memory together with the pattern address and pattern data when the pattern was generated. According to the configuration of the present invention,
In addition to being able to easily adjust the system delay, there are advantages in that the delay adjustment means can be constructed at low cost.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of the fail memory device portion of the analog LSI test equipment according to the present invention, FIG. 2 is a diagram illustrating an embodiment of the delay adjustment circuit, and FIG. 3 explains the operation. FIG. 4 is a conceptual configuration diagram showing an example of a conventional analog LSI test device. 1... Main control device, 2 ₁ to 2n... Sub control device,
4 ₁ to 4m...Module, 5...Test head,
6...Device under test, 20...Bus, 21...
Pattern memory, 22...formatsuta, 23...
...Driver, 24, 28, 29...Memory, 25
... Expected value memory, 26 ... Comparator, 27 ... Delay adjustment circuit, 61 ... Multiphase clock generator,
62...Delay latch group, 63, 66...Latch, 64...Counter, 65...Strobe generation circuit.

Claims (1)

[Claims] 1. It is possible to use a computer to execute a predetermined program for testing a device under test while switching its internal state according to the test results, and to determine whether the device under test is functioning properly. analog
The LSI test equipment includes a pattern memory in which data patterns to be applied to the device under test are stored, an expected value memory in which expected values corresponding to the measured data are stored in advance, and a A comparison value that compares the expected value from the expected value memory and outputs a pass/fail result, and a polyphase clock that generates multiphase clocks with different phases from the basic clock, and each phase of which is configured to be adjustable. a generator; a delay latch means having a multistage latch for shifting input data using the multiphase clock, and outputting pattern data and its storage address with a time delay according to the multiphase clock; and the delay latch means. a latch that captures the data pattern and its storage address output via the multiphase clock in synchronization with the multiphase clock; a latch that captures the comparison result from the comparator in synchronization with the multiphase clock; 1. An analog LSI test device comprising a memory for storing the contents of a latch, and capable of correcting a system delay by adjusting the phase of the multiphase clock.