JPS61234377A - Analog lsi tester - Google Patents

Abstract

PURPOSE:To enable the adjustment of a system delay, by correcting the system delay with the adjustment of multi-phase clocks to bring the results of the comparison between data to be measured and an expected value into a memory along with a pattern data and an address data. CONSTITUTION:A multi-phase clock generation circuit 61 receives a system base clock CLK to generate a multi-phase clock by delaying the base clock properly. A group 62 of delay latches with the delay value adjustable is made up of a group of multi-stage delay latches, for instance, to latch address data and pattern data at the timing of a clock C1, shifted to the latching at the next stage by a clock C2 and finally, it is latched by a clock C3. Thus, address data and pattern data can be sent from the time of the clock C1 to the time of the clock C3 to output. The latch data at the final stage is taken into a latch 63 at the timing of the clock C4. The results of comparison are inputted into a latch 66 from a timing module of the clock C4.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to an analog LSI test device, and in particular, in a functional test of an analog LSI, data output from a device under test is compared with expected value data, and the results of the comparison are used. The present invention relates to an improvement of a fail memory device having a function of determining the quality of a device under test based on the comparison result, and selecting and outputting new pattern data for the next test according to the comparison result.

(Prior Art) Conventionally, there has been an analog LSI testing device that utilizes a computer to test abnormalities in the operation of an analog LSI. Fourth
The figure is a conceptual configuration diagram showing an example of this type of analog LSI testing device. In the figure, a main control device 1 including a computer has a plurality of sub-control devices 2 + + 22 + +
+2n control. Each sub-control device is connected to various modules 41 + 42 + + r 4m (modules connected to sub-control devices other than the sub-control device 2I are not shown). A test head 5 on which a device under test is mounted is connected to this module.

An operator terminal 3 through which an operator inputs necessary commands is connected to the sub-control device.

In such a configuration, it is possible to run a desired test program in the main controller 1, give predetermined pattern data to the device under test via the sub-control device and module, and then import the data generated thereafter. The test results and the like can be displayed on the display device 7 as appropriate.

' The sub-control device 21 has a fail memory device having the following functions. That is, according to the program executed by the main controller 1, predetermined pattern data is output to the device under test via the module, and then data input from the device under test is imported via the module. It is compared with an expected value, and the comparison result is stored in a memory together with the pattern data and the address where the pattern data is stored. At the same time,
The pattern data to be output next is determined according to the comparison result.

(Problems to be Solved by the Invention) In this case, there is a non-negligible delay time between when pattern data is given to the device under test and when output data is received. Regarding the delay in response time of the measurement target, the data input/output time interval can be adjusted on the executing program side, but the delay time on the test equipment side (
system delay) had to be adjusted within the device.

However, it is generally difficult to adjust the system delay as described above, and there is a drawback that delicate and complicated adjustments are required each time the type of sub-control device changes.

The object of the present invention is to eliminate such drawbacks, and to provide an analog L with a fail memory device that allows system delay to be easily adjusted with a simple and inexpensive configuration.
Our purpose is to provide SI test equipment.

In order to achieve such an object, the present invention provides a means for generating a multi-phase clock by applying a time delay (variable) to the basic clock provided in the device, and a means for generating a multi-phase clock, and a means for generating a multi-phase clock, and pattern data and its data storage address. comprising a multistage delay latch means for latching, and a memory for storing comparison results (pass/fail data) between measured data and expected value data, pattern data given via the delay latch means, and the data storage address; The multiphase clock is rlI
The present invention is characterized in that the comparison result, pattern data, and address can be latched in the same phase and taken into the memory by correcting the system delay.

(Example) The present invention will be described in detail below using the drawings. FIG. 1 is a configuration diagram showing an embodiment of a 7-ile memory device portion of an analog LSI testing apparatus according to the present invention. In the same figure,
A pattern memory 21 has pattern data set in advance, and outputs pattern data at an address designated by a CPU (not shown) via the bus 20. A formatter circuit 22 converts the output data of the pattern memory 21 into a data format suitable for the module 41. The output of formatter circuit 22 is applied to module 41 via driver 23.

A memory 24 stores input/output switching data, and provides data output from this memory to the driver 23 to control its output.

Reference numeral 25 denotes an expected value memory, which stores expected values for measured data. 26 is a comparator, module 41
The measured data obtained from the above are compared with the data in the expected value memory 25, and a pass/fail result is obtained: if it falls within the expected value, it is acceptable, and if it exceeds the expected value, it is defective.

27 is a delay adjustment circuit that corrects the system delay necessary when storing the comparison result of the comparator 26, pattern address, pattern data, etc. in the memory.

More details will be described later.

28 is a memory for storing pattern addresses and pattern data, and 29 is a memory for storing the above-mentioned comparison results. These memories are connected to bus 20,
CPtJ can access it.

FIG. 2 shows an embodiment of the delay adjustment circuit 27 and part of its peripheral circuits. In the figure, 61 is a multiphase tarlock generation circuit which receives the system basic clock CLK of this device, delays this clock as appropriate, and generates a multiphase clock. Here, a case of four phases (C+, C2, C3, C4) is illustrated.

Reference numeral 62 denotes a delay latch group whose delay amount can be adjusted, for example, a multi-stage delay latch group, which latches address data and pattern data at the timing of clock C1, transfers them to the next stage latch at clock C2, and latches them at clock C2.
3 to latch to the final stage. In this way, address data and pattern data can be sent and output from the time of clock C1 to the time of clock C3. This final stage latch data is taken into the latch 63 at the timing of clock C4. Furthermore, the comparison result from the module is taken into the latch 66 at the timing of the clock C4.

64 is a counter operated by clock C4 or strobe ST'RB. 65 is a strobe generation circuit that receives the clock C4 and generates a strobe 5TRB for memory writing. Starting and stopping of strobe generation by this strobe generating circuit is controlled by the output of the counter 64. This strobe 5TRB allows the memory 28
The data in the register 63 is written into the memory 29, and the data in the register 66 is written into the memory 29.

The operation in such a configuration will be explained next with reference to the time chart of FIG. Note that only the operation related to the delay, which is a feature of the present invention, will be described here.

The multiphase clock generator 61 receives the basic clock CLK shown in (a) of FIG.
Generate phase clocks. Delay time DL+, DL
2, DLi, DLi can be adjusted according to the device.

The delay latch group 62 latches the pattern address and pattern data ((f) in FIG. 3) given via the bus 20 into the first stage latch at the timing of the clock C1.

At the next clock C2, it moves to the next stage latch, and clock C3
is sent to the final stage latch.

At the timing of the next rise of clock C4, the output of delay latch group 62 is taken into latch 63, and the comparison result is taken into latch 66. On the other hand, counter 64 receives clock C4 and sends a control signal to start strobe generation to strobe generation circuit 65. Strobe generation circuit 65
After receiving this control signal, it drops its output to the 'L' level at a timing synchronized with the clock CLK. This output changes the output of the counter 64 into a control signal that causes the strobe generation circuit 65 to stop strobe generation.

In this way, the strobe 5TR as shown in FIG.
B is generated, and the data of each latch 63 and 66 is stored in the memories 28 and 29 by this 5TRB. That is, the pattern address and pattern data (see FIG. 3) latched at the rising timing of the clock C7 are written into the memory 28, and the memory 28 is written with the clock C4.
The latched comparison result (FIG. 3(G)) is written at the rising edge of .

With such a delay method, as shown in FIG. 3, the system delay D L s from generation of pattern data to acquisition of comparison results is corrected.

If you use a fail memory device with such a configuration, even if the system delay changes with different devices, you can easily adjust the system by simply adjusting the delay amount of the multiphase delay generation circuit in the fail memory device. Delay can be corrected.

(Effects of the Invention) As explained above, according to the present invention, a multi-phase clock is created from one basic clock and the phase of each clock is adjusted, thereby correcting the system delay and matching the data under measurement. The result of the comparison with the expected value can be taken into the fail memory together with the pattern address and pattern data when the pattern was generated. According to the configuration of the present invention, there are advantages in that the system delay can be easily adjusted and the delay adjustment means can be constructed at low cost.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a 7-way memory device portion of an analog LSI testing device according to the present invention, FIG. 2 is a diagram for explaining an embodiment of a delay adjustment circuit, and FIG. 3 is an operation diagram. FIG. 4 is a conceptual block diagram showing an example of a conventional analog LSI test device. 1... Main control device, 21-2n... Sub-control device, 4
1~4m...Module, 5...Test head, 6
...Device under test, 20...Bus, 21...Pattern memory, 22...Formatter, 23...Driver, 24.28.29...Memory, 25...Expected value memory, 26... Comparator, 27... Delay adjustment circuit, 61... Multiphase clock generator, 62... Delay latch group, 63. 66... Latch, 64...
Counter, 65... Strobe generation circuit.

Claims (1)

[Claims] An analog device that uses a computer to execute a predetermined program for testing a device under test while switching its internal state according to the test results, and determines whether the device under test is functioning properly. The LSI test equipment includes: a pattern memory in which data patterns to be applied to the device under test are stored; an expected value memory in which expected values corresponding to the measured data are stored in advance; A comparator that compares the expected value from the expected value memory and outputs a pass/fail result, and a multiphase clock that generates multiphase clocks with different phases from the basic clock and is configured so that each phase can be adjusted. a generator; a delay latch means having a multistage latch that shifts input data using the multiphase clock, and outputting pattern data and its storage address with a time delay according to the multiphase clock; and the delay latch means. a latch that captures the data pattern and its storage address output via the multiphase clock in synchronization with the multiphase clock; a latch that captures the comparison result from the comparator in synchronization with the multiphase clock; An analog LSI testing device comprising: a memory for storing the contents of a latch, and capable of correcting a system delay by adjusting the phase of the multiphase clock.