JPH08293734A - Waveform generator - Google Patents

Abstract

PURPOSE: To prevent the storage capacity of a waveform sequence data memory from being increased and further, to improve the degree of freedom for preparing the sequence of an output waveform. CONSTITUTION: Concerning a waveform generator for which a waveform sequence data memory 2 stores waveform generation control data containing the number of times of repeated generation of the output waveform and the start address and end address of this output waveform and the output waveform is generated from a waveform data memory 1 in prescribed order based on those waveform generation control data, the waveform generation control data in the waveform sequence data memory 2 are arbitrarily divided into groups. Then, a group sequence data memory 4 is provided in the high order of the waveform sequence data memory 2 and the group sequence data memory 4 stores group control data containing the number of times of repeated generation and the start address and stop address of each group concerning the respective groups of waveform generation control data divided into groups. Then, the waveform sequence data memory 2 is controlled by the group sequence data memory 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a waveform generator, and more specifically, when measuring electrical characteristics of an electric component, such as a circuit board on which the component is mounted, a plurality of measurement signals having different waveforms are used. The present invention relates to a waveform generator that generates in a predetermined order.

[0002]

2. Description of the Related Art Not only electrical components such as resistors, capacitors and coils, and semiconductors, but also circuits that combine them have their own unique characteristics, and their electrical characteristics can be measured or their quality can be accurately determined. In order to discriminate, it is necessary to apply a measurement signal corresponding to it.

FIG. 7 shows a conventional example of a waveform generator capable of generating various measurement signals in response to such demands. That is, the same waveform generator includes a waveform data memory 1 in which a plurality of arbitrary waveforms are stored as digital data, and a waveform sequence data memory 2 in which waveform generation control data such as the output order and the number of generations of these waveforms are stored. And an address generator 3 for giving the address specified by the waveform sequence data memory 2 to the waveform data memory 1.

Here, in the waveform data memory 1, as shown in FIG. 8, the data of the sine wave A is stored in the addresses 0 to 99, and the data of the rectangular wave B is stored in the addresses 100 to 199. However, when it is assumed that the data of the triangular wave C is stored at the addresses 200 to 299 respectively, and the waveforms A, B, and C are repeatedly output twice, three times, and once, respectively, the waveform sequence data is output. The waveform generation control data as shown in FIG. 9 is stored in the memory 2.

That is, the waveform sequence data memory 2
For each waveform A, B, C, 0-2, 3-
Three addresses 5, 5 to 8 are given, and the addresses 0, 3, 6 store therein the data of the number of repeated occurrences of each waveform as 2, 3, 1. And the address 1,
The start address of each waveform is 0,100,2 in 4 and 7.
00, respectively, and addresses 2, 5, 8
The end addresses 99, 199, and 299 of the respective waveforms are written in the.

The address generator 3 outputs a read address to the waveform data memory 1 in the order of the data of the waveform sequence data memory 2, whereby the waveform data is sequentially read from the waveform data memory 1, and the waveform data is read. Is converted into an analog signal by a D / A converter (not shown) and supplied to the component under test or the circuit.

[0007]

By setting the waveform generation control data in the waveform sequence data memory 2 in this way, desired waveforms can be generated in an arbitrary order. Pattern waveform (waveform A twice, waveform B three times and waveform C 1
In order to repeatedly generate the waveform sequence data memory 2, it is necessary to expand the memory area of the same waveform sequence data memory 2 and repeatedly write the same step at that address. In No. 2, there is a problem that a memory having a larger storage capacity and therefore a costly memory is required, which is not preferable.

The present invention has been made in order to solve the above-mentioned conventional problems, and its object is to increase the degree of freedom in creating a sequence of output waveforms without increasing the storage capacity of the waveform sequence data memory. It is an object of the present invention to provide a waveform generator capable of further improving the waveform.

[0009]

In order to achieve the above object, the present invention provides a waveform data memory in which digital data of a plurality of different output waveforms are stored for each designated address range, and a repetition of the output waveforms. A waveform sequence data memory that stores waveform generation control data including the number of occurrences and a start address and end address of the same output waveform, and the waveform data memory based on the waveform generation control data from the waveform sequence data memory. A first address generator for giving a read address of the output waveform, and the digital data of the output waveform is read out in a predetermined order from the waveform data memory according to the waveform generation control data of the waveform sequence data memory. Waveform generator that generates the output waveform In the above, the sequence control data in the waveform sequence data memory is arbitrarily grouped, and group sequence data is stored in which group control data including the number of repeated occurrences of each group and the start address and end address of the same group are stored. It is characterized by including a memory and a second address generator which outputs a read address of the waveform generation control data to the waveform sequence data memory based on the group control data.

In this case, when grouping the waveform generation control data in the waveform sequence data memory, it is preferable to group the waveform generation control data over a continuous predetermined address range.

Each of the waveform sequence data memory and the group sequence data memory has first and second latch circuits for holding the start address and the end address, respectively, and a third latch for holding the number of repetitions. A circuit, and the first
And the second address generator counts the number of coincidence outputs from the comparator that compares the address generated from the address generator with the end address held in the second latch circuit, and the count value is A counter circuit for supplying a stop signal to the address generator when the number of times of repetition of the third latch circuit is reached, the waveform sequence data memory and the first address generator, the group sequence data memory and the third sequence data memory. The two address generators preferably have the same circuit configuration.

[0012]

According to the above configuration, first, the number of times of repeated occurrence, the start address and the end address for each group are output from the group sequence data memory to the waveform sequence data memory via the second address generator. In response to this, a wave is output and the read address is output to the waveform data memory via the first address generator. As a result, the waveform data stored at the specified address is read from the waveform data memory.

Here, in the group sequence data memory, assuming that the number of repeated occurrences of a certain group is, for example, two, and the number of repeated occurrences of waveforms belonging to the group is set to three, for example, in the waveform sequence data memory. 3 × 2 from the waveform data memory
That is, the waveform data is continuously output 6 times.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. As shown in FIG. 1, in addition to the waveform data memory 1, waveform sequence data memory 2 and address generator 3 shown in FIG. A group sequence data memory 4 in which control data is arbitrarily grouped, and group control data including the number of repeated occurrences of each group and a start address and an end address of the same group is stored, and based on the group control data, The waveform sequence data memory 2 is provided with an address generator 5 that outputs a read address of the waveform generation control data. In order to distinguish the address generator 3 and the address generator 5, the former is given a first number and the latter is given a second number.

FIG. 2 shows a specific circuit block of this waveform generator. According to this, on the output side of the group sequence data memory 4, the first and second latch circuits 4a, which temporarily hold the start address and the end address output from the memory 4, respectively,
4b and a third latch circuit 4c for temporarily holding the number of times of repeated occurrence output from the memory 4 are connected.

Further, in relation to the second address generator 5, a comparator 5a for comparing an address generated from the address generator 5 with an end address held in the second latch circuit 4b and a match from the comparator 5a. A counter circuit 5b is provided which counts the number of outputs and supplies an operation stop signal to the second address generator 5 when the count value reaches the number of times the third latch circuit 4c is repeatedly generated.

The second address generator 5 is connected to the input side of the waveform sequence data memory 2, but is output from the same side of the group sequence data memory 4 to the output side of the waveform sequence data memory 2. First and second latch circuits 2a and 2 for temporarily holding a start address and an end address, respectively.
b is connected to a third latch circuit 2c that temporarily holds the number of times of repeated occurrence output from the memory 2.

Further, in relation to the first address generator 3, a comparator 3a for comparing an address generated from the address generator 3 with an end address held in the second latch circuit 2b and a match from the comparator 3a. A counter circuit 3b is provided which counts the number of outputs and supplies an operation stop signal to the first address generator 3 when the count value reaches the number of times the third latch circuit 2c is repeatedly generated.

As described above, in this embodiment, the group sequence data memory 4 and the second address generator 5, and the waveform sequence data memory 2 and the first address generator 3 have the same structure.

Also in this embodiment, the waveform data memory 1 stores the data of the respective waveforms A, B and C as shown in FIG.
Further, it is assumed that the waveform sequence data memory 2 also stores the waveform generation control data for the waveforms A, B, and C as shown in FIG.

By the way, according to this embodiment, the waveform generation control data is group 1 as shown in FIG.
And are grouped into 2. That is, as shown in FIG. 7A, the waveform A is independently set as the group 1, and the waveforms B and C are collectively set as the group 2.

Therefore, the respective data of the addresses 0 to 8 of the waveform sequence data memory 2 are sequentially given to the waveform data memory 1 via the first address generator 3, so that as shown in FIG. From the same waveform data memory 1, waveforms A, A, B, B,
The respective waveform data are output in the order of B and C. By grouping as described above, the waveforms A and A are grouped as 1 and the waveforms B, B, B and C are also formed.
Are controlled as group 2.

As described above, in order to control each waveform as a group, the group sequence data memory 4 stores group control data as shown in FIG. 4A, for example. That is, three addresses are assigned to each group, and the number of repeated occurrences, start address, and end address are set.

In this example, addresses 0 to 2 are assigned to group 1.
Is assigned to address 0 as “1” as the number of repeated occurrences of the same group 1, “0” as the start address of the same group 1 as address 1, and “2” as the end address of the same group 1 as address 2. Each is set.

Addresses 3 to 5 are assigned to the group 2, "2" is assigned to the address 3 as the number of repeated occurrences of the group 2, "3" is assigned to the address 4 as the start address of the group 2, and 5 is set to "8" as the end address of the same group 2.

The start address and end address designated by the group sequence data memory 4 are the addresses of the waveform sequence data memory 2,
The start address and end address designated by the waveform sequence data memory 2 are the addresses of the waveform data memory 1.

The operation will be described. First, in synchronization with the clock pulse from the counter 6 (see FIG. 2), each data of the addresses 0 to 2 relating to the group 1 of the group sequence data memory 4 is read out, and the number of times of repeated occurrences is increased. "1" is held in the third latch circuit 4c, and
The start address "0" and the end address "2" are held in the first and second latch circuits 4a and 4b, respectively.

Then, a read address having a start address "0" and an end address "2" is supplied from the second address generator 5 to the waveform sequence data memory 2, whereby addresses 0 to 0 of the same waveform sequence data memory 2 are supplied. Each data of the waveform A is read from No. 2, the number of repetitions "2" is held in the third latch circuit 2c, and the start address "0" and the end address "99" are respectively stored in the first and second latches. It is held in the circuits 2a and 2b.

When the end address "2" is output from the second address generator 5, the comparator 5a
Outputs a coincidence output to the counter 5b, and the count value of the counter 5b becomes 1. In this case, since the number of repetitions is “1”, the operation stop signal is supplied from the counter 5b to the second address generator 5.

As described above, when the data is held in each of the latch circuits 2a to 2c, the read address from the first address generator 3 to the waveform data memory 1 is the start address "0" and the end address "99". Is supplied, whereby the data of the waveform A is read from the waveform data memory 1.

When the end address "99" is output from the first address generator 3, the comparator 3a outputs a coincident output to the counter 3b, and the count value of the counter 3b becomes 1, but in this case, the number of repetition occurrences is increased. "2"
Therefore, the read address having the start address “0” and the end address “99” is again supplied from the first address generator 3 to the waveform data memory 1, and the data of the waveform A is continuously read from the waveform data memory 1. .

In this way, when the data of the waveform A is repeatedly read twice, each data of the addresses 3 to 5 relating to the group 2 of the group sequence data memory 4 is read next, and the number of repetitions "2". Is held in the third latch circuit 4c, and the start address "3" and the end address "8" are held in the first and second latch circuits 4a and 4b, respectively.

As a result, the second address generator 5
A read address having a start address “3” and an end address “8” is supplied from the waveform sequence data memory 2. Along with this, first, each data of the waveform B from the addresses 3 to 5 of the same waveform sequence data memory 2, that is, the number of repeated occurrences “3”, the start address “100” and the end address “199”.
In the same manner as described above, each latch circuit 2c, 2a,
2b, and according to the read address output from the first address generator 3 based on this,
The waveform B data is repeatedly output from the waveform data memory 1 three times.

Next, each data of the waveform C from the addresses 6 to 8 of the waveform sequence data memory 2, that is, the number of times of repetition "1" and the start address "20".
"0" and the end address "299" are held in the respective latch circuits 2c, 2a, 2b, and based on this, the data of the waveform C is read from the waveform data memory 1 according to the read address output from the first address generator 3. It is output once.

In this case, since the number of repetitions of the group 2 of the group sequence data memory 4 is "2", the data of the waveform B is read three times and the data of the waveform C is read once again, as shown in FIG. ),
The waveform data will be read in the order of groups 1, 2 and 2.

In the above embodiment, the three waveforms A, B, and C are taken as an example, and the waveform A is the group 1 and the waveforms B and C are the group 2. However, the combination of the groups is arbitrary. Waveforms A and C are group 1 and waveform B
May be group 2.

In any case, according to the present invention, the capacity of the waveform sequence data memory 2 can be saved.
Incidentally, the waveform data memory stores 100 pieces of waveform data, and assuming that the capacity of the waveform sequence data memory is 100, data is written in the entire memory capacity as shown in FIG. 100 Hz (0.01 seconds), repeat count 1
When the same waveform sequence data memory makes one round, the time until all the waveform data is output is 0.01 (second) × 100 × 33 = 33 (second). On the other hand, as in the present invention, a group sequence data memory is used, and the same data as the waveform sequence data memory as shown in FIG. 6 (repetition occurrence number 10, start address 0, end address 9
When 8) is stored and waveform output is executed, the time required for it is (0.01 (sec) × 100 × 33) × 10 = 330 (sec). This means that the waveform can be output ten times as long as 330 seconds for the same contents of the waveform data memory as in the conventional case. In other words, when outputting the same waveform as the conventional one, according to the present invention, the capacity of the waveform sequence data memory can be saved.

[0038]

As described above, according to the present invention,
Waveform generation control data including the number of times the output waveform is repeatedly generated and the start and end addresses of the output waveform is stored in the waveform sequence data memory, and based on the waveform generation control data, the waveform data is stored in a predetermined order from the waveform data memory. In a waveform generator that reads out digital data of an output waveform and generates a desired output waveform, the waveform generation control data in the waveform sequence data memory is arbitrarily grouped, and a group sequence is placed in a higher order of the waveform sequence data memory. A data memory is provided, and in the same group sequence data memory,
Group control data including the number of repeated occurrences of grouped waveform generation control data for each group and the start address and end address of the same group is stored, and the waveform sequence data memory is controlled by the same group sequence data memory. By doing so, there is an effect that the degree of freedom in creating a sequence of output waveforms can be further increased without increasing the storage capacity of the waveform sequence data memory.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of a waveform generator according to the present invention.

FIG. 2 is a block diagram showing a specific circuit configuration example of the waveform generator.

FIG. 3 is an explanatory diagram showing a state in which waveform generation control data stored in a waveform sequence data memory of the same waveform generator is grouped, and an output waveform as the group.

FIG. 4 is an explanatory view schematically showing the sequence of group control data stored in a group sequence data memory of the waveform generator and waveforms repeatedly output in units of groups.

FIG. 5 is an explanatory diagram showing a state in which waveform generation control data is stored in a waveform sequence data memory according to a conventional method for comparison with the present invention.

6 is an explanatory diagram showing an example of data storage of a group sequence data memory according to the present invention provided above the waveform sequence data memory of FIG.

FIG. 7 is a schematic block diagram showing a conventional example of a waveform generator.

FIG. 8 is a schematic diagram showing waveform data stored in a waveform data memory of the conventional example.

FIG. 9 is a schematic diagram showing waveform generation control data stored in a waveform sequence data memory of the conventional example.

[Explanation of symbols]

 1 waveform data memory 2 waveform sequence data memory 3 first address generator 4 group sequence data memory 5 second address generator

Claims (3)

[Claims] 1. A waveform data memory in which digital data of a plurality of different output waveforms are stored for each designated address range, a number of times the output waveform is repeatedly generated, and a start address and an end address of the same output waveform. A waveform sequence data memory in which waveform generation control data is stored, and a first address generator which gives a read address of the output waveform to the waveform data memory based on the waveform generation control data from the waveform sequence data memory A waveform generator that reads digital data of the output waveform from the waveform data memory according to a predetermined order by the waveform generation control data of the waveform sequence data memory to generate a desired output waveform. Above in memory Waveform generation control data is arbitrarily grouped, and based on the group control data memory that stores group control data that includes the number of repeated occurrences for each group and the start and end addresses of the group, and the group control data. A waveform generator, comprising: a second address generator for outputting a read address of the waveform generation control data to the waveform sequence data memory. 2. The waveform generator according to claim 1, wherein the waveform generation control data in the waveform sequence data memory are grouped over a continuous predetermined address range. 3. The waveform sequence data memory and the group sequence data memory each include first and second latch circuits for holding the start address and the end address, respectively, and a third latch for holding the number of repetitions. A circuit for comparing the address generated from the address generator with the end address held in the second latch circuit, and a match output from the comparator. 2. A counter circuit, which counts the number of times and supplies an operation stop signal to the address generator when the count value reaches the number of times the third latch circuit is repeatedly generated. Waveform generator.